JPS6236921A - Pll type offset frequency synthesis circuit - Google Patents
Pll type offset frequency synthesis circuitInfo
- Publication number
- JPS6236921A JPS6236921A JP60175217A JP17521785A JPS6236921A JP S6236921 A JPS6236921 A JP S6236921A JP 60175217 A JP60175217 A JP 60175217A JP 17521785 A JP17521785 A JP 17521785A JP S6236921 A JPS6236921 A JP S6236921A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- output
- vco
- signal
- phase comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はＰＬＬ方式オフセット周波数合成器に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a PLL type offset frequency synthesizer.
従来オフセット周波数を合成する場合、第５図で示す構
成を取り、オフセット周波数信号をＲＰ正弦波信号でミ
ックスアップした後不要な信号をフィルタに１って取り
除く方法、又はＰＬＬ方式でも第６図の様な構成を用い
ていた。Conventionally, when synthesizing offset frequencies, the configuration shown in Figure 5 is used, the offset frequency signal is mixed up with an RP sine wave signal, and unnecessary signals are removed by a filter, or the PLL method is also used as shown in Figure 6. Various configurations were used.
上述した第１の方法では、入力ＲＦ正弦波信号と、オフ
セット周波数信号を混合した時、出力には、入力ＲＦ正
弦波信号及び入力Ｂ、Ｐ正弦波信号の上下にオフセット
周波数だけ離れた信号が現れる。このため、目的の信号
を得るためには、他の２波を減衰させる狭帯域フィルタ
が必要であるという欠点がある。In the first method described above, when the input RF sine wave signal and the offset frequency signal are mixed, the output is a signal that is separated by the offset frequency above and below the input RF sine wave signal and the input B and P sine wave signals. appear. Therefore, in order to obtain the desired signal, a narrow band filter is required to attenuate the other two waves.
第２の方法では、まず、ＶＣＯの周波数が変った時、ミ
キサーにぶってミックスダウンされた周波数はＩｆｃ
ｆｆｌ となり、その関係に第７図の様になった。In the second method, when the VCO frequency changes, the frequency mixed down by the mixer is
ffl, and the relationship is as shown in Figure 7.
工って、この信号とオフセット周波数信号との位相比較
を行う、位相比較器出力は第８図の様になる。ところで
ＶＣＯは、それに加える制御電圧が高い時、周波数が高
くなり、低い時周波数が低くなる。よって、ＶＣＯの出
力周波数ｆｖが第８図の４の領域にあった場合には、Ｖ
ＣＯ制御電圧が低いのでＶＣＯの出力周波数は下がり、
３と４の領域の間で落ち着く。逆に、ｆｖが２゜３の領
域にあった時はＶＣＯ出力周波数は高くなり、３と４の
領域の間に落ちつく。よって最初のＶＣＯの出力周波数
が、２，３．４の領域にあった場合、最終的にその周波
数はｆｃ＋ｆｏ に落ち着く。しかしながら、第８図の
１の領域にＶＣＯ出力周波数があった場合、ＶＣＯ出力
数は、さらに低くなって行き、ｆｃ＋ｆｏには落ち着か
ない。The output of the phase comparator which compares the phase of this signal with the offset frequency signal is as shown in FIG. By the way, when the control voltage applied to the VCO is high, the frequency becomes high, and when the control voltage applied to it is low, the frequency becomes low. Therefore, if the output frequency fv of the VCO is in the region 4 in FIG.
Since the CO control voltage is low, the VCO output frequency decreases,
It settles between areas 3 and 4. Conversely, when fv is in the 2°3 range, the VCO output frequency becomes high and settles between the 3 and 4 ranges. Therefore, if the initial VCO output frequency is in the 2.3.4 range, the frequency will eventually settle to fc+fo. However, when the VCO output frequency is in the region 1 in FIG. 8, the VCO output number becomes even lower and does not settle to fc+fo.
工って動作が不安定であるという短所があった。The disadvantage was that the operation was unstable.
本発明のＰＬＬ方式オフセット周波数合成回路は、ＶＣ
Ｏ出力を外部からのＲＦ正弦波（ＣＷ）信号に工ってミ
ックスダウンした信号とオフセット周波数信号との位相
比較をする第１の位相比較−３シフ＼
器、ＶＣＯ出力と外部からのＲＦＣＷ信号との位相比較
をする第２の位相比較器第１の位相比較器出力と第２の
位相比較器出力の大きい方を選ぶ最大値回路、及び、最
大値回路の出力を制御電圧とするＶＣＯを具備する。The PLL type offset frequency synthesis circuit of the present invention has a VC
The first phase comparison-3 shifter converts the O output into an external RF sine wave (CW) signal and compares the phase of the mixed down signal and the offset frequency signal, the VCO output and the external RFCW signal. a second phase comparator that compares the phase with the second phase comparator; a maximum value circuit that selects the larger of the first phase comparator output and the second phase comparator output; Be equipped.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の第１の実施例である。図で、１は位相
比較器Ｉでオフセット周波数入力の、ＶＣＯ出力をＲＦ
ＣＷ入力でミックスダウンした信号に対する位相の遅れ
に比例した電圧を出力する。３は最大値回路で位相比較
器１．１゛出力のうち高い電圧の方を出力する。４は希
望する出力周波数、つまりＲＦＣＷ入力周波数とオフセ
ット周波数の和の周波数を出力できるＶＣＯで、かつ電
圧に比例して周波数が高くなるものである。５はＲＦＣ
Ｗ入力信号でＶＣＯ出力をミックスダウンするミキサー
である。FIG. 1 shows a first embodiment of the invention. In the figure, 1 is the phase comparator I, which inputs the offset frequency and converts the VCO output to RF.
Outputs a voltage proportional to the phase delay with respect to the signal mixed down with CW input. 3 is a maximum value circuit which outputs the higher voltage among the outputs of the phase comparator 1.1. 4 is a VCO that can output a desired output frequency, that is, the sum of the RFCW input frequency and the offset frequency, and the frequency increases in proportion to the voltage. 5 is RFC
This is a mixer that mixes down the VCO output using the W input signal.
次に第２図〜第４図を用いてその動作を説明する。まず
、位相比較器１１１？、入力される信号は１周−１＝・
。Next, the operation will be explained using FIGS. 2 to 4. First, phase comparator 111? , the input signal is 1 round - 1 = ・
.
波数がｆ。のオフセット周波数信号と、周波数ｆｖのＶ
ＣＯ出力を、周波数ｆｃのＲＦＣＷ入力でミックスダウ
ンした周波数ｆｍ＝ｆＶ ｆＣ下る信号が入力される
。よってＶＣＯの周波数を変化させた時、ｆｃ ｆｏ
＜ｆｖ＜ｆｃ＋ｆｏ の時にはｆｍ（ｆｏ となり
、ｆｖ≦ｆｃ−ｆｏ又はｆｃ＋ｆｏ≦ｆｖの時には、
ｆｍ＞ｆｏとなるので、ＶＣＯ出力周波数と位相比較
器Ｉ出力の出力電圧の関係は第２図の様になる。同様に
ＶＣＯ出力周波数と位相比較器■出力の出力電圧の関係
は第３図の様になる。The wave number is f. offset frequency signal of frequency fv and V of frequency fv
A signal whose frequency is fm=fV fC, which is obtained by mixing down the CO output with the RFCW input of frequency fc, is input. Therefore, when changing the frequency of the VCO, fc fo
When <fv<fc+fo, fm(fo), and when fv≦fc−fo or fc+fo≦fv,
Since fm>fo, the relationship between the VCO output frequency and the output voltage of the phase comparator I output is as shown in FIG. Similarly, the relationship between the VCO output frequency and the output voltage of the phase comparator output is as shown in FIG.
この様な位相比較器１．Ｉｆの出力を最大値回路３に入
力することに工って、ＶＣＯ出力周波数と、最大値回路
出力３０の関係は第４図の様になる。Such a phase comparator 1. By inputting the output of If to the maximum value circuit 3, the relationship between the VCO output frequency and the maximum value circuit output 30 becomes as shown in FIG.
よって、■ＣＯ出力周波数がｆｃ＋ｆｏの時にのみＰＬ
Ｌがロックすることになる。Therefore, ■PL only when the CO output frequency is fc+fo
L will lock.
以上説明したような構成をとることにエフ、本発明は、
フィルタなどの必要のないＰＬＬシンセサイザ一方式で
、かつＶＣＯの可変周波数範囲に制限を設ける必要のな
いオフセット周波数合成回路を実現できる。In adopting the configuration as explained above, the present invention has the following features:
It is possible to realize an offset frequency synthesis circuit that uses a PLL synthesizer without the need for a filter and does not require any restriction on the variable frequency range of the VCO.
第１図は本発明の一実施例を示す図である。第２図はＶ
ＣＯ出力周波数と位相比較器Ｉ出力の関係を示した図、
第３図は■ＣＯ出力周波数と位相比較器■出力の関係を
示した図、第４図はＶＣＯ出力周波数と最大値回路出力
の関係を示した図、第５，６図は従来の例を示す図、第
７，８図は従来の動作を説明するだめの図。
図で、１・・・・・・位相比較器！、２・−・・・・位
相比較器■、３・・・・・・最大値回路、４・・・・・
・ＶＣｏ、５−・・・・・ミキサー。
−−γ−
３ｅ−
第４図FIG. 1 is a diagram showing an embodiment of the present invention. Figure 2 shows V
A diagram showing the relationship between CO output frequency and phase comparator I output,
Figure 3 shows the relationship between CO output frequency and phase comparator output, Figure 4 shows the relationship between VCO output frequency and maximum value circuit output, and Figures 5 and 6 show conventional examples. The diagrams shown in FIGS. 7 and 8 are only diagrams for explaining the conventional operation. In the figure, 1... Phase comparator! , 2... Phase comparator ■, 3... Maximum value circuit, 4...
- VCo, 5-...mixer. −−γ− 3e− Figure 4
Claims (1)
号を外部からのＲＦ正弦波信号によって周波数変換する
ミキサーと、前記ミキサーからのミックスダウンした信
号と外部からのオフセット周波数信号との位相比較をす
る第１の位相比較器と、前記ＶＣＯから出力信号と前記
ＲＦ正弦波信号との位相比較をする第２の位相比較器と
、前記第１の位相比較器の出力と第２の位相比較器の出
力の大きい出力を選択し前記ＶＣＯへ制御信号として供
給する最大値回路とを具備することを特徴徴とするＰＬ
Ｌ方式オフセット周波数合成器。A voltage controlled oscillator (VCO), a mixer that converts the frequency of the output signal from the VCO using an external RF sine wave signal, and compares the phase of the mixed down signal from the mixer and the external offset frequency signal. a first phase comparator; a second phase comparator that compares the phases of the output signal from the VCO and the RF sine wave signal; A PL characterized in that it comprises a maximum value circuit that selects a large output and supplies it to the VCO as a control signal.
L-type offset frequency synthesizer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60175217A JPS6236921A (en) | 1985-08-09 | 1985-08-09 | Pll type offset frequency synthesis circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60175217A JPS6236921A (en) | 1985-08-09 | 1985-08-09 | Pll type offset frequency synthesis circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6236921A true JPS6236921A (en) | 1987-02-17 |
Family
ID=15992338
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60175217A Pending JPS6236921A (en) | 1985-08-09 | 1985-08-09 | Pll type offset frequency synthesis circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6236921A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0273722A (en) * | 1988-09-09 | 1990-03-13 | Nec Corp | Pll system offset frequency synthesizing circuit |
| JPH08324779A (en) * | 1995-06-07 | 1996-12-10 | Murata Mach Ltd | Branching structure of roller conveyor |
| JPH08324780A (en) * | 1995-06-07 | 1996-12-10 | Murata Mach Ltd | Branching structure of roller conveyor |
| US6154097A (en) * | 1998-04-17 | 2000-11-28 | Nec Corporation | PLL oscillating circuit including oscillating circuit with mutual conductance controlled |
-
1985
- 1985-08-09 JP JP60175217A patent/JPS6236921A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0273722A (en) * | 1988-09-09 | 1990-03-13 | Nec Corp | Pll system offset frequency synthesizing circuit |
| JPH08324779A (en) * | 1995-06-07 | 1996-12-10 | Murata Mach Ltd | Branching structure of roller conveyor |
| JPH08324780A (en) * | 1995-06-07 | 1996-12-10 | Murata Mach Ltd | Branching structure of roller conveyor |
| US6154097A (en) * | 1998-04-17 | 2000-11-28 | Nec Corporation | PLL oscillating circuit including oscillating circuit with mutual conductance controlled |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH06244635A (en) | Microwave oscillator | |
| JP2001127554A (en) | Voltage controlled oscillator | |
| JPS6236921A (en) | Pll type offset frequency synthesis circuit | |
| EP1760877A1 (en) | Reconfigurable signal modulator | |
| JPS6363137B2 (en) | ||
| JPH0923158A (en) | Frequency synthesizer | |
| JPS6359116A (en) | Pll frequency synthesizer | |
| JP3091423B2 (en) | Accurate digital phase shifter | |
| CN110729996A (en) | Phase-locked loop circuit and method for miniaturization double phase locking | |
| JP2002208858A (en) | Frequency synthesizer and method for generating frequency | |
| JP2000332539A (en) | Frequency synthesizer | |
| JP2002076889A (en) | Frequency synthesizer | |
| EP0881775A1 (en) | A clock generator | |
| JP2631009B2 (en) | PLL circuit | |
| EP0409127A2 (en) | Phase-locked loop type frequency synthesizer having improved loop response | |
| JPS6238352Y2 (en) | ||
| JPH0374930A (en) | Phase controlled type oscillator | |
| FI86119B (en) | Device for the creation of two oscillator signals | |
| JPS6238351Y2 (en) | ||
| JPH03186017A (en) | Phase locked oscillation circuit | |
| JPH02214222A (en) | Voltage controlled oscillator | |
| JPH0537370A (en) | Frequency synthesizer | |
| JPH09214336A (en) | Double comparison type synthesizer oscillator | |
| JPH0362619A (en) | Frequency synthesizer | |
| JPH04222118A (en) | Phase locked oscillator |