JPS62298136A - Manufacture of semiconductor element - Google Patents
Manufacture of semiconductor elementInfo
- Publication number
- JPS62298136A JPS62298136A JP14032586A JP14032586A JPS62298136A JP S62298136 A JPS62298136 A JP S62298136A JP 14032586 A JP14032586 A JP 14032586A JP 14032586 A JP14032586 A JP 14032586A JP S62298136 A JPS62298136 A JP S62298136A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- contact hole
- resist mask
- substrate
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000010410 layer Substances 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000007747 plating Methods 0.000 claims abstract description 19
- 238000009792 diffusion process Methods 0.000 claims abstract description 15
- 239000011229 interlayer Substances 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims description 21
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 238000007772 electroless plating Methods 0.000 claims description 10
- 230000004888 barrier function Effects 0.000 claims description 6
- 239000011247 coating layer Substances 0.000 claims description 6
- 239000000470 constituent Substances 0.000 claims description 4
- 238000011049 filling Methods 0.000 claims description 2
- 239000007769 metal material Substances 0.000 claims description 2
- 239000012535 impurity Substances 0.000 abstract description 10
- 230000003197 catalytic effect Effects 0.000 abstract description 9
- 238000005530 etching Methods 0.000 abstract description 4
- 239000000463 material Substances 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000001771 vacuum deposition Methods 0.000 abstract 1
- 229910045601 alloy Inorganic materials 0.000 description 7
- 239000000956 alloy Substances 0.000 description 7
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000035515 penetration Effects 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000003054 catalyst Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 101100269850 Caenorhabditis elegans mask-1 gene Proteins 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052705 radium Inorganic materials 0.000 description 1
- HCWPIIXVSYCSAN-UHFFFAOYSA-N radium atom Chemical compound [Ra] HCWPIIXVSYCSAN-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
〔産業上の利用分野〕
本発明は半導体素子の製造方法に係り、脣に多層配線形
成時のコンタクトホールの埋め込み方法に関する。Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of burying contact holes when forming multilayer wiring.
以下、第３図に基き従来のコンタクトホールの埋め込み
方法について説明する。Hereinafter, a conventional contact hole burying method will be explained based on FIG.
まず同図（ａ）に示す如く、Ｓｉ基板３１にトランジス
タ等を構成する為の不純物拡散領域３２を形成し、次に
ＣＶＤ等の方法を用いてＰＳＧ、ＢＰＳＧ等から成る層
間絶縁膜３３を堆積する。次いでＲＩＥＫよって、この
層間絶縁膜３３にコンタクトホール３４を開孔し念後、
アニール渦理を施してコンタクトホール３４をリフロー
させる。この後、ス・ぞツタ等の方法でＡｊ −Ｓｉ系
合金をｔｚ Ｍ Ｌ／、これに周知のホトリソ・エツチ
ングを施して配線層３５を成す。First, as shown in FIG. 3A, an impurity diffusion region 32 for forming a transistor etc. is formed on a Si substrate 31, and then an interlayer insulating film 33 made of PSG, BPSG, etc. is deposited using a method such as CVD. do. Next, a contact hole 34 is opened in this interlayer insulating film 33 by RIEK, and then,
The contact hole 34 is reflowed by annealing. Thereafter, a wiring layer 35 is formed by forming an Aj--Si alloy using a method such as Szotsuta, and subjecting it to well-known photolithography and etching.
ここにおいて、半導体素子の集積度の向上に伴って微細
化が進むにつれ、コンタクトホール３４のアスペクト比
（径に対する深さの比）が大きくなシ、同図（ｂ）の如
く、コンタクトホール３４にリフローを施しても配線層
３５のコンタクトホール３４でのステップカバレージが
悪くなり、抵抗の増大１氏切れ等の生ずることが懸念さ
れる。As the degree of integration of semiconductor devices increases and miniaturization progresses, the aspect ratio (ratio of depth to diameter) of the contact hole 34 becomes larger, as shown in FIG. Even if reflow is performed, there is a concern that the step coverage in the contact hole 34 of the wiring layer 35 will be poor, and that resistance will increase and breakage by one degree or the like will occur.
これまで、この解決策として種々のコンタクトホールの
埋め込み方法が提案されてきている。例エバ、メタルの
バイアススパッタリング法による平担化配線技術、タン
グステン（Ｗ）の選択ＣＶＤ技術等が検討されている。Up to now, various contact hole burying methods have been proposed as a solution to this problem. For example, a planarization wiring technology using a metal bias sputtering method, a selective CVD technology for tungsten (W), etc. are being considered.
しかしながらメタルのバイアスス・ンツタ法や、Ｗの選
択ＣＶＤ法等の現在検討されているコンタクトホールの
埋め込み技術は、スルーグツトやダメージ、更にコンタ
クトホールへの埋め込み形状等にまだ問題が残っており
、技術的に満足される段階に至っていない・
従って、本発明は以上述べ友問題全解消し、ダメージフ
リーで高スルーグツトが得られ、しかも配線層を高平担
性を以って形成できるコンタクトホールの埋め込み方法
を実現した半導体素子の製造方法を提供することを目的
とする。However, contact hole embedding techniques currently being considered, such as the metal bias sintering method and the W selective CVD method, still have problems with throughput, damage, and the shape of the contact hole embedding, resulting in technical difficulties. Therefore, the present invention provides a method for burying contact holes that can solve all of the above-mentioned problems, provide damage-free and high throughput, and form wiring layers with high flatness. The purpose of this invention is to provide a method of manufacturing a semiconductor device that has been realized.
本発明に係る半導体素子の製造方法は、半導体基板上に
層間絶縁膜、レジストマスクを順次形成しこのレジスト
マスクを介して上記層間絶線膜にコンタクトホールを開
孔する工程と、基板全面に少なくとも触媒活性層を含む
４′４．性の被膜層を被着する工程と、上記レジストマ
スクを除去することにより上記コンタクトホール内にの
み上記被膜層を残す工程と、基板を無１！解めっき浴に
浸漬し上記コンタクトホールをめっき層で埋め込み、こ
の後配線層を形成する工程とを含むようにし友ものであ
る。The method for manufacturing a semiconductor device according to the present invention includes the steps of sequentially forming an interlayer insulating film and a resist mask on a semiconductor substrate, and opening a contact hole in the interlayer insulating film through the resist mask, and at least 4'4. containing a catalytically active layer; a step of depositing a transparent coating layer; a step of leaving the coating layer only in the contact hole by removing the resist mask; The contact hole is immersed in a plating bath to fill the contact hole with a plating layer, and then a wiring layer is formed.
以上のように、本発明によれば、少なくとも触媒活性層
を含む導電性の被膜層を、レジストマスク除去によりリ
フトオフ的にコンタクトホール内にのみ残すようにし友
ので、後工程の無電解めっき工程においてこの被膜層を
介してコンタクトホールを選択的にめっき層で作業性良
く容易に埋め込むことができる。As described above, according to the present invention, the conductive film layer including at least the catalytic active layer is left only in the contact hole for lift-off by removing the resist mask, so that it can be used in the subsequent electroless plating process. Contact holes can be selectively filled with a plating layer through this coating layer with good workability and ease.
また、コンタクトホールの埋め込みは無電解めっき法で
行うようにしているので、下地の半導体基板に対しダメ
ージ？与えることはない。Also, since the contact holes are filled using electroless plating, there is a risk of damage to the underlying semiconductor substrate. I won't give anything.
また特に、上記被膜層として上層の触媒活性層の他にめ
っき層と下地の半導体基板の各主要構成元素の拡散係数
が小さくなるような金属材料を用いてバリア金属層を設
けるようにすると、相互拡散が防止されめっき層の主要
構成元素の半導体基板への浸透を抑制することができる
。In particular, if a barrier metal layer is provided as the coating layer in addition to the upper catalytically active layer using a metal material that reduces the diffusion coefficient of each of the main constituent elements of the plating layer and the underlying semiconductor substrate, Diffusion is prevented and penetration of the main constituent elements of the plating layer into the semiconductor substrate can be suppressed.
更に、コンタクトホールを導電性の被膜層及びめっき層
とで埋め込むようにしているので、高平担性を有する配
線層を形成できる。Furthermore, since the contact hole is filled with a conductive film layer and a plating layer, a wiring layer having high flatness can be formed.
以下、第１図及び第２図に基き本発明の実施例を詳細に
説明する。Hereinafter, embodiments of the present invention will be described in detail based on FIGS. 1 and 2.
まず第１図に基き、本発明の第１の実施例を説明する。First, a first embodiment of the present invention will be described based on FIG.
Ｓｉ基板から成る半導体基板１１の所定個所に。At a predetermined location on a semiconductor substrate 11 made of a Si substrate.
トランジスタ等を構成する為の不純物拡散領域１２を形
成し、次Ｋ例えばＣＶＤ法を用いてＰＳＧ。An impurity diffusion region 12 for forming a transistor or the like is formed, and then PSG is formed using, for example, a CVD method.
ＢＰＳＧ等の層間ｔ５縁膜１３を６０００＾程度堆埃す
る。次いで１周知のホトリソ技術を用いてレジストマス
ク１４を形成し、更にこのレジストマスク１４全通して
ＲＩＥによ！ｌ１層間絶縁膜１３に選択エツチングを施
し、上記不純物拡散領域１２−Ｈにコンタクトホール１
５を開口する。そして上記レジストマスク１４を残しｆ
ｃまま触媒活性用材料として・ぐラジウム（Ｐｄ）を用
い、真空蒸着によりこれを基板全面に１００〜２００λ
程度夜着し触媒活性層１６を形成すると同図（ａ）に示
す如き断面梅造が得られる。Approximately 6000^ of dust is deposited on the interlayer T5 film 13 made of BPSG or the like. Next, a resist mask 14 is formed using a well-known photolithography technique, and then the entire resist mask 14 is passed through by RIE! The l1 interlayer insulating film 13 is selectively etched to form a contact hole 1 in the impurity diffusion region 12-H.
Open 5. Then, leave the resist mask 14 as f
Using radium (Pd) as a material for catalytic activation, a layer of 100 to 200 λ was applied to the entire surface of the substrate by vacuum evaporation.
When the catalytic active layer 16 is formed overnight, a cross-sectional Ume-zukuri shape as shown in FIG.
次に同図（ｂ）に示すように、リフトオフ的にレジスト
マスク１４を除去するとコンタクトホール１５にのみ選
択的にＰｄの触媒活性Ｒ１１１６が残ることとなる。Next, as shown in FIG. 3B, when the resist mask 14 is removed by lift-off, the Pd catalytic activity R1116 remains selectively only in the contact hole 15.
しかる後に同図（Ｃ）に示す如く、基板をＮｉ系無電解
めっき浴に浸し、層間絶縁膜１３と段差が生じない程度
にＮｉから成るめっき層１７ｔ−形成する。Thereafter, as shown in FIG. 2C, the substrate is immersed in a Ni-based electroless plating bath to form a plating layer 17t made of Ni to such an extent that there is no difference in level from the interlayer insulating film 13.
なお、この場合の無電尊めっき法としては、例えば文献
の特公昭５５−４８１０３号公報に開示される如き手法
を用いる。この後、ス・ぐツタ法を用いてＡｔ−３ｉ系
合金ｔ−６０００＾程度被着し、ホ） ＩＪンエツチン
グを行い上記めっき層１７と接続するＡｊ −８ｉ系合
金から成る配ＭＪ７ｍ１８ｔ−形成する。In this case, as the electroless plating method, a method as disclosed in Japanese Patent Publication No. 55-48103 is used, for example. After this, an At-3i alloy of about t-6000^ is deposited using the S-GUTSUTA method, and e) IJ etching is performed to form a MJ7m18t made of an Aj-8i alloy that connects with the plating layer 17. .
次に第２図に基き、本発明の第２の実施例を説明する。Next, a second embodiment of the present invention will be described based on FIG.
なお、第１図との同−ｔｅは相当個所には同一符号を付
すこととする・
まず第２図（ａ） Ｋ示す如く、Ｓｉ基板から成る半導
体基板１１上に不純物拡散領域１２を形成し、ＣＶＤ法
等で層間絶縁膜１３を堆積する。次いでレジストマスク
１４を形成し、これを介してＲＩＥにより層間絶縁膜１
３に選択エツチングを施し、上記不純物拡散領域１２上
にコンタクトホール１５を開孔する。Note that the same numbers as those in FIG. 1 are given to corresponding parts. First, as shown in FIG. 2(a) K, an impurity diffusion region 12 is formed on a semiconductor substrate 11 made of a Si substrate. , an interlayer insulating film 13 is deposited by a CVD method or the like. Next, a resist mask 14 is formed, and the interlayer insulating film 1 is formed by RIE through this.
3 is subjected to selective etching to form a contact hole 15 above the impurity diffusion region 12.
続いて同図（ｂ）に示すように、上記レジストマスク１
４を残し比状態で、初めにＳｉとＮｉの相方の拡散係数
が小さくなるような金属、例えばＴｉＮ。Subsequently, as shown in FIG. 2(b), the resist mask 1 is
A metal such as TiN, in which the diffusion coefficient of Si and Ni is initially small in the ratio state with 4 remaining.
Ｗ−Ｔｉをス・ぐツタ法等で５００〜１０００λ程度全
面に被着してバリア金属層１６ａと成す。次にＰｄを１
００〜２００λ程度全面に真空蒸着して触媒活性層１６
を形成する。A barrier metal layer 16a is formed by depositing W--Ti on the entire surface to a thickness of about 500 to 1000 λ using the sintering method or the like. Next, Pd is 1
A catalytic active layer 16 is vacuum-deposited on the entire surface of about 00 to 200λ.
form.
そして同図（ｃ）のように、リフトオフ的にレジストマ
スク１４を除去すると、コンタクトホール１５にのみ触
媒活性層（Ｐｄ）１６及びバリア金属層（ＴｉＮ 、
Ｗ−Ｔｉ ） １６ ａの２層膜が残ルコととｆｉル。When the resist mask 14 is removed by lift-off as shown in FIG.
The two-layer film of W-Ti) 16a remains.
しかる後に、基板をＮｉ系無電解めっき浴に浸漬するこ
とにより、コンタクトホール１５内ｋ Ｎ ｉ系合金か
ら成るめっき層１７で略完全に埋め込む。Thereafter, by immersing the substrate in a Ni-based electroless plating bath, the inside of the contact hole 15 is almost completely filled with a plating layer 17 made of a kNi-based alloy.
次にＡｊ−３ｉ系合金全真空蒸着しこれを・セターニン
グすると、十分な平担性を有する配線層１８を形成する
ことができる。Next, an Aj-3i alloy is deposited in full vacuum and then settered to form a wiring layer 18 having sufficient flatness.
以上述べた第２の実施例によれば、コンタクトホール１
５の形成部分において下地の不純物拡散領域１２と上層
のＰｄ触媒活性層１６との間にＴｉＮ。According to the second embodiment described above, the contact hole 1
5, between the underlying impurity diffusion region 12 and the upper Pd catalyst active layer 16.
Ｗ−Ｔｉ等から成るバリア金属層１６ａｋ設けるように
しているので、不純物拡散領域１２の８１と無電解めっ
き法で埋め込んだＮｉ系合金から成るめっき層１７のＮ
ｉとの相互拡散を防止できる。発明者らの鋭意なる実験
によれば、不純物拡散領域１２へのＮｉの浸透は無く、
この為ス・ンイクも生ぜず短絡によるリークを完全に防
止できるという結果か得られている。Since the barrier metal layer 16ak made of W--Ti etc. is provided, the N of the plating layer 17 made of Ni-based alloy buried in the impurity diffusion region 12 by electroless plating is
Mutual diffusion with i can be prevented. According to the inventors' extensive experiments, there was no penetration of Ni into the impurity diffusion region 12.
For this reason, leaks caused by short circuits can be completely prevented without causing leakage.
以上詳細に説明したように、本発明によれば、半導体基
板上に開孔されたコンタクトホールに少なくとも触媒活
性層を含む導電性の被膜層を残し、これ全弁して無電解
めっき法によりコンタクトホールをめつき層で選択的に
埋め込むようにしてい一般に無電解めっき法は、下地に
対しダメージもなく多量処理が可能であると共に析出金
属の均一性も良いことから、本発明でにダメージフリー
で高スルーグツトｅ以って半導体基板上のコンタクトホ
ールの埋め込みを行うことができるという効果がろる。As described in detail above, according to the present invention, a conductive film layer containing at least a catalytically active layer is left in a contact hole formed on a semiconductor substrate, and the conductive film layer is completely closed and contacted by electroless plating. Holes are selectively filled with a plating layer.Generally, electroless plating allows for large quantities of metal to be processed without causing damage to the base, and the deposited metal has good uniformity. The advantage is that a contact hole on a semiconductor substrate can be filled with a high throughput.
またコンタクトホールをめっき層で埋め込むようにして
いることから、従来のようにコンタクトホールをフロー
する必要がないことと相まって低温処理化が実現できる
と共に微細・９ターンを形成できるという効果がある。In addition, since the contact hole is filled with a plating layer, there is no need to flow through the contact hole as in the conventional method, and together with this, low-temperature processing can be realized and nine fine turns can be formed.
更に、めつき眉による埋め込み方法を採っていることか
ら高平担性の配線層を形成でき、段切れ等を回避できる
という信頼性上の効果もある。Furthermore, since a embedding method using a glazed eyebrow is adopted, a highly flat wiring layer can be formed, and there is also an effect in terms of reliability in that step breakage and the like can be avoided.
まｆｃ特に触媒活性層を、バリア金属層を弁じてコンタ
クトホール内の半導体基板上に形成するようにすると、
めっき層の主要構成元素の半導体基板への浸透が抑制さ
れるので、ス・母イクも生ぜず短絡によるリークを防止
できる。この為、浅い接合を有する半導体素子も歩留り
良く製造でき、無電解めっき埋め込み法の適用範囲を拡
めることができるという効果もある。In particular, if a catalytically active layer is formed on the semiconductor substrate within the contact hole using a barrier metal layer,
Since penetration of the main constituent elements of the plating layer into the semiconductor substrate is suppressed, leakage due to short circuits can be prevented without causing any leakage. Therefore, semiconductor elements having shallow junctions can be manufactured with good yield, and the range of application of the electroless plating filling method can be expanded.
第１図は本発明の第１の実施例を説明する工程断面図、
第２図は本発明の第２の実施例を説明する工程断面図、
第３図は従来例の説明図である。
１１・・・半導体基板（Ｓｉ基板）、１２・・・不純物
拡散領域、１３−・・層間絶縁膜（ＰＳＧ、ＢＰＳＧ）
、１４・・・レジストマスク、１５・・−コンタクトホ
ール、１６・・・触媒活性層（Ｐｄ）、１６ａ・・・バ
リア金属層（ＴｉＮ 、 Ｗ−Ｔｉ ）、１７・・・め
っき層（Ｎｉ 、 Ｎｉ系合金）、１８・・・配線層（
Ａｊ−８ｉ系合金）。
・じ、；、、、、ｔ ”；＋
第２図FIG. 1 is a process sectional view explaining the first embodiment of the present invention;
FIG. 2 is a process sectional view explaining a second embodiment of the present invention;
FIG. 3 is an explanatory diagram of a conventional example. 11... Semiconductor substrate (Si substrate), 12... Impurity diffusion region, 13-... Interlayer insulating film (PSG, BPSG)
, 14... Resist mask, 15...-Contact hole, 16... Catalyst active layer (Pd), 16a... Barrier metal layer (TiN, W-Ti), 17... Plating layer (Ni, Ni-based alloy), 18... wiring layer (
Aj-8i alloy).・J,;,,,,t ”;+ Figure 2
Claims (2)
クを順次形成すると共に、このレジストマスクを介して
上記層間絶縁膜にコンタクトホールを開孔する工程、 （ｂ）基板全面に少なくとも触媒活性層を含む導電性の
被膜層を形成する工程、 （ｃ）上記レジストマスクを除去することにより、上記
コンタクトホール内にのみ上記被膜層を残す工程、 （ｄ）基板を無電解めつき浴に浸漬して上記コンタクト
ホールをめつき層で埋め込み、この後配線層を形成する
工程 とを含むことを特徴とする半導体素子の製造方法。(1) (a) A step of sequentially forming an interlayer insulating film and a resist mask on a semiconductor substrate, and opening a contact hole in the interlayer insulating film through this resist mask, (b) At least catalytically active on the entire surface of the substrate. (c) removing the resist mask to leave the coating layer only in the contact hole; (d) immersing the substrate in an electroless plating bath. A method for manufacturing a semiconductor device, comprising the steps of: filling the contact hole with a plating layer; and then forming a wiring layer.
板の各主要構成元素の拡散係数が小さくなるような金属
材料を用いたバリア金属層を介して、上記触媒活性層を
形成するようにしたことを特徴とする特許請求の範囲第
１項記載の半導体素子の製造方法。(2) The coating layer forms the catalytically active layer through a barrier metal layer using a metal material that reduces the diffusion coefficient of each main constituent element of the plating layer and the underlying semiconductor substrate. A method for manufacturing a semiconductor device according to claim 1, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14032586A JPS62298136A (en) | 1986-06-18 | 1986-06-18 | Manufacture of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14032586A JPS62298136A (en) | 1986-06-18 | 1986-06-18 | Manufacture of semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62298136A true JPS62298136A (en) | 1987-12-25 |
Family
ID=15266191
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14032586A Pending JPS62298136A (en) | 1986-06-18 | 1986-06-18 | Manufacture of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62298136A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63229840A (en) * | 1987-03-19 | 1988-09-26 | Nec Corp | Formation of multilayer interconnection |
| US5227332A (en) * | 1989-12-02 | 1993-07-13 | Lsi Logic Corporation | Methods of plating into holes and products produced thereby |
| JPH06177126A (en) * | 1992-12-01 | 1994-06-24 | Alps Electric Co Ltd | Formation of multilayer thin film |
| WO1995002901A1 (en) * | 1993-07-15 | 1995-01-26 | Astarix, Inc. | Top level via structure for programming prefabricated multi-level interconnect |
| JP2010517280A (en) * | 2007-01-24 | 2010-05-20 | ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング | Electronic components |
| WO2015076358A1 (en) * | 2013-11-21 | 2015-05-28 | 株式会社ニコン | Wiring-pattern manufacturing method and transistor manufacturing method |
-
1986
- 1986-06-18 JP JP14032586A patent/JPS62298136A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63229840A (en) * | 1987-03-19 | 1988-09-26 | Nec Corp | Formation of multilayer interconnection |
| US5227332A (en) * | 1989-12-02 | 1993-07-13 | Lsi Logic Corporation | Methods of plating into holes and products produced thereby |
| JPH06177126A (en) * | 1992-12-01 | 1994-06-24 | Alps Electric Co Ltd | Formation of multilayer thin film |
| WO1995002901A1 (en) * | 1993-07-15 | 1995-01-26 | Astarix, Inc. | Top level via structure for programming prefabricated multi-level interconnect |
| JP2010517280A (en) * | 2007-01-24 | 2010-05-20 | ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング | Electronic components |
| WO2015076358A1 (en) * | 2013-11-21 | 2015-05-28 | 株式会社ニコン | Wiring-pattern manufacturing method and transistor manufacturing method |
| JPWO2015076358A1 (en) * | 2013-11-21 | 2017-03-16 | 株式会社ニコン | Wiring pattern manufacturing method and transistor manufacturing method |
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