JPS62293751A - Capacitor - Google Patents
CapacitorInfo
- Publication number
- JPS62293751A JPS62293751A JP13767486A JP13767486A JPS62293751A JP S62293751 A JPS62293751 A JP S62293751A JP 13767486 A JP13767486 A JP 13767486A JP 13767486 A JP13767486 A JP 13767486A JP S62293751 A JPS62293751 A JP S62293751A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline
- layer
- capacitor
- capacitance
- linear patterns
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 36
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 33
- 238000000034 method Methods 0.000 abstract description 8
- 230000002093 peripheral effect Effects 0.000 abstract description 3
- 238000007493 shaping process Methods 0.000 abstract 2
- 239000004065 semiconductor Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
〔産業上の利用分野〕
本発明は、半導体装置に関するもので、特に半導体集積
回路等に作り込むキャパシタに関する。Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a capacitor built into a semiconductor integrated circuit or the like.
本発明は、半導体装置等に使用される第１導電層・誘電
体層・第２導電層からなるキャパシタに於いて、−第１
導電層を互いに間隔をあけた複数の線状パターンに分け
、かつそれを電気的に接続し、これらの第１導電層側壁
部に容量蓄積部を設けることによって、占有面積が小さ
くて製造の容易なキャパシタを提供したものである。The present invention provides a capacitor including a first conductive layer, a dielectric layer, and a second conductive layer used in a semiconductor device, etc.
By dividing the conductive layer into a plurality of linear patterns spaced apart from each other, electrically connecting them, and providing a capacitance storage section on the side wall of the first conductive layer, the area occupied is small and manufacturing is easy. This provides a capacitor with a wide range of functions.
第３図Ａ、 Ｂに２層多結晶シリコン構造を用いた従来
のキャパシタの例が示されている。これは、単結晶Ｓｉ
等の基板１上に第１多結晶Ｓｉ層をキャパシタの第１電
極として形成し、その上に厚さＤのＳｉＯ□等の絶縁層
３を設け、さらにその上に第２多結晶Ｓｉ層４を設けた
多結晶Ｓｉ−多結晶Ｓｉキャパシタである。第３図Ａの
平面図に示されるように、多結晶Ｓｉ層をａｘａの正方
形とし、絶キ（膜りの誘電率をεとすると、このキャパ
シタの容量はεａ２／Ｄとなる。An example of a conventional capacitor using a two-layer polycrystalline silicon structure is shown in FIGS. 3A and 3B. This is single crystal Si
A first polycrystalline Si layer is formed as the first electrode of a capacitor on a substrate 1 such as, an insulating layer 3 of SiO□ or the like having a thickness of D is provided thereon, and a second polycrystalline Si layer 4 is further formed on it. This is a polycrystalline Si-polycrystalline Si capacitor. As shown in the plan view of FIG. 3A, if the polycrystalline Si layer has a square shape of axa and the dielectric constant of the film is ε, then the capacitance of this capacitor is εa2/D.
従来のキャパシタの構造では、大きな容量を得るために
は大面積を必要とし・今後パターンが微細化していく半
導体技術に於いては従来のキャパシタ構造は不利な状況
にある。つまり多結晶Ｓｉ −多結晶Ｓｉ間主キヤパシ
タ於いては、基板シリコンに於ける酸化膜程薄くて良質
の熱酸化膜を形成することが困難であるために、熱酸化
膜厚を一定以下の厚さにして容量を大きくすることがで
きない。Conventional capacitor structures require a large area in order to obtain large capacitance, and are at a disadvantage in semiconductor technology where patterns will become finer in the future. In other words, in the main capacitor between polycrystalline Si and polycrystalline Si, it is difficult to form a thermal oxide film as thin and high quality as the oxide film on the substrate silicon, so the thermal oxide film thickness is kept below a certain level. It is not possible to increase the capacity at the same time.
このため、大容量を得るためには誘電体層の厚さを薄く
するのではなく多結晶Ｓｉ電極の面積を大きくする必要
があり、このことは微細化の方向と逆行している。また
、この容量形成を含むプロセスでは、第１多結晶Ｓｉに
加え（第１多結晶Ｓｉプロセスは通常のトランジスタ形
成プロセスに使用される）第２多結晶Ｓｉもフォトエツ
チングによりパターニングしなければならず、従来の多
結晶Ｓｉ −多結晶Ｓｉキャパシタ構造は複雑なプロセ
スを必要としている。Therefore, in order to obtain a large capacity, it is necessary to increase the area of the polycrystalline Si electrode rather than reducing the thickness of the dielectric layer, which is contrary to the direction of miniaturization. Furthermore, in a process that includes this capacitor formation, in addition to the first polycrystalline Si (the first polycrystalline Si process is used in a normal transistor formation process), the second polycrystalline Si must also be patterned by photoetching. , conventional polycrystalline Si-polycrystalline Si capacitor structures require complicated processes.
本発明に於いては、キャパシタの第１の電極を並列する
複数の線状パターンとし、これらの線状パターンを電気
的に誘電体層とキャパシタの第２の電極を設けて、少な
くとも第１電極の側壁部に容量蓄積部を形成することに
よって、上記問題点を解決した。In the present invention, the first electrode of the capacitor is formed into a plurality of parallel linear patterns, and these linear patterns are electrically connected to the dielectric layer and the second electrode of the capacitor so that at least the first electrode The above-mentioned problem was solved by forming a capacitance storage section on the side wall of the device.
従来の平面的な多結晶Ｓｉ−多結晶Ｓｉキャパシタに於
いては、容量を大きくする要求には面積を大きくするこ
とにより対処されていたが、本発明に於いては、第１電
極を複数の線状パターンに分割して、第１電極の側面の
縦の容量を利用して、キャパシタの占有面積の増大を防
いでいる。In conventional planar polycrystalline Si-polycrystalline Si capacitors, the demand for increasing capacitance was met by increasing the area, but in the present invention, the first electrode is By dividing the capacitor into linear patterns and utilizing the vertical capacitance of the side surfaces of the first electrode, an increase in the area occupied by the capacitor is prevented.
実施例”■
第１多結晶Ｓｉ層２を第１図の様になるべく周辺長が長
くなる様にパターニングする。次に酸化を行い、第１多
結晶Ｓｉ−第２多結晶Ｓｉ間の容量形成用の酸化膜３を
形成する。その後全面に第２多結晶Ｓｉを成長させる。Example "■ The first polycrystalline Si layer 2 is patterned so that the peripheral length is as long as possible as shown in FIG. 1. Next, oxidation is performed to form a capacitance between the first polycrystalline Si and the second polycrystalline Si. A second oxide film 3 is then formed.A second polycrystalline Si is then grown on the entire surface.
第２多結晶ＳｉＮ４の全面エッチをＲＩＥ法により行い
、第１多結晶Ｓｉ層２のサイドに第２多結晶Ｓｉ層４を
残す。第１図Ｂに示すように、丁度第１多結晶Ｓｉ層２
を取り囲む様に第２多結晶Ｓｉ層４が残る事になる。The entire surface of the second polycrystalline SiN 4 is etched by RIE, leaving the second polycrystalline Si layer 4 on the side of the first polycrystalline Si layer 2. As shown in FIG. 1B, just the first polycrystalline Si layer 2
The second polycrystalline Si layer 4 will remain so as to surround it.
従来のキャパシタと本発明のキャパシタの間で容量の比
較をしてみる。単純化のため、両方ともキャパシタの大
きさ、形状は一辺の長さａの正方形とする。５ｉｎ２層
の厚さをり、誘電率をεとすると、従来のキャパシタの
場合、容量は
一方、本発明のキャパシタの場合、第１多結晶Ｓｉ層２
の線巾と線間隔を各々ｂとすると容量はおよそ、
εａｄ ａ ｔａ２ ｂＤ
ｂ Ｄ ｄとな
る。ｄ／ｂ＞ｌであれば、つまり第１多結晶５ｉＪｉ２
の厚みｄが線巾すより大であれば、従来のキャパシタに
比較して本発明のキャパシタの方が容量が大きくなる。Let's compare the capacitance between a conventional capacitor and a capacitor according to the present invention. For simplification, the size and shape of both capacitors are assumed to be a square with a side length a. If the thickness of the 2 layers is 5in, and the dielectric constant is ε, then in the case of a conventional capacitor, the capacitance is, on the other hand, in the case of the capacitor of the present invention,
If the line width and line spacing are respectively b, the capacity is approximately εad a ta2 bD
b D d. If d/b>l, that is, the first polycrystal 5iJi2
If the thickness d is greater than the line width, the capacitance of the capacitor of the present invention will be larger than that of the conventional capacitor.
実施例■
第１多結晶Ｓｉ層２を第２図の様になるべく周辺長が長
くなる様にパターニングする。次に熱酸化を行い、第１
多結晶Ｓｔ層−第２多結晶Ｓｉ層間の容量形成用の酸化
膜３を形成する。その後全面に第２多結晶Ｓｉ層４を成
長させる。第２多結晶５ｉＪ５４のパターニングをＲＩ
Ｅにより行い、容量を形成する。Example 2 The first polycrystalline Si layer 2 is patterned so that the peripheral length is as long as possible as shown in FIG. Next, thermal oxidation is performed, and the first
An oxide film 3 for forming a capacitance between the polycrystalline St layer and the second polycrystalline Si layer is formed. Thereafter, a second polycrystalline Si layer 4 is grown over the entire surface. RI patterning of second polycrystalline 5iJ54
E to form a capacitor.
この実施例についてのキャパシタの容量は、Ｄ
ｂ２
となる。ｄ／ｂ ＋ １／２ ＞ １、つまりｄ＞ｂ／
２であれば（ｂ ＜ ２ｄ）、すなわち、第１多結晶Ｓ
ｉ層２の線巾すがその厚みのｄの２倍より小であれば、
本発明のキャパシタの方が従来のキャパシタより容量が
大となる。The capacitance of the capacitor for this example is D
It becomes b2. d/b + 1/2 > 1, that is, d>b/
2 (b < 2d), that is, the first polycrystal S
If the line width of i-layer 2 is smaller than twice its thickness d, then
The capacitor of the present invention has a larger capacitance than the conventional capacitor.
半導体集積回路技術の進展に伴い、パターンが微細化し
つつある状況に於いては、本発明の第１電極層の線巾す
を細くすることも容易になり６つあるから、小面積で大
きな容量が得られる本発明の構造のキャパシタはますま
す重要となって来る。With the progress of semiconductor integrated circuit technology, patterns are becoming finer, and the line width of the first electrode layer of the present invention can be made thinner, and since there are six layers, large capacitance can be achieved in a small area. A capacitor having the structure of the present invention that provides the following is becoming increasingly important.
また本発明のキャパシタの形成方法は、ポリサイド ウ
オール スペーサを用いたＬＤＤ ）ランジスタの形成
プロセスと整合性があるので、マスクパターンを修正す
るのみで、Ｌ［ｌＤ ｌ−ランジスタ形成のプロセスに
本発明のキャパシタの製造プロセスを組み込むことがで
きる。Furthermore, since the capacitor formation method of the present invention is compatible with the formation process of LDD transistors using polycide wall spacers, the present invention can be applied to the process of forming L[lD l- transistors by simply modifying the mask pattern. Capacitor manufacturing processes can be incorporated.
また、本発明の構造のキャパシタの製造工程に於いては
、第２多結晶Ｓｉ層をフォトエツチングによりバターニ
ングする必要がないと言う効果もある。Further, in the manufacturing process of the capacitor having the structure of the present invention, there is also the advantage that there is no need to pattern the second polycrystalline Si layer by photoetching.
第１図は本発明の容量を示す。 第２図は他の本発明の容量を示す。 第３図は従来の多結晶−多結晶容量を示す。 FIG. 1 shows the capacity of the present invention. FIG. 2 shows another capacity of the present invention. FIG. 3 shows a conventional polycrystalline-polycrystalline capacitor.
Claims (1)
されたキャパシタにおいて、前記第１の導電層が互いに
間隔をあけて並列する複数の線状パターンよりなり、且
つ前記複数の線状パターンは互いに接続され、少なくと
も前記第１の導電層側壁部に容量蓄積部が形成されたこ
とを特徴とするキャパシタ。In a capacitor in which a second conductive layer is formed on a first conductive layer via a dielectric layer, the first conductive layer is composed of a plurality of linear patterns arranged in parallel at intervals, and the plurality of A capacitor, wherein the linear patterns are connected to each other, and a capacitance storage portion is formed at least on a sidewall portion of the first conductive layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13767486A JPS62293751A (en) | 1986-06-13 | 1986-06-13 | Capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13767486A JPS62293751A (en) | 1986-06-13 | 1986-06-13 | Capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62293751A true JPS62293751A (en) | 1987-12-21 |
Family
ID=15204167
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13767486A Pending JPS62293751A (en) | 1986-06-13 | 1986-06-13 | Capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62293751A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8178404B2 (en) | 2001-10-09 | 2012-05-15 | Nxp B.V. | Metal-insulator-metal (MIM) capacitor structure and methods of fabricating same |
-
1986
- 1986-06-13 JP JP13767486A patent/JPS62293751A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8178404B2 (en) | 2001-10-09 | 2012-05-15 | Nxp B.V. | Metal-insulator-metal (MIM) capacitor structure and methods of fabricating same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR950034789A (en) | Semiconductor integrated circuit device and manufacturing method thereof | |
| GB2392311A (en) | DRAM storage capacitor electrodes | |
| KR920022527A (en) | Manufacturing method of semiconductor integrated circuit device | |
| JP2008205180A (en) | Semiconductor device and its manufacturing method | |
| KR890008984A (en) | Semiconductor integrated circuit device and manufacturing method thereof | |
| JPS6118167A (en) | Semiconductor device | |
| JP2001257320A (en) | Semiconductor memory device and method of manufacturing the same | |
| KR930005741B1 (en) | Dram cell having a tunnelled capacitor and method of fabricating therefor | |
| JPS62293751A (en) | Capacitor | |
| KR100644526B1 (en) | Method of fabricating embossing-typed capacitor | |
| JPH08330518A (en) | Semiconductor integrated circuit and its manufacturing method | |
| KR940003606B1 (en) | Semiconductor device | |
| JPS59181045A (en) | Semiconductor device | |
| JPS63197368A (en) | Semiconductor device and its manufacture | |
| KR0155790B1 (en) | Capacitor fabrication method of semiconductor device | |
| JPH05347392A (en) | Manufacture of semiconductor device | |
| CN1255748A (en) | Method for making storage electrode of DRAM capacitor | |
| KR940001286B1 (en) | High-load resistor of semiconductor device | |
| KR0165304B1 (en) | Self align contact structure semiconductor device & its fabrication method | |
| KR970000976B1 (en) | Producing method of stack capacitor | |
| JPS61152064A (en) | Semiconductor memory device | |
| KR0176267B1 (en) | Manufacture of semiconductor storage device | |
| JPH05110027A (en) | Semiconductor device | |
| KR0140781B1 (en) | Structure of capacitor and its manufacturing method | |
| KR100233560B1 (en) | Dram device and its fabricating method |