JPS6229156A - High-density lsi substrate - Google Patents

High-density lsi substrate

Info

Publication number
JPS6229156A
JPS6229156A JP16821185A JP16821185A JPS6229156A JP S6229156 A JPS6229156 A JP S6229156A JP 16821185 A JP16821185 A JP 16821185A JP 16821185 A JP16821185 A JP 16821185A JP S6229156 A JPS6229156 A JP S6229156A
Authority
JP
Japan
Prior art keywords
wiring
duplicate
lsi
density
mounting pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16821185A
Other languages
Japanese (ja)
Inventor
Tsuneaki Tajima
田島　恒明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP16821185A priority Critical patent/JPS6229156A/en
Publication of JPS6229156A publication Critical patent/JPS6229156A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0286—Programmable, customizable or modifiable circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To improve the yield rate for high-density LSI substrates by a method wherein wirings are connected in duplicate to the mounting pads whereto LSI terminals are to be connected and cutting sections are provided for the disconnection of one of the two members of the wiring laid in duplicate. CONSTITUTION:A plurality of mounting pads 3 whereto the terminals of LSIs 1 are to be connected, a plurality of duplicate wirings 4 which are clock wirings to be connected to one of the mounting pads 3, and cutting sections 5 for the disconnection of one of the constituent members of the duplicate wiring 4, are provided. For example, wiring will be accomplished in duplicate between the mounting pad 3 of an LSI 1 and the mounting pad 3 belonging to another LSI 1, which means that a high-density LSI substrate 2 will be judged acceptable even if one of the constituent members of the duplicate wiring is down in the presence of the other functioning normally. Further, a cutting section 5 is provided in the vicinity of a mounting pad 3 for the disconnection of one of the two constituent members of a wiring laid in duplicate at a point between the mounting pad 3 and the cutting section 5 with the other constituent member being allowed to remain free of disconnection.

Description

【発明の詳細な説明】 し産業上の利用分野〕 本発明は、電子装置に使用される高密度ＬＳＩ（大規模
４Ａ積回路）基板に関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a high-density LSI (large scale 4A integrated circuit) board used in electronic devices.

〔従来の技術］ 第２図（ａ）〜（ｃ）はそれぞれ従来の高密度ＬＳ１基
板の平面図、０部を拡大した平面図、およびＤＤ断面図
である。ＬＳＩＩは高密度ＬＳＩ基板２の表面層にある
取付パッド３に取付けられ、この取付パッド３から他の
ＬＳＩＩの取付パッド３まで、内層又は表面層を通して
印刷方法又はメッキ・エツチング方法により配線されて
おり、ＬＳｒｌどうしを電気的に接続している。これら
の配線にはクロック配線４のばかその池の信号の配線。[Prior Art] FIGS. 2(a) to 2(c) are a plan view, an enlarged plan view of part 0, and a DD sectional view of a conventional high-density LS1 substrate, respectively. The LSII is mounted on a mounting pad 3 on the surface layer of the high-density LSI board 2, and wiring is conducted from this mounting pad 3 to the mounting pads 3 of other LSIIs through the inner layer or surface layer by a printing method or a plating/etching method. , LSrl are electrically connected to each other. These wires are the signal wires for clock wire 4, Bakasonoike.

電源配線当の配線６があり、第２図（ｃ）にクロック配
線４を示す。There is a wiring 6 for power supply wiring, and the clock wiring 4 is shown in FIG. 2(c).

従来、製造過程でおきる配線４．６の断面・短絡に対し
ては配線の両端を切断し、基板の表面で細いケーブルに
よって接続している。Conventionally, in response to cross-sections and short circuits in the wiring 4.6 that occur during the manufacturing process, both ends of the wiring are cut off and connected using thin cables on the surface of the board.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の高密度ＬＳＩ基板では、クロ・ツク配線
が断線又は短絡したときに、一般に布線という細いケー
ブルによる修理をしているが、電子装置が高性能になり
クロック信号が高速になると高密度ＬＳｒ基板内の配線
を伝わる電気のスピードと、布線によるケーブル内を伝
わる電気のスピードが異なることに起因する電気的問題
で、クロツク配線については布線による修理は不可能と
なり、高密度ＬＳＩ基板内に多数あるクロック配線のう
ち１木でも断線又は短絡があると高密度ＬＳＩ基板全体
が不良品になってしまうという欠点がある。またこれは
電子装置の高性能化に伴い、高密度ＬＳＩ基板の配線は
線幅が細くなり、さらに配線の密度が急激に高くなって
いるので、配線の断線・短絡が増々起き易くなっており
、上記問題は近年深刻な問題になってきている。In the conventional high-density LSI boards mentioned above, when the clock wiring becomes disconnected or shorted, it is generally repaired using thin cables called wiring, but as electronic devices become more sophisticated and clock signals become faster, This is an electrical problem caused by the difference in the speed of electricity transmitted through the wiring inside the high-density LSI board and the speed of the electricity transmitted through the wired cable, making it impossible to repair the clock wiring by wiring. There is a drawback that if even one of the many clock wiring lines in the board is disconnected or shorted, the entire high-density LSI board becomes a defective product. Additionally, as the performance of electronic devices increases, the line width of the wiring on high-density LSI boards has become narrower, and the density of the wiring has rapidly increased, making it more likely that wires will be disconnected or short-circuited. The above problem has become a serious problem in recent years.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の高密度ＬＳＩ基板は、搭載するＬＳＩの端子が
接続される複数の取付パッドと、この取付パッドのいず
れかに重複して接続された複数本の重複配線と、この重
複配線のうち選択した１本を残して他を切断するための
切断部とを含んで構成される。The high-density LSI board of the present invention has a plurality of mounting pads to which the terminals of the LSI to be mounted are connected, a plurality of overlapping wirings that are redundantly connected to any of the mounting pads, and a selection among the overlapping wirings. and a cutting section for cutting the remaining one and cutting the others.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図（ａ）〜（ｃ）はそれぞれ本発明の一実施例の平
面図、Ａ部を拡大した拡大平面図、およびＢＢ断面図で
ある。ＬＳｌｌは高密度ＬＳＩ基板２の表面層にある取
付パッド３に取り付けられ、この取付パッド３から池の
ＬＳＩＩの取付パッド３まで、内層又は表面層を通して
印刷方法又はメッキ・エツチング方法により配線４．６
が設けられており、ＬＳ［Ｌどうしを電気的に接続して
いる。FIGS. 1(a) to 1(c) are a plan view, an enlarged plan view of part A, and a cross-sectional view taken along line BB, respectively, of an embodiment of the present invention. The LSII is attached to a mounting pad 3 on the surface layer of the high-density LSI board 2, and wiring 4.6 is connected from this mounting pad 3 to the mounting pad 3 of the Ike's LSII through the inner layer or surface layer by a printing method or a plating/etching method.
is provided, and the LS [Ls are electrically connected to each other.

クロック配線４は第１図（ｂ）に示すように取付パッド
３から他のＬＳＩＩの取付パッド３までを複数１ヒ（第
１図（ｂ）では２本化）することにより、複数化された
クロック配線４のうち少くとも１本が良好であれば、池
のクロック配線４が不良となってら高密度ＬＳＩ基板を
良品とすることが可能である。従って、製造過程で発生
ずる可能性のある配線の断線・短絡のうち、従来修理不
可能であった２０ツク配線の断線・短絡に起因する不良
を減少させ・ることかできる。As shown in FIG. 1(b), the clock wiring 4 is made into multiple clock wires by connecting multiple wires from the mounting pad 3 to the mounting pad 3 of another LSII (two wires in FIG. 1(b)). If at least one of the clock wiring lines 4 is good, it is possible to make the high-density LSI board a good product even if the main clock wiring line 4 is defective. Therefore, among the disconnections and short-circuits in wiring that may occur during the manufacturing process, it is possible to reduce defects caused by disconnections and short-circuits in the 20-piece wiring, which could not be repaired in the past.

各クロック配線４の途中で取付パッド３の近くに切断パ
ッド部５を設けである。クロック配線４は電気的要求上
配線の長さ及び静電容量等が厳しく制限されるので、高
密度ＬＳＩ基板２の製造完了時点で、複数本あるクロッ
ク配線・１のうち良好な１本を選択し、池の余分なタロ
ツク配線４は取付パッド３と切断パッド部５の間で切断
することにより、常にＬＳＩ１間のクロック配線４の静
〔云容量等を同−Ｑ　作にすることができる。A cutting pad part 5 is provided near the mounting pad 3 in the middle of each clock wiring 4. Since the length and capacitance of the clock wiring 4 are strictly limited due to electrical requirements, at the time of completion of manufacturing the high-density LSI board 2, a good one of the multiple clock wirings 1 is selected. However, by cutting off the extra clock wiring 4 between the mounting pad 3 and the cutting pad section 5, the static capacitance of the clock wiring 4 between the LSIs 1 can always be kept at the same -Q level.

し発明の効果〕 以上説明したように本発明は、ＬＳＩの端子が接続され
る取付パッドに重複配線を接続しておくことにより、重
複配線のうち一本を残し他を切断して使用することで高
密度ｔＳＺ基板の製造歩留りを向上することができる。[Effects of the Invention] As explained above, the present invention enables overlapping wiring to be connected to the mounting pad to which the terminal of the LSI is connected, so that one of the overlapping wirings is left and the others are cut. Accordingly, the manufacturing yield of high-density tSZ substrates can be improved.

特に取付バ・ソドに接続される各種配線のうちクロック
配線だけを重複して配線することにより高密度ＬＳＩ基
板全体の配線密度への影響を最小限に押えながら高密度
１−８Ｉ基板の製造歩留りを向上することができる。In particular, by overlapping only the clock wiring among the various wiring connected to the mounting board, the manufacturing yield of high-density 1-8I boards can be minimized while minimizing the effect on the wiring density of the entire high-density LSI board. can be improved.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ）〜（ｃ＞はそれぞれ本発明の一実施例の平
面図、Ａ部の拡大平面図およびＢＢ断面図、第２図（ａ
）〜（ｃ）はそれぞれ従来の高密度ＬＳＩ基板の平面図
、０部の拡大平面図およびＤＤ断面図である。 １・・・ＬＳＩ、２・・・高密度＋−ｓｒ基板、３・・
・取付パッド、４・・・クロック配線、５・・・切断パ
ッド部。 （Ｌ＞ （Ｃ） （α） ＣＣ）FIGS. 1(a) to (c> are a plan view, an enlarged plan view and a BB sectional view of part A, and FIG. 2(a) of an embodiment of the present invention, respectively.
) to (c) are a plan view, an enlarged plan view of part 0, and a DD sectional view of a conventional high-density LSI board, respectively. 1...LSI, 2...High density +-SR board, 3...
・Mounting pad, 4... Clock wiring, 5... Cutting pad part. (L> (C) (α) CC)

Claims (1)

【特許請求の範囲】[Claims] 搭載する大規模集積回路の端子が接続される複数の取付
パッドと、この取付パッドのいずれかに重複して接続さ
れた複数本の重複配線と、この重複配線のうち選択した
１本を残して他を切断するための切断部とを含むことを
特徴とする高密度ＬＳＩ基板。Multiple mounting pads to which the terminals of the large-scale integrated circuit to be mounted are connected, multiple overlapping wirings connected to any of these mounting pads, and all but one selected among these overlapping wirings. A high-density LSI board, comprising: a cutting section for cutting other parts.
JP16821185A 1985-07-29 1985-07-29 High-density lsi substrate Pending JPS6229156A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16821185A JPS6229156A (en) 1985-07-29 1985-07-29 High-density lsi substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16821185A JPS6229156A (en) 1985-07-29 1985-07-29 High-density lsi substrate

Publications (1)

Publication Number Publication Date
JPS6229156A true JPS6229156A (en) 1987-02-07

Family

ID=15863844

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16821185A Pending JPS6229156A (en) 1985-07-29 1985-07-29 High-density lsi substrate

Country Status (1)

Country Link
JP (1) JPS6229156A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5887482A (en) * 1995-01-13 1999-03-30 Yoshiki Industrial Co., Ltd. Apparatus for mutual conversion between circular motion and reciprocal motion

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5887482A (en) * 1995-01-13 1999-03-30 Yoshiki Industrial Co., Ltd. Apparatus for mutual conversion between circular motion and reciprocal motion

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