JPS62291183A - Manufacture of multijunction semiconductor photoelectric conversion element - Google Patents
Manufacture of multijunction semiconductor photoelectric conversion elementInfo
- Publication number
- JPS62291183A JPS62291183A JP61135521A JP13552186A JPS62291183A JP S62291183 A JPS62291183 A JP S62291183A JP 61135521 A JP61135521 A JP 61135521A JP 13552186 A JP13552186 A JP 13552186A JP S62291183 A JPS62291183 A JP S62291183A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- cell
- junction
- gaas
- upper cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000006243 chemical reaction Methods 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000000034 method Methods 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 230000015572 biosynthetic process Effects 0.000 claims abstract 5
- 210000004027 cell Anatomy 0.000 claims description 99
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 33
- 210000004692 intercellular junction Anatomy 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 8
- 238000010030 laminating Methods 0.000 claims 1
- 239000000463 material Substances 0.000 description 12
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 230000006866 deterioration Effects 0.000 description 5
- 238000001451 molecular beam epitaxy Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 230000002411 adverse Effects 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 2
- 229910015363 Au—Sn Inorganic materials 0.000 description 2
- 229910001297 Zn alloy Inorganic materials 0.000 description 2
- 235000011114 ammonium hydroxide Nutrition 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Photovoltaic Devices (AREA)
Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
〔産業上の利用分野〕
本発明は多接合半導体光電変換素子の製造方法に関する
ものである。Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method of manufacturing a multi-junction semiconductor photoelectric conversion element.
単一のＰＮ接合を用いた半導体太陽電池は、透過損ｐ光
エネルギ不完全利用損等の損失により、光洩で、その効
率は、！３〜．２４ｔ％（理論計算上の仮定等により、
ばらつきがある）である。これを上回る高効率を得るた
めの構造の太陽電池として多接合半導体構造の太陽電池
が提案されている。代表的多接合半導体太陽電池の例を
第グ図に示す。A semiconductor solar cell using a single PN junction suffers from light leakage due to losses such as transmission loss and incomplete utilization of light energy, and its efficiency is... 3~. 24t% (due to assumptions in theoretical calculations, etc.)
There are variations). A solar cell with a multi-junction semiconductor structure has been proposed as a solar cell structured to obtain higher efficiency than this. An example of a typical multijunction semiconductor solar cell is shown in Fig.
これは短波長側の受光を禁制帯幅（Ｅり）の大きな半導
体材料より成る上部接合を有する上部セル２とＥｆの小
さな半導体材料より成る下部接合を有する下部セル弘を
上下接合部３で接続し、上部セル２上に表面電極／、下
部セルグ上に裏面電極夕を設けた構造である。この多接
合半導体太陽電池は、短波長側の受光を上部セル２で行
い、長波長側の受光を下部セル弘で行い、有効波長の広
帯域化を図っている。上下セルを電気的につなぐ方法と
してはトンネル接合、金属電極、格子不整によるリーク
電流を利用した接合等を用いた接続が提案されている。In this case, an upper cell 2 having an upper junction made of a semiconductor material with a large forbidden band width (E) and a lower cell 2 having a lower junction made of a semiconductor material with a small Ef are connected at an upper and lower junction part 3 for receiving light on the short wavelength side. However, it has a structure in which a front electrode is provided on the upper cell 2 and a back electrode is provided on the lower cell. This multi-junction semiconductor solar cell receives light on the short wavelength side in the upper cell 2, and receives light on the long wavelength side in the lower cell 2, thereby achieving a wide range of effective wavelengths. As methods for electrically connecting upper and lower cells, connections using tunnel junctions, metal electrodes, junctions that utilize leakage current due to lattice misalignment, etc. have been proposed.
現在、このような多接合半導体構造の太陽電池を分子線
エピタキシー（ＭＢＥ）法や有機金属気相成長（ＯＭＶ
ＰＥ）法によって作製する試みが多く行われている。材
料系は、上部セル２にＪ臥ｓやｃｍｓｐ＋下部セルグに
ＧａＡｓ、 ＩｎＧａＡｓ等の■−ｖ族化合物半導体を
使うものがほとんどである。このような多接合半導体太
陽電池は、先ず下部セル弘を成長させた後に上部セル２
を成長させる方法で作られていた。しかし、上部セル２
と下部セル弘の成長条件が異なる場合、従来の成長の順
番である下部セル弘を作製した後上部セル２を作製する
という順序で多接合構造の太陽電池を作ると、下部セル
≠が上部セル２の成長条件によって悪影響をうけるとい
う欠点がある。この悪影響とは、例えば、格子不整合、
熱かぶり、高濃度のキャリア濃度で接合をつくる時のド
ーピング等の問題点が原因になって起こるものである。Currently, solar cells with such multijunction semiconductor structures are manufactured using molecular beam epitaxy (MBE) method and metal organic vapor phase epitaxy (OMV) method.
Many attempts have been made to produce the material using the PE method. Regarding the material system, most of the materials use a ■-v group compound semiconductor such as JS for the upper cell 2 and GaAs or InGaAs for the cmsp+ lower cell. In such a multi-junction semiconductor solar cell, first the lower cell layer is grown, and then the upper cell layer 2 is grown.
It was made in a way that allowed it to grow. However, upper cell 2
When the growth conditions of the lower cell 2 and the lower cell 2 are different, if a solar cell with a multijunction structure is made in the conventional growth order of producing the lower cell 2 and then producing the upper cell 2, the lower cell ≠ is the upper cell. It has the disadvantage that it is adversely affected by the growth conditions of 2. These negative effects include, for example, lattice mismatch,
This is caused by problems such as thermal fogging and doping when forming a junction with a high carrier concentration.
以下１．ｐＪＧａＡｓ −ＧａＡｓ系とＡＡ）ａＡｓ
−ＩｎＧａＡｓ系を例にとって具体的に従来の欠点を指
摘する。Below 1. pJGaAs-GaAs system and AA) aAs
- Taking the InGaAs system as an example, the drawbacks of the conventional system will be specifically pointed out.
■ ＡｌＧａＡｓ −ＧａＡｓ系は、格子定数、熱膨張
係数の上下セルでのマツチングもよく高効率が得られる
材料系として期待されている。上部セル２と下部セル弘
とを電気的につなぐ方法としても、非有効面積がなく成
長後や成長途中のプロセスが不必要なトンネル接合を採
用でき、ピーク電流密度が数アンペアから数百アンペア
／−と高電流密度の多接合半導体構造の太陽電池が得ら
れている。(2) The AlGaAs-GaAs system is expected to be a material system that can provide high efficiency with good matching of lattice constant and coefficient of thermal expansion between upper and lower cells. As a method for electrically connecting the upper cell 2 and the lower cell 2, a tunnel junction can be used that does not have an ineffective area and does not require processes after growth or during growth, and the peak current density can range from several amperes to several hundred amperes/ A solar cell with a multi-junction semiconductor structure of - and high current density has been obtained.
ところが変換効率の向上には限界があった。即ち、ＡＭ
Ｏ〜２の太陽光に対して多接合構造の太陽電池でトンネ
ル接合を用いた純粋な二端子素子では変換効率１０優に
満たないのが現状であった。However, there was a limit to the improvement in conversion efficiency. That is, A.M.
At present, a pure two-terminal element using a tunnel junction in a solar cell with a multi-junction structure has a conversion efficiency of less than 10 for sunlight of 0~2.
この変換効率は各セルの単一構造の太陽電池から予想さ
れる値よりはるかに低い値である。This conversion efficiency is much lower than what would be expected from a solar cell with a single structure of each cell.
各セル部分単独では良好な変換効率が得られながら多接
合構造全体の変換効率が向上しないことの最も大きな原
因は各部の最適成長条件が大幅に違い、多接合構造を作
製する際に先に形成した部分が後の工程で悪影響をうけ
てしまうことである。The biggest reason why the conversion efficiency of the entire multi-junction structure does not improve even though good conversion efficiency can be obtained with each cell part alone is that the optimal growth conditions for each part are significantly different, and when the multi-junction structure is fabricated, it is necessary to This means that the parts that have been removed will be adversely affected in subsequent processes.
ＭＢＥ法についていえば、下部セル≠のＧａＡｓ接合部
は基板温度ＴＳ ＝ ６１０−ｔ ００’Ｃ、Ｖ、Ａ１
１俵−分ｌ’ｆ−ｅ度比ト、＝ 、１： ；、 １で形
成Ｍたｌ鳴府の膜噴汐勉α好卿こトンネル接合を用いた
接続部３はＴＳ−ＪＯＯ〜６２０°Ｃ２γ＝ｇ〜ＩＯで
形成し、上部セル２のＭ以Ｓ接合部はＴｓ＝７０θ〜７
２０″Ｃ２γ＝２〜グで形成することが好ましい。第５
図に上部セル２であるＭ虱Ｓの成長温度と膜質を表わす
パラメータである少数キャリア拡散長との関係を示した
。短絡電流密度や少数キャリア拡散長の最大値が７００
′Ｃ付近であることからも上部セル２の積層には高温成
長（ＴＳ＝７００〜７２０’Ｃ）が良い膜をつくる絶対
条件であることがわかる。ところが、トンネル接合を用
いた接続部は上部セルの高温成長により大幅に劣化して
しまう。この劣化の様子を第４図に示す。実線２は、ｓ
ｏｏｏｃで成長したＧａＡｓ基板上−Ｐ＋＋のトンネル
ダイオードの特性であり、点線７はＧａＡｓ ｎ ＋＋
−Ｐ″−の上に７００”ＣでＡ／！ＧａＡＳ膜／ｐｍを
成長したＧａＡｓｎ −Ｐ のトンネルダイオード
の特性である。第を図から点線７は実線２よりトンネル
電流が少ないことからトンネル接合が上部セル２成長時
の温度によって劣化されていることがわかる。Regarding the MBE method, the GaAs junction of the lower cell≠ has a substrate temperature TS = 610-t 00'C, V, A1
The connection part 3 using the tunnel junction is TS-JOO ~ 620. °C2γ=g~IO, and the M to S junction of upper cell 2 is Ts=70θ~7
It is preferable to form with 20″C2γ=2~g.
The figure shows the relationship between the growth temperature of MEL S, which is the upper cell 2, and the minority carrier diffusion length, which is a parameter representing the film quality. The maximum value of short circuit current density and minority carrier diffusion length is 700
It can be seen that high temperature growth (TS=700 to 720'C) is an absolute condition for forming a good film in the lamination of the upper cell 2, since the temperature is around 'C. However, connections using tunnel junctions deteriorate significantly due to high temperature growth of the upper cell. The state of this deterioration is shown in FIG. Solid line 2 is s
The dotted line 7 shows the characteristics of a -P++ tunnel diode on a GaAs substrate grown by oooc.
A/! at 700”C on -P”-! These are the characteristics of a GaAsn-P tunnel diode grown with a GaAS film/pm. From the figure, it can be seen that the tunnel junction is degraded by the temperature during the growth of the upper cell 2 because the tunnel current is smaller in the dotted line 7 than in the solid line 2.
また、温度以外にもトンネル接合部のｎ （ｈＡｓ層
を高濃度にする際、不純物イオンの打込処理表面は高濃
度にすることが容易であるが、ｎ ＋＋ＧａＡｓ層の不
純物イオンの打込処理裏面を高濃度にすることは難しい
ことが知られている。In addition to temperature, when making the n(hAs layer of the tunnel junction a high concentration), it is easy to make the impurity ion implantation surface highly concentrated, but the impurity ion implantation treatment of the n++ GaAs layer It is known that it is difficult to achieve high concentration on the back side.
■ ＡＩＱｊａＡｆｓ Ｉｎ（）ａＡｓ系では太陽光
に対して最も高効率を得られるＥｆの組み合せとして、
上部セル２のＥｇＩが／、 ＆〜／、 ７ ｅＶ、下部
セルＩＩＯ場が／、／〜／、 、２ ｅＶが理論的に算
出されるがこの下部セル弘の好適なＥｐを実現する最も
簡単なｍ−ｖ族の組み合せは、ＩｎＧａＡｓ （Ｉｎ組
成０．／〜０．２）である。この下部セル材料の欠点は
・格子整合のとれる二元■−■族基板が存在しないこと
であるが、格子定数がＩｎＧａＡｓより小さい一基板を
用い、バッファ層を用いること等により、結晶品質のよ
いＩｎＧａＡｓをＧａＡｓ基板上に形成できる。■ AIQjaAfs In()aAs system, the Ef combination that provides the highest efficiency for sunlight is
It is theoretically calculated that the EgI of the upper cell 2 is /, &~/, 7 eV, and the IIO field of the lower cell is /, /~/, , 2 eV, but this is the easiest way to realize a suitable Ep for the lower cell. A typical m-v group combination is InGaAs (In composition 0./~0.2). The disadvantage of this lower cell material is that there is no binary ■-■ group substrate that can achieve lattice matching, but by using a substrate with a lattice constant smaller than that of InGaAs and using a buffer layer, it is possible to achieve good crystal quality. InGaAs can be formed on a GaAs substrate.
ところが、このようにして得られたＩｎＧａＡｓを下部
セルに用いた多接合構造の太陽電池では、最も良好なも
のでも効率が２０−．２３％と単一な接合構造のものの
効率と余り変りがない。ｌ’ＪｃＩＩＡ５ ＨＧａＡＳ
Ｐ等を上部セル材料として用いた場合では格子不整の問
題が生じ、上部セル ′ −９≠の材料の方が下
部セル弘の材料に比べ格子定数が小・さいため格子不整
の克服が難しい。また、これらの上部セル材料の成長時
には、一般に高温が必要なため下部セル弘のＩｎＧａＡ
ｓからＩｎが上部セルλへ侵入して上部セル２を劣化さ
せる。このように品質のよい上部セルが形成できないの
で、太陽電池の効率を向上できない。However, in the multi-junction solar cell using InGaAs for the lower cell obtained in this way, even the best one has an efficiency of 20-. The efficiency is 23%, which is not much different from the efficiency of a single junction structure. l'JcIIA5 HGaAS
When P or the like is used as the upper cell material, the problem of lattice misalignment occurs, and it is difficult to overcome the lattice misalignment because the material of the upper cell'-9≠ has a smaller lattice constant than the material of the lower cell. In addition, since high temperatures are generally required when growing these upper cell materials, InGaA for the lower cell layer is
In enters the upper cell λ from s and deteriorates the upper cell 2. Since a high-quality upper cell cannot be formed in this way, the efficiency of the solar cell cannot be improved.
本発明の目的は、高効率の多接合半導体光電変換素子の
製造方法を提供することにある。An object of the present invention is to provide a method for manufacturing a highly efficient multi-junction semiconductor photoelectric conversion element.
本発明は、ダミー基板を用意し、その上に先ず上部セル
を先に形成した後、上部セル上に上部セルと下部セルの
接続部を形成し、次いで接続部上に下部セルを形成した
後ダミー基板を除去することを主要な特徴とする。In the present invention, a dummy substrate is prepared, an upper cell is first formed on the dummy substrate, a connecting portion between the upper cell and the lower cell is formed on the upper cell, and then a lower cell is formed on the connecting portion. The main feature is that the dummy substrate is removed.
本発明の製造方法では、ダミー基板を用い、成長温度の
高い上部セルを先に成長させ、次いで成長温度の低い下
部セルを成長させるので各セルは成長後に成長時より高
い熱処理を経ない。また、下部セルに比べ格子定数の小
さい上部セルをもつ多接合半導体光電変換素子について
も、格子定数の小さい順にセルを成長させるので格子不
整合の克服が容易である。従って、高品質の上部セルを
形成でき、効率の高い多接合半導体光電変換素子を実現
できる。In the manufacturing method of the present invention, a dummy substrate is used, and the upper cell with a higher growth temperature is grown first, and then the lower cell with a lower growth temperature is grown, so that each cell does not undergo a higher heat treatment after growth than during growth. Further, even in a multi-junction semiconductor photoelectric conversion element having an upper cell having a smaller lattice constant than a lower cell, it is easy to overcome lattice mismatch because the cells are grown in order of decreasing lattice constant. Therefore, a high-quality upper cell can be formed, and a highly efficient multijunction semiconductor photoelectric conversion element can be realized.
ＡｌＧａＡｓ ＧａＡｓ系を用いた本発明の第１の実
施例を以下に述べる。A first embodiment of the present invention using an AlGaAs GaAs system will be described below.
第１図は、本発明の第１の実施例を説明する図である。FIG. 1 is a diagram illustrating a first embodiment of the present invention.
エピタキシャル成長法として！−、ｉ：ＭＢＥ法を用い
ている。まず、ダミー基板としてＧａＡｓ結晶ざを用意
する。次いで、このダミー基板ざの表面の欠陥等の上部
セルへの悪影響を除去するために帥バッファ層りを成長
基板温度Ｔ５−！♂Ｏ′Ｃで−ＩＯ−
ダミー基板ｒ上に成長する（第１図（Ａ））。次にＴ、
を７００”Ｃへ上げ、ストップエッチ層となる鳩（ｈｌ
−）４ Ａ、ｓ （：ＩＱ） ＝ （１）り）層１０を
バッファ層り上に成長する（第７図（Ｂ））。続いて素
子本体の成長に入るがＡｔＧａＡｓは表面オーミック電
極がとりにくいため、Ｔｓを再びｒｒｏ’ｃへ下げオー
ミック用のキャリア濃度が約１０ ｃｍ のＰＯａ
ＡＳ層／／をＭＯ，ｇ ＧａＯ，Ｉ Ａｓ層１０の上に
成長する（第１図（Ｃ））。As an epitaxial growth method! -, i: MBE method is used. First, a GaAs crystal substrate is prepared as a dummy substrate. Next, a buffer layer is grown on the dummy substrate at a temperature T5-! in order to remove any adverse effects on the upper cells such as defects on the surface of the dummy substrate. -IO- is grown on the dummy substrate r with ♂O'C (FIG. 1(A)). Next, T.
Raise the temperature to 700"C and apply a stop etch layer (hl).
-)4 A,s (:IQ) = (1) ri) A layer 10 is grown on the buffer layer (FIG. 7(B)). Next, the growth of the device body begins, but since it is difficult to form an ohmic electrode on the surface of AtGaAs, Ts is lowered to rro'c again, and POa with an ohmic carrier concentration of about 10 cm is used.
An AS layer // is grown on the MO, g GaO, I As layer 10 (FIG. 1(C)).
に、キャリア濃度が約！ Ｘ ／ ０１８ｃｍ−８の上
部セル接Ｘ合用のＰ Ａ／ｙ、、Ｏａｔ ｘ４Ａｓ （
Ｘ、−０，ｔ４ ）層／３、キャリア濃度が１０〜１０
ｃｍ の上部セル接合用のｎ Ａｔｘ２Ｇａｌ−
没ＡＳ層／グ、キャリア濃度が約ｊＸ１０ ｃｍの裏窓
層用のｎ Ａ２ｘ３Ｇａｉ−均Ａｓ （ｘｓ ＝ ０．
ｚ）層／オ、の順にＰ ＧａＡｓ層／／の上に成長
する（第７図（Ｄ））。, the carrier concentration is approximately! P A/y,, Oat x4As (
X, -0, t4) layer/3, carrier concentration is 10 to 10
n Atx2Gal- for the top cell junction of cm
n A2x3 Gai - average As (xs = 0.
z) layer/o is grown on the P GaAs layer// in this order (FIG. 7(D)).
これらの層／、２〜／ｊの部分がＭ以Ｓ上部セル／ｌで
ある。続いて、Ｉ５をｔｏｏ″ｃへ下げ、キャリア濃度
が約／ ０１９ｃｍ−８のトンネル上部層のｎ ” Ｏ
結、ｓ層／７、キャリア濃度が約／ ０１９ｃｍ−８の
トンネル下部層のＰ ＧａＡｓ層ｉｔ、をＡ７ＧａＡ
ｓ上部セル／ｌの上に成長する（第１図（Ｅ））。これ
らの層／７． ＸＩがトンネル接合を用いた接続部／
りである。次にＴｓをｊ♂Ｏ′Ｃへ上げ、キャリア濃度
が約夕×１０ｃｒｎの下部セル接合用のＰ ＧａＡｓ層
２０、キャリア濃度が１０１６〜１０１７の下部セル接
合用のｎＧａｕ層２／、キャリア濃度が約ｒ Ｘ ／
０１８ｏｎ−”の裏面電極コンタクト用ｎ 鳳ｓ層２
２の順で接続部／りの上に成長する（第１図（Ｆ））。The portions of these layers /, 2 to /j are the upper M or S upper cells /l. Subsequently, I5 is lowered to too''c, and the n''O of the tunnel upper layer with a carrier concentration of about /019 cm
In other words, the P GaAs layer of the tunnel lower layer with an s layer of /7 and a carrier concentration of about /019 cm-8 is made of A7GaA.
It grows on top of the s upper cell/l (Fig. 1(E)). These layers/7. Connection part where XI uses tunnel junction/
It is. Next, Ts is increased to j♂O'C, and a P GaAs layer 20 for the lower cell junction with a carrier concentration of about 10 crn, an nGau layer 2/ for the lower cell junction with a carrier concentration of 1016 to 1017, and a carrier concentration of Approximately r x /
018on-'' n-s layer 2 for back electrode contact
It grows on the connection part/li in the order of 2 (FIG. 1(F)).
これらの層２０．２／、２２の部分がＧａＡｓ下部セル
２３である。なお、不純物としてはｎ形がＳｉ＋Ｐ形が
Ｂｅを用いればよい。A portion of these layers 20.2/22 is the GaAs lower cell 23. Note that as impurities, Si for n-type and Be for p-type may be used.
続いて、ｎ （）ａＡｓ層２２面上（素子としては裏面
）に裏面電極となるＡｕ−Ｓｎ合金２≠を蒸着してＡｕ
２ｊ蒸着をしたＡｔ板、２ＪにとのＡｕ −Ｓｎ合金層
２≠をＡ７ペーストで貼り付ける（第１図（（２））。Subsequently, an Au-Sn alloy 2≠, which will become a back electrode, is deposited on the surface of the n()aAs layer 22 (the back surface as an element) to form an Au
The Au-Sn alloy layer 2≠ of 2J is attached to the At plate on which 2J has been deposited using A7 paste (FIG. 1 (2)).
Ａｔ板２ｔを研磨して３０μｍまで薄くした後、これを
Ｉ２０２ ： ＮＨ４ＯＨ（体積比３０ ： ／ ）溶
液に入れてダミー ＧａＡｓ基板♂及びＧａＡｓバッフ
ァ層りをエツチング除去する（第１図（［（） ）。こ
のエツチングはＧａＡｓにのみ有効なため素子本体はス
トップエッチ履用Ａｔｏ、ｇ ＧａＯ，ＩＡＳ層ＩＯに
よって保護される。次にＡｔＯ，ｇ ＧａＯ，ｌ Ａｓ
層ＩＯにのみエツチングが有効なＫＩ：Ｉ２；Ｉ２０（
重量比７：４ｔ：Ｉ７７）溶液でストップエッチ層Ａ１
６ｏＧａＯ，ＩＡｓ層ＩＯをエツチングで除去する（第
り
７図（Ｉ））。露出した（３ａＡＳ面／／にＡｕ −Ｚ
ｎ合金Ｕ−ｆＩ−を真空蒸着によりつける（第１図（Ｊ
））。フォトリングラフィ技術を用いて、櫛形のエツチ
ングマスクをつけて、保護されているところ以外のＡｕ
−Ｚｎり
合金２４−をＫＩ： Ｉ２ ’ ＨｉＯ溶液（重量比７
：グ：／７７）り
でエツチングしパターンｊ−！Ｉ−ａを形成する。さら
に）（２０２’ ＮＨ４ＯＨ（体積比３Ｃ）：／）溶液
を用い、ク
パターン２−ＩＦａをマスクにして、ＧａＡＳ層／／を
エツチングしパターン／／ａを形成する。これをア七ト
ンで洗いエツチングマスクをとれば櫛形のＡｕ−Ｚｎ合
金電極２−９−ができる（第１図（）０）。After polishing the At plate 2t to a thickness of 30 μm, it was placed in an I202:NH4OH (volume ratio 30:/) solution and the dummy GaAs substrate ♂ and the GaAs buffer layer were etched away (see Figure 1 ([()). ).Since this etching is effective only for GaAs, the element body is protected by the stop-etch layer Ato, g GaO, IAS layer IO. Next, AtO, g GaO, l As
KI where etching is effective only for layer IO: I2; I20(
Weight ratio 7:4t:I77) Stop etch layer A1 with solution
The 6oGaO, IAs layer IO is removed by etching (FIG. 7(I)). Au-Z on the exposed (3aAS surface //
n alloy U-fI- is applied by vacuum evaporation (Fig. 1 (J
)). Using photolithography technology, a comb-shaped etching mask is applied to remove the Au other than the protected areas.
-Zn alloy 24- is KI: I2' HiO solution (weight ratio 7
:G:/77) Etching pattern j-! Form I-a. Further, using a (202' NH4OH (volume ratio 3C):/) solution and using the pattern 2-IFa as a mask, the GaAS layer // is etched to form a pattern //a. If this is washed with acetone and the etching mask is removed, a comb-shaped Au--Zn alloy electrode 2-9- is obtained (FIG. 1()0).
以上の工程で特に問題となるのは、ＴＳ”３０ぴＣで成
長したトンネル接合の接続部／りが下部セル２３の各層
成長時にＪ′ｇＯ′Ｃとなることによって劣化しないか
という点であるが、第２図に示すようにｊ♂Ｏ′ＣでＧ
ａＡｓを３μｍ成長させたときの特性３０にみられるよ
うにＪ′ｇｏ”ｃの工程を通ったトンネル接合では大幅
な劣化はみられない。但し、オ♂Ｏ′Ｃの工程を経るに
してもＧａＡｓ ）ンネル接合の成長温度は必らずｓｏ
ｏ′ｃで行う必要がある。A particular problem in the above process is whether the connection part of the tunnel junction grown at TS"30 pC will deteriorate due to becoming J'gO'C during the growth of each layer of the lower cell 23. However, as shown in Figure 2, G at j♂O'C
As seen in characteristic 30 when aAs is grown to 3 μm, no significant deterioration is observed in tunnel junctions that have gone through the J'go'c process. However, even though they have gone through the O♂O'C process, The growth temperature of the GaAs) tunnel junction is necessarily so
It is necessary to do this at o'c.
このような工程で作製した素子では特性の劣化はほとん
どみられず、Ａ Ｍ ／ ＋ ／ ００ ｍ ｗ／ｃｒ
／ｌの太陽光に対し変換効率２！〜、２＆％とかなりの
素子特性の改善をみた。Devices fabricated using this process show almost no deterioration in characteristics, with A M / + / 00 mw/cr
Conversion efficiency is 2 for /l of sunlight! A considerable improvement in device characteristics was observed, ranging from 2% to 2%.
次にＡｔＧａＡｓ −ＩｎＧａＡｓ系を用いる本発明の
第２実施例を以下に述べる。Next, a second embodiment of the present invention using the AtGaAs-InGaAs system will be described below.
第３図は、本発明の第２の実施例を説明する図である。FIG. 3 is a diagram illustrating a second embodiment of the present invention.
ダミー ＧａＡｓ基板１０ｇを用い、ＧａＡｓバッファ
層１０り、ストップエッチのだめのＭ＠（３ａｌ ％Ａ
Ｓ（ＸＯ＝（７，７）層／１０及びオーミックコンタク
ト用のＰ ＧａＡＳ層／／／の形成を実施例／と同様
に行う。次にＴｓを７００′Ｃへ上げキャリア濃度約夕
×１０ ｃｍ の窓層用のｐ ＡｔＸ、 Ｇａｌ
ＸＩ Ａｓ （ｘｓ ＝＝ （Ｈ）層／／、２．キャリ
ア濃度約Ｊ−Ｘ ／ ０１８ｃｍ””の上部セル接合用
のＰ＋人へ、 （ｈｌ−ｙ、 Ａｓ （）Ｑ ＝０．−
２ ）層／／３．キャリア濃度〆・ｏ、、４６．、、／
θ１°７□−３“３の上部セル接合用の積載−１＋−ｍ
Ａｓ層／／弘、ギヤリア濃度約！ｒ×１０ ｔｙｎ
の裏窓層用のｎ ＋Ａｔｙ、、 Ｇａ１−ｙ、 Ａｓ
、（黛＝ 、’０．４’ ）層／／ｊ、をこの順にＰ
１℃ａＡ、ｓ層／／／の上に成長する（第４図（Ａ））
。これら各層／７２〜／／！の部分がＡｌＧａＡｓ上部
セル／／１である。続いてＴｓを！ｒＯＯ°Ｃへ下げ、
キャリア濃度約１０１９ノｎ ＋＋Ａ１．Ｘ６Ｇａ１−
ｘ６Ａｓ （Ｘｓ ＝ （７，，２）層／／７、キャリ
ア濃度約１０ ｃｍ のＰ Ｉｎｙ、Ｇ１１−ｙ、
ｋｓ（Ｙ１＝０．０り ／／Ｊ’、をＶ臥Ｓ上部セル
部／／１．の上に成長する（第３図（Ｂ））。Using 10 g of dummy GaAs substrate, 10 g of GaAs buffer layer, M@(3al%A
The S(XO=(7,7) layer/10 and the P GaAS layer/// for ohmic contact are formed in the same manner as in Example/. Next, Ts is increased to 700'C and the carrier concentration is approximately 2×10 cm. p AtX, Gal for the window layer of
XI As (xs == (H) layer//, 2. P+ person for the upper cell junction with carrier concentration approximately J-X/018 cm"", (hl-y, As ()Q = 0.-
2) Layer //3. Carrier concentration 〆・o,,46. ,,/
Loading for upper cell junction of θ1°7□-3"3 -1+-m
As layer//Hiroshi, Gearia concentration approx! r×10 tyn
n +Aty, Ga1-y, As for the back window layer of
, (Mayuzumi = , '0.4') layer //j, in this order P
1℃aA, grows on top of the s layer /// (Figure 4 (A))
. Each of these layers /72~//! The portion is the AlGaAs upper cell //1. Next is Ts! lower to rOO°C;
Carrier concentration approximately 1019n ++A1. X6Ga1-
x6As (Xs = (7,,2) layer //7, P Iny with carrier concentration of about 10 cm, G11-y,
ks(Y1=0.0ri//J') is grown on the upper cell part of V*S//1. (Fig. 3(B)).
これらの層／／７＋／／♂が格子不整のある接続部／ｌ
りである。最後にＴｓを！２０°Ｃとし、キャリア濃度
約３×１０１８．−”のバッファ層用のＰ＋Ｉｎｙ２Ｇ
ａｌ−ｙ２ＡＳ （Ｙｚ 嬌０．０３−０．／ ｊ ）
層／２０．下部上下接合用のキャリア濃度約！×１０１
ｍ のＰ Ｉｎｙ２（Ｊｋｒ） ｙ２Ａｓ層７２ノ
、キャリア濃度１０１６〜１０１″ｃｒｎ−８の下部セ
ル接合用のｎ Ｉｎｙ２Ｇａ １−ｙ２ Ａｓ層／２２
．キャリア濃度約ｊ×１０１８ｃｒｎ−８の裏面電極コ
ンタクト用のｎ Ｉｎｙ２Ｇａ１ 、Ａｓｓｉ２３・
を形成する（第３図（Ｃ））。These layers //7+//♂ are connections with lattice misalignment/l
It is. Finally, Ts! The temperature was 20°C, and the carrier concentration was approximately 3×1018. -” P+Iny2G for buffer layer
al-y2AS (Yz嬌0.03-0./j)
Layer/20. Carrier concentration for lower and upper junctions is approximately! ×101
m P Iny2 (Jkr) y2As layer 72, n Iny2Ga 1-y2 As layer/22 for lower cell junction with carrier concentration 1016~101'' crn-8
．． n Iny2Ga1 for back electrode contact with carrier concentration of about j×1018crn-8, Assi23・
(Fig. 3(C)).
これらの層／２０〜／コ３までの部分がＩｒｆ）ａＡｓ
下部セル／２４ｔである。These layers /20 to /ko3 are Irf)aAs
The lower cell is 24t.
このあと、第１図（（２）〜（Ｋ）の構造を得る工程を
第１の実施例と同様に行う。Thereafter, the steps for obtaining the structures shown in FIG. 1 ((2) to (K)) are performed in the same manner as in the first embodiment.
以上の工程によって作製した素子では、ＩｎＧａＡｓの
下部セル／２弘が高温にさらされることがないので、上
部セル／／ｚ−＼のＩｎの侵入がなく、上部セル／／乙
の劣化はみられない。ＡＭ／ 、 ／ ｏｏｍＷＡｄの
太陽光に対し、変換効率２グ〜２ｊ％とかなりの特性の
改善をみた。特に上部セル／／１と下部セル／２１Ｉ−
をつないでいる接続部／／りの不整格子によるオーミッ
ク接続が良いだめ、レンズによる通常の太陽光の１０倍
程度の集光をしても変換効率は落ちなかった。In the device manufactured by the above process, the lower InGaAs cell /2 is not exposed to high temperatures, so there is no intrusion of In in the upper cell //z-\, and no deterioration of the upper cell /2 is observed. do not have. For AM/, /oomWAd sunlight, we observed a significant improvement in the conversion efficiency, with a conversion efficiency of 2g to 2j%. Especially the upper cell //1 and the lower cell /21I-
Thanks to the good ohmic connection made by the mismatched lattice at the connecting part, the conversion efficiency did not drop even when the lens focused about 10 times the amount of normal sunlight.
以上説明したように、本発明によれば上部セルを先に作
製するので、熱に弱い下部セルを高温にさらすことなく
多接合半導体構造を作製できる。As explained above, according to the present invention, since the upper cell is manufactured first, a multijunction semiconductor structure can be manufactured without exposing the lower cell, which is sensitive to heat, to high temperatures.
よって、上部セルを高温で長時間かけて成長しても、下
部セルは劣化しない。Therefore, even if the upper cell grows at high temperature for a long time, the lower cell will not deteriorate.
このように本発明では、多接合半導体構造中の各機能部
分を最適の条件で成長でき、かつ互いに他の部分の劣化
を伴うことがないため、高効率の光電変換素子を得られ
る。As described above, in the present invention, each functional part in a multi-junction semiconductor structure can be grown under optimal conditions, and each functional part can be grown without deterioration of other parts, so that a highly efficient photoelectric conversion element can be obtained.
また基板を除去しているため軽量となっている。Also, since the substrate is removed, it is lightweight.
ところで、一般にｎ 層を作る際にｎドーパント（ｓｎ
、ｓｉ等）はまずｎ＋＋層表面に堆積し、その後拡散に
よシｎ＋＋層内に拡がるため、ｎ＋＋層表面は高濃度に
なるが表面から遠ざかるにつれて濃度が低くなる。本発
明によれば、トンネル接合部をｎ＋＋層、Ｐ 層の順に
作るのでＰｎ接合部分を高濃度にできるため、よシ良い
特性が得られる（特にＭＢＥ法の場合）。By the way, when forming an n layer, an n dopant (sn
, si, etc.) are first deposited on the surface of the n++ layer and then spread into the n++ layer by diffusion, so that the concentration is high at the surface of the n++ layer, but the concentration decreases as you move away from the surface. According to the present invention, since the tunnel junction is formed in the order of the n++ layer and the P layer, the concentration of the Pn junction can be made high, so that better characteristics can be obtained (particularly in the case of the MBE method).
更に、第２の実施例のような材料系の場合、格子不整合
面は上下セルの間の一面でよく、この格子不整合面も本
発明では、禁制帯内準位を利用することによってオーミ
ック接続をとることができるので上下セルを電気的に接
続することが容易にできる。Furthermore, in the case of a material system like the second embodiment, the lattice mismatching surface may be one surface between the upper and lower cells, and in the present invention, this lattice mismatching surface can also be made ohmic by utilizing the levels in the forbidden band. Since the connection can be made, it is easy to electrically connect the upper and lower cells.
第１図は、本発明による第１の実施例の多接合半導体光
電変換素子の製造工程を示す図、第２図はｊｒＯｏＣで
成長した多接合半導体光電変換素子のトンネル特性を示
す図、第３図は本発明による第２の実施例の多接合半導
体光電変換素子の製造工程を示す図、第グ図は多接合半
導体光電変換素子の概略断面図、第！図はＡ７！ＧａＡ
ｓ上部セルのＭＢＥ成長温度に対する短絡光電流密度及
び少数キャリア拡散長を示す図、第２図は高温成長での
多接合半導体光電変換素子のトンネル特性の劣化を示し
た図。
ｒ・・・ＧａＡｓ基板、り・・・ＧａＡｓバッファ層、
１０・・・ＡｔＧａＡｓストップエッチ層、／／・・・
ＧａＡ３オーミックコンタクト層、／ｌ・・・ＡｔＧａ
Ａｓ上部接合部、／９・・・トンネル接合を用いた接続
部、２３・・・ＧａＡ ｓ下部接合部、／／２・・・Ｇ
ａＡｓ上部セル、／／り・・・格子不整のある接続部、
／２グ・・・ＩｎＧａＡｓ下部セル。FIG. 1 is a diagram showing the manufacturing process of a multi-junction semiconductor photoelectric conversion device according to a first embodiment of the present invention, FIG. 2 is a diagram showing tunneling characteristics of a multi-junction semiconductor photoelectric conversion device grown with jrOoC, and FIG. The figures are diagrams showing the manufacturing process of a multi-junction semiconductor photoelectric conversion device according to a second embodiment of the present invention. The diagram is A7! GaA
FIG. 2 is a diagram showing the short-circuit photocurrent density and minority carrier diffusion length with respect to the MBE growth temperature of the upper cell. FIG. r...GaAs substrate, r...GaAs buffer layer,
10...AtGaAs stop etch layer, //...
GaA3 ohmic contact layer, /l...AtGa
As upper junction, /9...Connection using tunnel junction, 23...GaAs lower junction, //2...G
aAs upper cell, //ri...connection with lattice irregularity,
/2g...InGaAs lower cell.
Claims (4)
合半導体光電変換素子の製造方法において、基板上に前
記上部セルを形成する工程と、その後前記上部セル上に
前記接続部を形成する工程と、更にその後前記接続部上
に前記上部セルの形成温度より低い温度で前記下部セル
を形成する工程と、前記基板を除去する工程とを含むこ
とを特徴とする多接合半導体光電変換素子の製造方法。(1) A method for manufacturing a multi-junction semiconductor photoelectric conversion element in which an upper cell and a lower cell are connected at a connecting portion, including a step of forming the upper cell on a substrate, and then forming the connecting portion on the upper cell. A multi-junction semiconductor photoelectric conversion element comprising the steps of: forming the lower cell on the connection portion at a temperature lower than the formation temperature of the upper cell; and removing the substrate. manufacturing method.
にＡｌ＿ｘ＿＿０Ｇａ＿１＿−＿ｘ＿＿０Ａｓ層が設け
られた構造であって、前記基板の除去工程は前記ＧａＡ
ｓ層をエッチングし前記Ａｌ＿ｘ＿＿０Ｇａ＿１＿−＿
ｘ＿＿０Ａｓ層を殆んどエッチングしないエッチング液
で前記ＧａＡｓダミー基板及び前記ＧａＡｓ層を除去し
た後、前記Ａｌ＿ｘ＿＿０Ｇａ＿１＿−＿ｘ＿＿０Ａｓ
層に対するエッチング速度が他のＡｌＧａＡｓ層のエッ
チング速度よりも早いエッチング液で前記Ａｌ＿ｘ＿＿
０Ｇａ＿１＿−＿ｘ＿＿０Ａｓ層を除去する工程である
ことを特徴とする特許請求の範囲第１項記載の多接合半
導体光電変換素子の製造方法。(2) The substrate has a structure in which an Al_x__0Ga_1_-_x__0As layer is provided on a GaAs layer on a GaAs dummy substrate, and the step of removing the substrate is performed using the GaAs layer.
Etching the s layer and forming the Al_x__0Ga_1_-_
After removing the GaAs dummy substrate and the GaAs layer with an etching solution that hardly etches the x__0As layer, the Al_x__0Ga_1_-_x__0As
The Al_x__
2. The method for manufacturing a multi-junction semiconductor photoelectric conversion element according to claim 1, wherein the step is to remove the 0Ga_1_-_x__0As layer.
ンタクト層、窓用Ｐ＾＋Ａｌ＿ｘ＿＿１Ｇａ＿１＿−＿
ｘ＿＿１Ａｓ層、上部セル接合用Ｐ＾＋Ａｌ＿ｘ＿＿２
Ｇａ＿１＿−＿ｘ＿＿２層、上記セル接合用ｎＡｌ＿ｘ
＿＿２Ｇａ＿１＿−＿ｘ＿＿２Ａｓ層及び裏窓層用のｎ
＾＋Ａｌ＿ｘ＿＿３Ｇａ＿１＿−＿ｘ＿＿３Ａｓ層をこ
の順に積層する工程で、前記接続部の形成工程はｎ＾＋
ＧａＡｓ層及びＰ＾＋＾＋ＧａＡｓ層をこの順に積層す
るトンネル接合部の形成工程で、前記下部セルの形成工
程は、下部セル接合用 Ｐ＾＋ＧａＡｓ層、下部セル接合用ｎＧａＡｓ層及び裏
面電極コンタクト用ｎ＾＋ＧａＡｓ層をこの順に積層す
る工程であることを特徴とする特許請求の範囲第１項記
載の多接合半導体光電変換素子の製造方法。(3) The formation process of the upper cell is a GaAs ohmic contact layer, P^+Al_x__1Ga_1_-_ for the window.
x__1 As layer, P^+Al_x__2 for upper cell junction
Ga_1_-_x__2 layer, nAl_x for the above cell junction
___2Ga_1_-_x__2n for As layer and back window layer
In the step of stacking the ^+Al_x__3Ga_1_-_x__3As layers in this order, the step of forming the connection part is n^+
In the step of forming a tunnel junction in which a GaAs layer and a P^+^+GaAs layer are laminated in this order, the step of forming the lower cell includes a P^+GaAs layer for the lower cell junction, an nGaAs layer for the lower cell junction, and a back electrode contact layer. The method for manufacturing a multi-junction semiconductor photoelectric conversion device according to claim 1, characterized in that the step is to stack n^+GaAs layers in this order.
ンタクト層、窓用Ｐ＾＋Ａｌ＿ｘ＿＿１Ｇａ＿１＿−＿
ｘ＿＿１Ａｓ層、上部セル接合用Ｐ＾＋Ａｌ＿ｘ＿＿４
Ｇａ＿１＿−＿ｘ＿＿４Ａｓ層、上部セル接合用ｎＡｌ
＿ｘ＿＿４Ｇａ＿１＿−＿ｘ＿＿４Ａｓ層及び裏窓層用
のｎ＾＋Ａｌ＿ｘ＿＿５Ｇａ＿１＿−＿ｘ＿＿５Ａｓ層
をこの順に積層する工程で、前記接続部の形成工程はｎ
＾＋＾＋Ａｌ＿ｘ＿＿６Ｇａ＿１＿−＿ｘ＿＿６Ａｓ層
及びＰ＾＋＾＋Ｉｎ＿ｙ＿＿１Ｇａ＿１＿−＿ｙ＿＿１
Ａｓ層をこの順に積層する格子不整のある接続部の形成
工程で、前記下部セルの形成工程はバッファ層用Ｐ＾＋
Ｉｎ＿ｙ＿＿２Ｇａ＿１＿−＿ｙ＿＿２Ａｓ層、下部セ
ル接合用のＰ＾＋Ｉｎ＿ｙ＿＿２Ｇａ＿１＿−＿ｙ＿＿
２Ａｓ層、下部セル接合用ｎＩｎ＿ｙ＿＿２Ｇａ＿１＿
−＿ｙ＿＿２Ａｓ層及び裏面電極コンタクト用ｎ＾＋Ｉ
ｎ＿ｙ＿＿２Ｇａ＿１＿−＿ｙ＿＿２Ａｓ層をこの順に
積層する工程であることを特徴とする特許請求の範囲第
１項記載の多接合半導体光電変換素子の製造方法。(4) The formation process of the upper cell is a GaAs ohmic contact layer, P^+Al_x__1Ga_1_-_ for the window.
x__1 As layer, P^+Al_x__4 for upper cell junction
Ga_1_-_x__4As layer, nAl for upper cell junction
In the step of laminating the _x__4Ga_1_-_x__4As layer and the n^+Al_x__5Ga_1_-_x__5As layer for the back window layer in this order, the step of forming the connection part is n
^+^+Al_x__6Ga_1_-_x__6As layer and P^+^+In_y__1Ga_1_-_y__1
In the process of forming a connection part with lattice misalignment in which As layers are laminated in this order, the process of forming the lower cell is performed using P^+ for the buffer layer.
In_y__2Ga_1_-_y__2As layer, P^+In_y__2Ga_1_-_y__ for lower cell junction
2As layer, nIn_y__2Ga_1_ for lower cell junction
-_y__2As layer and back electrode contact n^+I
The method for manufacturing a multi-junction semiconductor photoelectric conversion device according to claim 1, characterized in that the step is to stack n_y__2Ga_1_-_y__2As layers in this order.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61135521A JPS62291183A (en) | 1986-06-11 | 1986-06-11 | Manufacture of multijunction semiconductor photoelectric conversion element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61135521A JPS62291183A (en) | 1986-06-11 | 1986-06-11 | Manufacture of multijunction semiconductor photoelectric conversion element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62291183A true JPS62291183A (en) | 1987-12-17 |
Family
ID=15153710
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61135521A Pending JPS62291183A (en) | 1986-06-11 | 1986-06-11 | Manufacture of multijunction semiconductor photoelectric conversion element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62291183A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007105675A1 (en) * | 2006-03-13 | 2007-09-20 | Shin-Etsu Chemical Co., Ltd. | Method for manufacturing substrate for photoelectric conversion element |
| US7488890B2 (en) | 2003-04-21 | 2009-02-10 | Sharp Kabushiki Kaisha | Compound solar battery and manufacturing method thereof |
| JP2009065208A (en) * | 2008-12-12 | 2009-03-26 | Sharp Corp | Compound solar cell and manufacturing method therefor |
| JP2009076921A (en) * | 2007-09-24 | 2009-04-09 | Emcore Corp | Multijunction solar cell and manufacturing method thereof |
| JP2010010704A (en) * | 2009-10-06 | 2010-01-14 | Sharp Corp | Compound solar cell and method of manufacturing the same |
| JP2010118666A (en) * | 2008-11-14 | 2010-05-27 | Emcore Solar Power Inc | Alternative substrate of inversion altered multi-junction solar battery |
| WO2013047059A1 (en) * | 2011-09-30 | 2013-04-04 | シャープ株式会社 | Laminated body for manufacturing compound semiconductor solar cell, compound semiconductor solar cell, and method for manufacturing compound semiconductor solar cell |
-
1986
- 1986-06-11 JP JP61135521A patent/JPS62291183A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7488890B2 (en) | 2003-04-21 | 2009-02-10 | Sharp Kabushiki Kaisha | Compound solar battery and manufacturing method thereof |
| WO2007105675A1 (en) * | 2006-03-13 | 2007-09-20 | Shin-Etsu Chemical Co., Ltd. | Method for manufacturing substrate for photoelectric conversion element |
| JP2007250575A (en) * | 2006-03-13 | 2007-09-27 | Shin Etsu Chem Co Ltd | Manufacturing method of substrate for photoelectric conversion element |
| US7935611B2 (en) | 2006-03-13 | 2011-05-03 | Shin-Etsu Chemical Co., Ltd. | Method for manufacturing substrate for photoelectric conversion element |
| JP2009076921A (en) * | 2007-09-24 | 2009-04-09 | Emcore Corp | Multijunction solar cell and manufacturing method thereof |
| JP2010118666A (en) * | 2008-11-14 | 2010-05-27 | Emcore Solar Power Inc | Alternative substrate of inversion altered multi-junction solar battery |
| JP2009065208A (en) * | 2008-12-12 | 2009-03-26 | Sharp Corp | Compound solar cell and manufacturing method therefor |
| JP2010010704A (en) * | 2009-10-06 | 2010-01-14 | Sharp Corp | Compound solar cell and method of manufacturing the same |
| WO2013047059A1 (en) * | 2011-09-30 | 2013-04-04 | シャープ株式会社 | Laminated body for manufacturing compound semiconductor solar cell, compound semiconductor solar cell, and method for manufacturing compound semiconductor solar cell |
| JP2013077724A (en) * | 2011-09-30 | 2013-04-25 | Sharp Corp | Laminate for manufacturing compound semiconductor solar cell, compound semiconductor solar cell, and method of manufacturing the same |
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