JPS62281434A - Chip carrier package - Google Patents
Chip carrier packageInfo
- Publication number
- JPS62281434A JPS62281434A JP61123327A JP12332786A JPS62281434A JP S62281434 A JPS62281434 A JP S62281434A JP 61123327 A JP61123327 A JP 61123327A JP 12332786 A JP12332786 A JP 12332786A JP S62281434 A JPS62281434 A JP S62281434A
- Authority
- JP
- Japan
- Prior art keywords
- heat sink
- substrate
- semiconductor element
- chip
- silicone gel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 14
- KZHJGOXRZJKJNY-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Si]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O KZHJGOXRZJKJNY-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052863 mullite Inorganic materials 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims abstract description 4
- 229910015365 Au—Si Inorganic materials 0.000 claims abstract 2
- 229920001296 polysiloxane Polymers 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 16
- 238000002347 injection Methods 0.000 claims description 7
- 239000007924 injection Substances 0.000 claims description 7
- 230000005496 eutectics Effects 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 239000006023 eutectic alloy Substances 0.000 abstract description 3
- 238000001816 cooling Methods 0.000 abstract 2
- 239000000945 filler Substances 0.000 abstract 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 239000000499 gel Substances 0.000 description 20
- 238000005516 engineering process Methods 0.000 description 7
- 238000001723 curing Methods 0.000 description 6
- 239000003795 chemical substances by application Substances 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 238000004132 cross linking Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 3
- 230000035515 penetration Effects 0.000 description 3
- 238000003848 UV Light-Curing Methods 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229920001971 elastomer Polymers 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000003921 oil Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 235000010627 Phaseolus vulgaris Nutrition 0.000 description 1
- 244000046052 Phaseolus vulgaris Species 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 125000000217 alkyl group Chemical group 0.000 description 1
- 229910001579 aluminosilicate mineral Inorganic materials 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 238000009833 condensation Methods 0.000 description 1
- 230000005494 condensation Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000002075 main ingredient Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 239000004447 silicone coating Substances 0.000 description 1
- 229920002545 silicone oil Polymers 0.000 description 1
- 229920002379 silicone rubber Polymers 0.000 description 1
- 239000004945 silicone rubber Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
〔産業上の利用分野〕
本発明はチップキャリアパッケージに関し、特に、その
多ピン化技術、熱抵抗低減技術および信頼性向上技術に
関する。Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a chip carrier package, and in particular, to technology for increasing the number of pins, technology for reducing thermal resistance, and technology for improving reliability.
大型コンピュータ（スーパーコンビエータ）に用いられ
るチップキャリアタイプパッケージとして従来提唱され
ている構造例の一つに、配線基板上に、フィルムキャリ
ア方式（別称Ｔ Ａ Ｂ方式、Ｔａｐｅ Ａｕｔｏｍａ
ｔｅｄ Ｂｏｎｄｉｎｇ Ｓｙｓｔｅｍ）により得られ
たＴＡＢ素子をフェイスダウンボンディング方式により
接合し、該素子の裏面に接合材を介して断面が凹字状の
金属キャップを密着させ、該キャンプの下端部と当該配
線基板の内面とを半田により接合して封止する構造のも
のがある。このパッケージは、パッケージ（配線基板）
の裏面に半田付は可能な電極パッドが引出されており、
該パッドにより、プリント基板などの実装基板の導体面
に実装できるような形の、チップキャリアタイプパッケ
ージに構成されている。One of the structural examples conventionally proposed for chip carrier type packages used in large computers (super combinators) is a film carrier type (also known as T A B type, Tape Automa) on a wiring board.
ted Bonding System) is bonded by a face-down bonding method, and a metal cap with a concave cross section is closely attached to the back side of the element via a bonding material, and the lower end of the camp and the wiring board are bonded. There is a structure in which the inner surface of the inner surface is bonded with solder and sealed. This package is a package (wiring board)
Electrode pads that can be soldered are pulled out on the back side of the
The pads form a chip carrier type package that can be mounted on the conductor surface of a mounting board such as a printed circuit board.
この従来例では、上記配線基板にアルミナ多層基顧を使
用しており、その為、素子（チップ）との直接接合では
熱歪を生じるために、上記ＴＡＢ素子によるよう釦、素
子とアルミナ配線基板との間に熱歪な緩和させる部材を
介在させる必要があり、かかるＴＡＢ素子により、その
周辺に引出されたリードを配線基板の導体部に接合する
形であるため、多ビン化という面で限界がある。In this conventional example, an alumina multilayer substrate is used for the above-mentioned wiring board, and therefore, direct bonding with the element (chip) causes thermal strain, so the button, element and alumina wiring board are connected by the above-mentioned TAB element. It is necessary to interpose a member to alleviate thermal strain between the TAB element and the leads drawn out around the TAB element to be connected to the conductor part of the wiring board, so there is a limit in terms of increasing the number of bins. There is.
なお、チップキャリアタイプパッケージおよびＴＡＢ方
式について述べた文献の例としては１９８０年１月１５
日（株）工業調食会発行ｒＩＣ化実装技術」ｐ１４１〜
１４４、ｐ１７５およびｐ８４〜８５がある。An example of a document describing the chip carrier type package and the TAB method is January 15, 1980.
"rIC implementation technology" published by Kogyo Choshokukai Co., Ltd. p141~
144, p175 and p84-85.
本発明は新規な構造を有するチップキャリアパッケージ
を提供し、かかる従来技術の有する欠点を解消し、より
一層の多ビン化が可能な、フリップチップ実装を実現し
、熱抵抗の低減を図り、高信頼性のパッケージを提供す
るＯとを目的とてる。The present invention provides a chip carrier package with a novel structure, eliminates the drawbacks of the conventional technology, realizes flip-chip mounting that allows for an even larger number of bins, reduces thermal resistance, and achieves high performance. The aim is to provide a reliable package.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.
本願において開示されろ発明のうち代表的なものの概要
を簡単に説明丁れば、下記のとおりである。A brief summary of representative inventions disclosed in this application is as follows.
丁なわち、本発明では、ヒートシンクとしてシリコーン
グル注入口を有するＳｉＣ放熱板を接合してなる半導体
チップを、ムライトよりなる配線基板にフリップチップ
方式により接合し、前記注入口よりシリコーンゲルな注
入して、当該チップと配線基板との接合部を当該ゲルに
より保護してなる主要構造を有してなるチップキャリア
パッケージに係わる。That is, in the present invention, a semiconductor chip formed by bonding a SiC heat sink having a silicone gel injection port as a heat sink is bonded to a wiring board made of mullite by a flip-chip method, and silicone gel is injected from the injection port. The present invention relates to a chip carrier package having a main structure in which the bond between the chip and the wiring board is protected by the gel.
本発明ではフリップチップ方式によりチップを配線基板
に接合するので高密度化が可能で、より一層の多ピン化
の要請に答えることができる。また、チップには熱伝導
性の良いＳｉＣ放熱板が接合されているので、熱抵抗が
低減される。さらに、フリップチップ接合部はシリコー
ンゲルにより保Ｆｉされ、封止の信頼性が高い。In the present invention, since the chip is bonded to the wiring board using the flip-chip method, it is possible to increase the density and meet the demand for an even higher number of pins. Furthermore, since a SiC heat sink with good thermal conductivity is bonded to the chip, thermal resistance is reduced. Furthermore, the flip-chip joint is protected by silicone gel, resulting in high sealing reliability.
次に、本発明の実施例を図面に基づいて説明する。 Next, embodiments of the present invention will be described based on the drawings.
＠１図は本発明によるチップキャリアパッケージの断面
図の一例を示し、また、第２図は本発明によるチップキ
ャリアパッケージの組豆説明図を示す。@ Figure 1 shows an example of a sectional view of a chip carrier package according to the present invention, and Figure 2 shows an explanatory diagram of assembly of the chip carrier package according to the present invention.
半導体素子１の一方の面に、ヒートシンク２を接合する
。A heat sink 2 is bonded to one surface of the semiconductor element 1.
半導体素子（チップ）１は、例えばシリコン単結晶基板
から成り、周知の技術によってこのチップ内には多数の
回路素子が形成され、１つの回路機能が与えられている
。回路素子の具体例は、例えばＭｏＳトランジスタから
成り、これらの回路素子によりて、例えば論理回路およ
びメモリの回路機能が形成されている。A semiconductor element (chip) 1 is made of, for example, a silicon single crystal substrate, and a large number of circuit elements are formed within this chip using well-known techniques to provide one circuit function. A specific example of the circuit element is, for example, a MoS transistor, and these circuit elements form, for example, a logic circuit and a memory circuit function.
ヒートシンク２は、例えば放熱板より成り、熱伝導性の
良い絶縁材により構成されているとよい。The heat sink 2 is preferably made of a heat sink, for example, and made of an insulating material with good thermal conductivity.
ＳｉＣ放熱板はその好ましい例として例示される。A SiC heat sink is exemplified as a preferable example.
該ヒートシンク２には適宜の位置に後述するシリコーン
グルを注入するだめの、注入口３が設げられている。第
２図に示すように、該放熱板２の端部に適宜の大きさに
該注入口３があけられているとよい。The heat sink 2 is provided with an injection port 3 at an appropriate position for injecting silicone glue, which will be described later. As shown in FIG. 2, it is preferable that the injection port 3 is opened in an appropriate size at the end of the heat dissipation plate 2.
半導体素子１とＳｉＣ放熱板２との接合は各種の方法に
より可能である。例えば、ＳｉＣ放熱板２の裏面にＡｕ
メタライズ層を施しておぎ、Ａｕ−８ｉ共晶合金層４を
形成するようにして接合することができろ。The semiconductor element 1 and the SiC heat sink 2 can be bonded by various methods. For example, Au on the back side of the SiC heat sink 2.
After a metallized layer is applied, the Au-8i eutectic alloy layer 4 can be formed and bonded.
このよ５Ｋ、あらかじめ熱伝導性の良い絶縁性のヒート
シンク２を有する半導体素子を、配線基板５に固着させ
る。At this time, the semiconductor element having the insulating heat sink 2 with good thermal conductivity is fixed to the wiring board 5 in advance.
当該配線基板５は、ムライトにより構成されているとよ
い。ムライトは、単鎖構造をもつアルミノケイ酸塩鉱物
であり、その組成は３ Ａ−ｅ ｔ Ｏｓ・２３ ｉ
０．〜２Ａ−６．０．８ ｉｏ、ｆ示ｇれ、一般に９０
〜９４％アルミナセラミックスによるセラミック基板と
は異なる。該ムライト基板５の使用により、半導体素子
１はフリップチップ実装が可能となる。The wiring board 5 is preferably made of mullite. Mullite is an aluminosilicate mineral with a single-chain structure, and its composition is 3 A-e t Os・23 i
0. ~2A-6.0.8 io, f shown, generally 90
This is different from a ceramic substrate made of ~94% alumina ceramics. By using the mullite substrate 5, the semiconductor element 1 can be mounted by flip-chip.
フリップチップとは、チップを裏返してその表面または
基板に形成された接続端子を用いてボンディングする、
いわゆるフェイスダウンポンディングすることから与え
られた呼称であり、フリップチップには形成する接続端
子の形態によって、チップに金属ボールをつげるボール
方式や、突起電極をつげろバンプ方式や基板にペデスタ
ルをつｈるペデスタル方式などがある。本発明はこれら
各穐の方式が可能であるが、その−例な示すと、Ａ２電
極を形成したブレーナ素子の表面を保護用ガラスで被覆
し、次いで電極部のガラス膜を除去し、Ｃｒ −Ｃｕ−
Ａｕの多層金属で電極下地を形成し、５ｎ−Ｐｂを用い
て半球状のバンプ（突起電極）を形成する、いわゆるＣ
ＣＢ（コンドロールド・コラップス、ボンディング）方
式があげられる。Flip chip is a process in which the chip is turned over and bonded using connection terminals formed on its surface or substrate.
The name is derived from the so-called face-down bonding process, and depending on the form of the connection terminal formed on the flip chip, there are two types of flip chips: a ball method in which a metal ball is attached to the chip, a bump method in which a protruding electrode is attached to the chip, and a pedestal method in which a pedestal is attached to the substrate. There is also a pedestal method. The present invention can be applied to each of these methods, but as an example, the surface of the Brehner element on which the A2 electrode is formed is coated with protective glass, then the glass film on the electrode part is removed, and Cr- Cu-
The so-called C
One example is the CB (chondral collapse, bonding) method.
第１図に示す符号６は、かかるＣＣＢ方式による、半導
体素子１と配線基板５との接合部を示す。Reference numeral 6 shown in FIG. 1 indicates a joint portion between the semiconductor element 1 and the wiring board 5 using the CCB method.
半導体素子ｌ内の前記ＡＡ電極による内部配線は、当該
接合部６を介し、さらに、当該配線基板５内に設げられ
た、例えばス）ｖ−ホール技術による内部配線７を介し
て、該基板５の裏面に設けられた外部接続端子８との間
で電気的な導通がとられる。The internal wiring by the AA electrode in the semiconductor element 1 is connected to the substrate via the bonding portion 6 and further via the internal wiring 7 provided in the wiring board 5 using, for example, V-hole technology. Electrical continuity is established with an external connection terminal 8 provided on the back surface of 5.
外部接続端子８は、例えば６０／４０半田よりなる突起
電極により構成される。プリント基板などの実装基板に
、該端子８を溶融させて面付は実装が可能となっている
。The external connection terminal 8 is constituted by a protruding electrode made of 60/40 solder, for example. Surface mounting is possible by melting the terminal 8 onto a mounting board such as a printed circuit board.
ムライト配線基板５には第１図および第２図に示すよう
に、ダム９が周設されている。As shown in FIGS. 1 and 2, a dam 9 is provided around the mullite wiring board 5. As shown in FIGS.
上記した接合部６を外部雰囲気中の湿分なと外的環境か
ら保護するため、当該枠内にシリコーンゲ＃１０を、前
記ＳｉＣ放熱板２の注入口３から、注入し、当該接合部
６を該シリコーンゲル１０により被覆する。In order to protect the above-mentioned joint part 6 from the external environment such as moisture in the external atmosphere, silicone gel #10 is injected into the frame from the injection port 3 of the SiC heat sink 2. is coated with the silicone gel 10.
本発明に使用されるシリコーン（系）ゲル１０としては
、従来エレクトロニクスあるいはオプティカルファイバ
ー用シリコーンコーディング剤として市販されていたも
のを使用でき、例えばシリコーンゲルはＩＣメモリのソ
フトエラ一対策用として用いられていた。As the silicone gel 10 used in the present invention, those commercially available as silicone coating agents for electronics or optical fibers can be used. For example, silicone gel has been used as a countermeasure against soft errors in IC memory. .
本発明はこれを封止材料として使用せんとするものであ
る。The present invention aims to use this as a sealing material.
ゲルは、その加熱硬化前はリキッド状態であり、１液タ
イプ、２液タイプがあり、例えば主剤と硬化剤とからな
る２液タイプの場合、これらを混合すると反応硬化（架
橋反応）し、硬化物を得る。Gel is in a liquid state before it is heated and cured, and there are two-component types and one-component types. For example, in the case of a two-component type consisting of a main ingredient and a curing agent, when they are mixed together, they undergo reaction curing (crosslinking reaction) and hardening. get something
硬化システムとしては次の反応式で示す様に、縮合型、
付加型、紫外線硬化型がある。As shown in the following reaction formula, the curing system is condensation type,
There are addition type and UV curing type.
縮合型 Ｃａｔ ： ５ｎ−Ｔｉ系触媒 Ｒ：例えばアルキル基（以下同じ） 付加型 −Ｓ ｉ − 紫外線硬化型 硬化物を得るに、加熱（ベーク）するとゴム化が進む。condensed type Cat: 5n-Ti catalyst R: For example, an alkyl group (the same applies below) Additive type -S i - UV curing type To obtain a cured product, heating (baking) progresses the rubberization.
本発明に使用されるシリコーン系ゲル１０はシリコーン
ゴムやシリコーンオイルと異なり架橋密度の低いもので
ある。The silicone gel 10 used in the present invention has a low crosslinking density, unlike silicone rubber or silicone oil.
例えば架橋密度の大小からみるとゴムが架橋密度が一番
大で、その下がゲル、さらに、その下がオイルというこ
とになる。For example, in terms of crosslink density, rubber has the highest crosslink density, gel is below that, and oil is below that.
架橋密度は一般に針入度計を用いて測定され、針入度計
についてはＪＩＳＫ２８０８に規定され、それに使用さ
れる針についてはＡＳＴＭＤ １３２１に規格がある。The crosslinking density is generally measured using a penetrometer, and the penetrometer is specified in JISK2808, and the needle used therein is specified in ASTM D 1321.
針入度からみて、一般に、ゲルは４０〜２００ｍ１の範
囲、オイルは４０８１以下であり、ゲルの硬化反応の促
進によりゴム化が起こり、ゴムと称されているものは一
般に針入度２００＋ｉ＋ａ以上である。In terms of penetration, gel is generally in the range of 40 to 200 ml, oil is 4081 or less, and rubberization occurs due to the acceleration of the curing reaction of gel, and what is called rubber generally has a penetration of 200 + i + a or more. be.
本発明に使用されるシリコーン系ゲル１０には前記の如
く、市販のものが使用され、例えば信越化学工業社製Ｋ
ＪＲ９０１０，Ｘ−３５−１００，東しシリコーン社ｇ
ＪｃＲ６１１０などが使用できる。As mentioned above, commercially available silicone gels are used as the silicone gel 10 used in the present invention, such as K manufactured by Shin-Etsu Chemical Co., Ltd.
JR9010, X-35-100, Toshi Silicone Company g
JcR6110 etc. can be used.
上記Ｘ−３５−１００（Ａ（主剤）、Ｂ（硬化剤）２液
タイプ、針入度１００〕の硬化反応機構は白金付加型で
、２液低温高温用ゲルで一７５〜２５０″Ｃの温度範囲
で使用できる。The curing reaction mechanism of the above X-35-100 (A (base ingredient), B (curing agent) two-part type, penetration rate 100) is a platinum addition type, and is a two-part low temperature and high temperature gel. Can be used in a temperature range.
ダム９（ま、主として当該シリコーンゲル１０注入時の
流れ止め用に使用されろ。Dam 9 (well, it's mainly used to stop the flow when injecting the silicone gel 10).
ダム９は当該配線基板５と一体であればよく、当該基板
５に、ＳｉＣ放熱板２を有する半導体素子１を収納でき
る凹部を設げれば済む。The dam 9 only needs to be integrated with the wiring board 5, and it is sufficient to provide the board 5 with a recess in which the semiconductor element 1 having the SiC heat sink 2 can be accommodated.
本発明によれば配線基板５にムライトよりなるものを使
用することによりフリップチップ実装が可能となり、多
ピン化を促進できろ。半導体素子１はあらかじめ熱伝導
性の良好なＳｉＣ放熱板２が接合されているので熱抵抗
を低減できろ。According to the present invention, by using a material made of mullite for the wiring board 5, flip-chip mounting becomes possible and the number of pins can be increased. Since the semiconductor element 1 is bonded with the SiC heat sink 2 having good thermal conductivity in advance, the thermal resistance can be reduced.
配？ｆＭ基板５にはダムを形成することにより、フリッ
プチップ接続部６をシリコーンゲル１０により外部環境
から保護することができる。Distribution? By forming a dam on the fM substrate 5, the flip chip connection portion 6 can be protected from the external environment by the silicone gel 10.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で糧々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on examples, it is to be understood that the present invention is not limited to the above-mentioned examples, and can be modified as much as possible without departing from the gist of the invention. Not even.
例えば、前記実施例ではヒートシンクとして放熱板を例
示し１こが、放熱フィンなどであってもよい。For example, in the above embodiments, a heat sink is used as a heat sink, but instead of the heat sink, a heat sink may be used instead.
不発明はチップキャリアパッケージ全般に適用すること
ができろ。The invention can be applied to chip carrier packages in general.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明丁れば、下記のとおりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
第１図は本発明の実施例を示す断面図、第２図は本発明
の実施例を示す組豆説明図である。
１・・・半導体素子、２・・・放熱板（ヒート７ンク）
、３・・・シリコーンゲル注入口、４・・・Ａ ｕ −
Ｓ ｒ共晶合金層、５・・・配線基板、６・・・ＣＣＢ
接合部、７・・・内部配線、８・・・外部接続端子、９
・・・ダム、１０・・・シリコーンゲル。
代理人 弁理士 小 川 勝 男
第 １ 図
第 ２ 図FIG. 1 is a sectional view showing an embodiment of the present invention, and FIG. 2 is an explanatory diagram of assembled beans showing an embodiment of the present invention. 1... Semiconductor element, 2... Heat sink (heat 7 tank)
, 3... Silicone gel injection port, 4... A u −
S r eutectic alloy layer, 5... wiring board, 6... CCB
Joint part, 7... Internal wiring, 8... External connection terminal, 9
...Dam, 10...Silicone gel. Agent: Patent Attorney Katsoo Ogawa Figure 1 Figure 2
Claims (1)
配線基板にフリップチップ方式により接合し、当該素子
と当該基板との接合部をシリコーンゲルにより被覆して
成ることを特徴とするチップキャリアパッケージ。 ２、ヒートシンクが、シリコーンゲル注入口を有するＳ
ｉＣ放熱板よりなり、該ヒートシンクと半導体素子とを
Ａｕ−Ｓｉ共晶により接合し、配線基板がムライト材よ
り成り、かつその周辺にシリコーンゲル流れ止め用ダム
を形成して成り、該ダム内に前記放熱板のシリコーンゲ
ル注入口よりシリコーンゲルを注入して成る、特許請求
の範囲第１項記載のチップキャリアパッケージ。[Claims] 1. An assembly consisting of a semiconductor element bonded to a heat sink is bonded to a wiring board using a flip-chip method, and the bonded portion between the element and the substrate is covered with silicone gel. chip carrier package. 2.S where the heat sink has a silicone gel inlet
It is made of an iC heat sink, the heat sink and the semiconductor element are bonded by Au-Si eutectic, the wiring board is made of mullite material, and a dam for preventing the flow of silicone gel is formed around it, and within the dam. The chip carrier package according to claim 1, wherein silicone gel is injected from a silicone gel injection port of the heat sink.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61123327A JPS62281434A (en) | 1986-05-30 | 1986-05-30 | Chip carrier package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61123327A JPS62281434A (en) | 1986-05-30 | 1986-05-30 | Chip carrier package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62281434A true JPS62281434A (en) | 1987-12-07 |
Family
ID=14857809
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61123327A Pending JPS62281434A (en) | 1986-05-30 | 1986-05-30 | Chip carrier package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62281434A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05275580A (en) * | 1992-03-25 | 1993-10-22 | Nec Corp | Semiconductor device |
| JPH1149959A (en) * | 1997-08-05 | 1999-02-23 | Toshiba Silicone Co Ltd | Silicone gel composition for flame-retardant heat dissipative sheet and flame-retardant heat dissipative silicone sheet |
| WO2002081592A1 (en) * | 2001-03-30 | 2002-10-17 | Geltec Co., Ltd. | Extrudable bridged grease-like heat radiating material, container sealingly filled with the material, method of manufacturing the container, and method of radiating heat by the use thereof |
| US7304413B2 (en) * | 2005-08-10 | 2007-12-04 | Nihon Dempa Kogyo Co., Ltd. | Piezooscillator |
| JP2014187117A (en) * | 2013-03-22 | 2014-10-02 | Toyota Motor Corp | Cooling device |
-
1986
- 1986-05-30 JP JP61123327A patent/JPS62281434A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05275580A (en) * | 1992-03-25 | 1993-10-22 | Nec Corp | Semiconductor device |
| JPH1149959A (en) * | 1997-08-05 | 1999-02-23 | Toshiba Silicone Co Ltd | Silicone gel composition for flame-retardant heat dissipative sheet and flame-retardant heat dissipative silicone sheet |
| WO2002081592A1 (en) * | 2001-03-30 | 2002-10-17 | Geltec Co., Ltd. | Extrudable bridged grease-like heat radiating material, container sealingly filled with the material, method of manufacturing the container, and method of radiating heat by the use thereof |
| KR100818596B1 (en) | 2001-03-30 | 2008-04-01 | 젤텍 가부시키 가이샤 | Extrudable, crosslinked, greasy heat-radiating material, container filled with and sealing the same, process for producing the same container, and heat radiation method using the same container |
| US7304413B2 (en) * | 2005-08-10 | 2007-12-04 | Nihon Dempa Kogyo Co., Ltd. | Piezooscillator |
| JP2014187117A (en) * | 2013-03-22 | 2014-10-02 | Toyota Motor Corp | Cooling device |
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