JPS62274914A - Jitter generator - Google Patents
Jitter generatorInfo
- Publication number
- JPS62274914A JPS62274914A JP61118518A JP11851886A JPS62274914A JP S62274914 A JPS62274914 A JP S62274914A JP 61118518 A JP61118518 A JP 61118518A JP 11851886 A JP11851886 A JP 11851886A JP S62274914 A JPS62274914 A JP S62274914A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- jitter
- wave
- output
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 11
- 230000000630 rising effect Effects 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000005855 radiation Effects 0.000 description 1
Landscapes
- Manipulation Of Pulses (AREA)
- Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
- Monitoring And Testing Of Transmission In General (AREA)
Abstract
Description
【発明の詳細な説明】
3、発明の詳細な説明
〔概要〕
ジッタ発生器において、周波数nfoの波のレベルが周
波数f1の波のレベルより高い時は1が、低い時は0が
比較器から出力されるので、この出力の立上り点又は立
下り点の何れが一方でn分周器を動作させて、ジッタが
付加された。占有率がほぼ一定で周波数f。のパルス列
を得る様にしたものである。Detailed Description of the Invention 3. Detailed Description of the Invention [Summary] In the jitter generator, when the level of the wave of frequency nfo is higher than the level of the wave of frequency f1, 1 is output from the comparator, and when it is lower, 0 is output from the comparator. Since it is output, either the rising point or the falling point of this output operates the n frequency divider on the one hand, and jitter is added. The occupancy rate is almost constant and the frequency f. This is to obtain a pulse train of .
本発明は例えばPCM伝送装置の試験に使用するジッタ
発生器の改良に関するものである。The present invention relates to an improvement in a jitter generator used for testing PCM transmission equipment, for example.
一般に、ジッタは大別して中継伝送路で生ずる伝送路ジ
ッタと、多重化同期のためにパルススタッフ同期を適用
した場合に生ずるスタッフジッタに分けられるが、ジッ
タ発生器は伝送路ジッタに対応するジッタが付加された
パルス列(即ち、装置の試験用クロック)を発生ずるも
ので、このクロックの占有率がほぼ一定であることが必
要である。In general, jitter can be broadly divided into transmission line jitter that occurs on relay transmission lines and stuff jitter that occurs when pulse stuff synchronization is applied for multiplex synchronization. It generates an added pulse train (ie, a clock for testing the device), and it is necessary that the occupancy rate of this clock be approximately constant.
第4図は従来例のブロック図、第5図は第4図の動作説
明図で、第5図(a)はf。の波とflの波の交点が振
幅0の線よりも上にある場合、第5図fblは交点がそ
れよりも下にある場合を示す。尚、第5図中の数字は第
4図中の同し数字の部分の波形を示す。以下、第5図を
参照して第4図の動作を説明する。FIG. 4 is a block diagram of the conventional example, FIG. 5 is an explanatory diagram of the operation of FIG. 4, and FIG. 5(a) is f. When the intersection of the wave .f1 and the wave fl is above the zero amplitude line, FIG. 5 fbl shows the case where the intersection is below the line. Note that the numbers in FIG. 5 indicate the waveforms of the portions with the same numbers in FIG. The operation shown in FIG. 4 will be explained below with reference to FIG.
先ず、周波数f。の正弦波(以下f。の波と省略する)
はこの発生器の出力周波数を、f、の波はジッタ幅とジ
ッタの速度を決定するものであるが、例えばf。は数肛
2程度、fIは100Hz以下で、 faの方がflよ
りも非常に高い値となっている。First, the frequency f. sine wave (hereinafter abbreviated as f. wave)
is the output frequency of this generator, and the wave of f determines the jitter width and jitter speed, for example, f. The frequency is about a few degrees, and fI is less than 100 Hz, and fa has a much higher value than fl.
この様な2つの周波数の波が発振器1,2より比較器3
に加えられるが、第5図(a)、第5図(blに示す様
にf。の波のレベルがflの波のそれよりも高い時に比
較器3より例えば1が、低い時にはOが出力される。These two frequency waves are transmitted from oscillators 1 and 2 to comparator 3.
As shown in Figures 5(a) and 5(bl), when the level of the f wave is higher than that of the fl wave, the comparator 3 outputs, for example, 1, and when it is lower, O is output. be done.
ここで、第5図(81−■に示ずパルス列の立上り点a
″′はf。の波の立上り部分とflの波の交点aと一致
し、この位置はf。の波が振幅Oの線との交点Aよりも
Δ1だけ右側にシフトしている。そして、f、とf、の
波は傾きを持っている為にこの交点aの位置は時間と共
に変化し、第5図(bl−■の様にf。Here, the rising point a of the pulse train, not shown in FIG.
″′ coincides with the intersection point a of the rising part of the wave f. and the wave fl, and this position is shifted to the right by Δ1 from the intersection A where the wave f. Since the waves f and f have an inclination, the position of this intersection a changes with time, and as shown in Fig. 5 (bl-■), the position of the intersection point a changes with time.
の波とflの波の交点が振幅0の線の下側になった時は
A点よりも左側にΔ3だけシフトした所になる。When the intersection of the wave of and the wave of fl is below the line of zero amplitude, it is shifted to the left of point A by Δ3.
即ち、第5図(al−■及び第5図fbl−■に示した
様にパルス列の立」ニリ点が時間と共に変化するので(
これがジッタになる)、ジッタが付加されたパルス列が
比較器3から出力される。That is, as shown in FIG. 5 (al-■ and FIG.
This becomes jitter), and a pulse train to which jitter is added is output from the comparator 3.
ここで、第5図Fa+及び第5図fblに示ず様にfo
の波とf、の波の交点a、bがfoの波の尖頭値に近い
場合と反対側の尖頭値に近い場合とではパルス幅もが異
なる。しかし、前記の様にfoはfIよりも非常に高<
、foの波の相隣る立上り部分又は立下り部分は一定で
あるからパルス間隔Tがほぼ一定とみられるので、ジッ
タの大きさが変化すると比較器3より出力されるパルス
列の占有率t/Tが変化する。Here, as shown in Fig. 5 Fa+ and Fig. 5 fbl, fo
The pulse width also differs when the intersection points a and b of the waves f and f are close to the peak value of the wave fo and when they are close to the peak value on the opposite side. However, as mentioned above, fo is much higher than fI.
Since the adjacent rising or falling parts of the waves of , fo are constant, the pulse interval T is considered to be almost constant. Therefore, when the magnitude of jitter changes, the occupancy rate t/T of the pulse train output from the comparator 3 changes. changes.
一方、前記の様に装置に供給するクロックの占有率はほ
ぼぼ一定でなければならないので、シック発生器はこれ
を満足させる様なりロック(パルス列)を発生しなけれ
ばならないと言う問題点がある。On the other hand, as mentioned above, the occupancy rate of the clock supplied to the device must be almost constant, so there is a problem in that the sick generator must generate a lock (pulse train) in a way that satisfies this requirement. .
上記の問題点は第1図に示す様に、出力周波数のn倍の
周波数を持つ第1の発振器4と、ジッタ幅とジッタ速度
とを決定する第2の発振器2と、該第1及び第2の発振
器の出力を比較する比較器5と、該比較器の出力の周波
数をn分周するn分周器6とから構成された本発明のジ
ッタ発生器により解決される。The above problem is as shown in FIG. This problem is solved by the jitter generator of the present invention, which is composed of a comparator 5 that compares the outputs of two oscillators, and an n frequency divider 6 that divides the frequency of the output of the comparator by n.
本発明は、第5図(alに示ずf。の波の相隣る立上り
部分、又は立下り部分の間隔はf、 < f、の為にほ
ぼ等しいとしたので、これを利用して占有率がほぼ一定
のジッタ付きパルスを得る様にした。The present invention assumes that the intervals between adjacent rising or falling portions of waves f (not shown in FIG. A jittered pulse with a nearly constant rate was obtained.
即ち、従来はf。の波の立上り部分及び立下り部分とf
、の波の交点とでパルス幅が決定されているので、ジッ
タの大きさに対応してパルス幅が変化して占有率が変化
した。That is, conventionally f. The rising and falling parts of the wave and f
Since the pulse width is determined by the intersection of the waves of , the pulse width changes in accordance with the magnitude of the jitter, and the occupancy rate changes.
しかし、本発明ではfoの波の立下り部分又は立下り部
分とflの波の交点で分周器6を駆動して分周動作で占
有率を決定する様にした。そこで、ジッタの大きさが変
化しても占有率がほぼ一定のクロックを発生ずることが
できる。However, in the present invention, the frequency divider 6 is driven at the falling portion of the wave of fo or the intersection of the falling portion of the wave of fo and the wave of fl, and the occupation rate is determined by the frequency dividing operation. Therefore, it is possible to generate a clock whose occupancy rate is approximately constant even if the magnitude of jitter changes.
第2図は本発明の実施例のブロック図、第3図は第2図
の動作説明図を示す。尚、全図を通じて同一符号は同一
対象物を示す。以下、簡単の為にn=2として第3図を
参照しながら第2図の動作を説明する。ここで、第3図
中の数字は第2図の同じ数字の部分の波形を示す。FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of the operation of FIG. 2. Note that the same reference numerals indicate the same objects throughout the figures. Hereinafter, for the sake of simplicity, the operation shown in FIG. 2 will be explained with reference to FIG. 3, assuming that n=2. Here, the numbers in FIG. 3 indicate the waveforms of the portions with the same numbers in FIG.
先ず、第1の発振器4よりの周波数2foの波と第2の
発振器2よりの周波数f1の波とが比較器5で比較され
てジッタが付加された2foのパルスが出力される(第
3図−〇〜■参照)。そして、これをフリップフロップ
を用いた2分周器6′に加えて第3図−■に示す様にジ
ッタ及び周波数が騒されて占有率が50%になったf。First, a wave of frequency 2fo from the first oscillator 4 and a wave of frequency f1 from the second oscillator 2 are compared in the comparator 5, and a jittered pulse of 2fo is output (Fig. 3). −〇~■). Then, by adding this to a 2-frequency divider 6' using a flip-flop, the jitter and frequency are increased and the occupation rate becomes 50%, as shown in FIG.
のパルス列が得られる。A pulse train of 1 is obtained.
尚、フリップフロップ61は第3図〜■のパルスの立下
りで例えば0を出力し1次の立下りで1を出力する。The flip-flop 61 outputs, for example, 0 at the falling edge of the pulse shown in FIGS. 3 to 3, and outputs 1 at the primary falling edge.
以上、詳細に説明した様に占有率がほぼ50%でジッタ
が付加されたクロックを発生ずることが出来ると云う効
果がある。As described in detail above, there is an effect that a clock with an occupation rate of approximately 50% and jitter added can be generated.
第1図は本発明の原理ブロック図、
第2図は本発明の実施例のブロック図、第3図は第2図
の動作説明図、
第4図は従来例のブロック図、
第5図は第4図の動作説明図を示す。
図において、
2は第2の発振器、
4は第1の発振器、
5は比較器、
6はn分周器を示す。
本発明の原理ブロック図
IC
第2図
tK
輻
と
第2図の動イ乍説1H図
草3ZFig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is an explanatory diagram of the operation of Fig. 2, Fig. 4 is a block diagram of a conventional example, and Fig. 5 is a block diagram of an embodiment of the present invention. The operation explanatory diagram of FIG. 4 is shown. In the figure, 2 is a second oscillator, 4 is a first oscillator, 5 is a comparator, and 6 is an n frequency divider. Principle block diagram of the present invention IC Fig. 2 tK Radiation and movement of Fig. 2 Theory 1H Fig. 3Z
Claims (1)
、ジッタ幅とジッタ速度とを決定する第2の発振器(2
)と、該第1及び第2の発振器の出力を比較する比較器
(5)と、該比較器の出力の周波数をn分周するn分周
器(6)とから構成されたことを特徴とするジッタ発生
器。A first oscillator (4) with a frequency n times the output frequency, and a second oscillator (2) that determines the jitter width and jitter speed.
), a comparator (5) that compares the outputs of the first and second oscillators, and an n frequency divider (6) that divides the frequency of the output of the comparator by n. jitter generator.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61118518A JPS62274914A (en) | 1986-05-23 | 1986-05-23 | Jitter generator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61118518A JPS62274914A (en) | 1986-05-23 | 1986-05-23 | Jitter generator |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62274914A true JPS62274914A (en) | 1987-11-28 |
Family
ID=14738606
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61118518A Pending JPS62274914A (en) | 1986-05-23 | 1986-05-23 | Jitter generator |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62274914A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01169296U (en) * | 1988-05-20 | 1989-11-29 | ||
JP2008182643A (en) * | 2007-01-26 | 2008-08-07 | Matsushita Electric Works Ltd | Wireless transmitting circuit and wireless transmitter |
CN106160883A (en) * | 2015-03-27 | 2016-11-23 | 江苏艾科半导体有限公司 | A kind of RF transceiver Auto-Test System |
-
1986
- 1986-05-23 JP JP61118518A patent/JPS62274914A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01169296U (en) * | 1988-05-20 | 1989-11-29 | ||
JP2008182643A (en) * | 2007-01-26 | 2008-08-07 | Matsushita Electric Works Ltd | Wireless transmitting circuit and wireless transmitter |
CN106160883A (en) * | 2015-03-27 | 2016-11-23 | 江苏艾科半导体有限公司 | A kind of RF transceiver Auto-Test System |
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