JPS62268165A - Field effect transistor - Google Patents
Field effect transistorInfo
- Publication number
- JPS62268165A JPS62268165A JP11217186A JP11217186A JPS62268165A JP S62268165 A JPS62268165 A JP S62268165A JP 11217186 A JP11217186 A JP 11217186A JP 11217186 A JP11217186 A JP 11217186A JP S62268165 A JPS62268165 A JP S62268165A
- Authority
- JP
- Japan
- Prior art keywords
- inp
- layer
- doped gaas
- field effect
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 17
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 abstract description 7
- 238000005530 etching Methods 0.000 abstract description 2
- 239000012212 insulator Substances 0.000 abstract description 2
- 238000007493 shaping process Methods 0.000 abstract 1
- 239000012808 vapor phase Substances 0.000 abstract 1
- 230000004888 barrier function Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 150000004678 hydrides Chemical class 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/802—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with heterojunction gate, e.g. transistors with semiconductor layer acting as gate insulating layer, MIS-like transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電界効果トランジスタ、特にＩｎＰ動作層を用
いた電界効果トランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field effect transistor, and particularly to a field effect transistor using an InP active layer.
ＩｎＰ半導体結晶は電子の飽和速度が大きく、また熱伝
導率がＧａＡｓの３倍程度大きいことから超高速素子、
特に高出力用の超高周波素子材料として注目され、これ
を用い友電界効果トランジスタ（ＰＥＴ）の検討がいく
つか行なわれている。InP semiconductor crystal has a high electron saturation velocity and a thermal conductivity that is about three times higher than GaAs, making it suitable for ultra-high-speed devices.
In particular, it has attracted attention as a material for ultra-high frequency devices for high output, and several studies have been conducted on field effect transistors (PETs) using it.
第４図は例えばバレン（Ｂａｒｒｅｒａ ）及びアーチ
ャ−（Ａｒｃｈｅｒ ）Ｋより米国の雑誌アイ・イー・
イー・イー、）ランス オン エレクトロン デバイス
（Ｉ ＢＥＥ、 Ｔｒａｎｓ、 ｏｎ Ｅｌｅｃｔｒｏ
ｎ、 Ｄｅｖｉｃｅｓ。Figure 4 is, for example, from Barrera and Archer K.
I BEE, Trans, on Electron device (I BEE, Trans, on Electron device)
n, Devices.
ｖｏＣＥＤ−２２，Ｎｏ、１１ 、Ｎｏｖ、１９７５．
ｐｐ、１０２３−１０３０）に報告された従来技術に
よるシ馴フトキーゲートを用いた電界効果トランジスタ
（ＭＢＳＦＥＴ）の基本構造を示す断面図で、１は半絶
縁性ＩｎＰ基板、２はＮチャネルＩｎＰ動作層、３とゲ
ート電極、４はソース電極、５けドレイン電極である。voCED-22, No. 11, Nov. 1975.
This is a cross-sectional view showing the basic structure of a field effect transistor (MBSFET) using a conventional shift gate, which was reported in 1999 (pp. , 3 is a gate electrode, 4 is a source electrode, and 5 is a drain electrode.
一方、第５図はライル（Ｌｉｌｅ）等によってエレクト
ロニクス レター誌（Ｅｌｅｃｔｒｏｎ、 Ｌｅｔｔ、
ｖｏｌ。On the other hand, Figure 5 shows the results of electronics letters (Electron, Lett,
vol.
１４ 、 ｐｐ、６５７−６５９．８ｅｐｔ、１９７８
）に報告されたＳｉｎ、膜をゲート絶縁膜１ｃ用いた
Ｍ Ｉ Ｓ （Ｍｅｔａｌ −Ｉｒｓｕｌａｔｏｒ−８
ｏｍｉｃｏｎｃｂｕ（ｔｏｒ ）型ゲート電界効果トラ
ンジスタ（ＭＩＳＦＥＴ）の晴造断面図で第４図と同一
部分は同一番号をつけである。但し、２′はＮ＋ＩｎＰ
コンタクト層で、７は５ｉ０２膜である。14, pp, 657-659.8ept, 1978
) reported in MIS (Metal-Irsulator-8) using the gate insulating film 1c.
In this Haruzo cross-sectional view of an omicon cbu (tor) type gate field effect transistor (MISFET), the same parts as in FIG. 4 are given the same numbers. However, 2' is N+InP
In the contact layer, 7 is a 5i02 film.
ところで、前記構造のＩｎＰ ｆ用い７ｔＦＥＴでは、
まずＭＥＳＦＥＴの場合、ゲート電極とＮ型ＩｎＰ動作
層の間のシ側ットキー接合のパリアハイトク。By the way, in the 7tFET using InP f with the above structure,
First, in the case of MESFETs, there is a barrier high junction between the gate electrode and the N-type InP active layer.
が０．３〜０．４ｅＶ程度しか力く従って逆方向のリー
ク電流が大きい、ゲート耐圧が小さい等、実用上大き々
問題点があり几。The voltage is only about 0.3 to 0.4 eV, so there are major problems in practical use, such as a large reverse leakage current and a low gate breakdown voltage.
一方、５ｉｏｔ等の絶縁層音用い几ＭＩ ５ＦＥＴでは
前述のリーク電流の問題は力いものの界面準位が犬きく
良好な特性を得るのが困難であり、特にハツトギャップ
（Ｍ＋ｄｇａｐ）から価電子帯に向って界面準位が極め
て大きく、従ってツールミレベルがＭｉｄ ｇａｐから
伝導帯近くの間しか変化し危いために、ディプレッジ・
ンモードの動作を得るのが困難で、大きな電流をとる必
要のある高出力系子ができない々ど多くの問題を有して
いる。On the other hand, in MI 5FETs using insulating layer sound such as 5iot, although the aforementioned leakage current problem is strong, the interface state is too strong and it is difficult to obtain good characteristics, especially from the heart gap (M+dgap) to the valence band. The interfacial state is extremely large towards
There are many problems in that it is difficult to obtain a mode of operation, and it is impossible to create a high-power system that requires a large current.
本発明の目的は、上述の問題点を解消し、高耐圧・高出
力の超高周波ＩｎＰ Ｆ Ｆ、 Ｔ ｆ提供することで
ある。An object of the present invention is to solve the above-mentioned problems and provide a high-voltage, high-output ultra-high frequency InPF, Tf.
本発明によれは半絶＠性基板上にＮ型ＩｎＰ層を設け、
該ＴｎＰ層上にノンドープＧａＡｓ層を設け、該ノンド
ープＧａＡｓ層上に前記ＴｎＩ’ｌｉに形成されるチャ
ネル全制御するゲート電極と前記ＩｎＰｉにオーム性接
触するソース電ジ及びドレイン電極を具備したことを特
徴とする電界効果トランジスタが得られる。According to the present invention, an N-type InP layer is provided on a semi-isolated substrate,
A non-doped GaAs layer is provided on the TnP layer, and a gate electrode for controlling the entire channel formed in the TnI'li and a source electrode and a drain electrode in ohmic contact with the InPi are provided on the non-doped GaAs layer. A field effect transistor with characteristics can be obtained.
以下、本発明と実施例を用いて詳細に説明する。 Hereinafter, the present invention will be explained in detail using examples.
第１図は本発明にこる電界効果トランジスタの構造断面
図である。第４図と同一構成部分には同じ番号を付しで
ある。但し、６はノンドープＧａＡｓ層である。ま之、
この時の熱平衡状態でのゲート１！極下のエネルギー帯
図全第２図に示す。ここで、２１はゲート電極の領域、
２２框ノンド一プＧａＡｓ層、２３はＮチャネルＩｎＰ
動作層、２４は半絶縁性ＩｎＰ基板の領域全島られす。FIG. 1 is a cross-sectional view of the structure of a field effect transistor according to the present invention. Components that are the same as those in FIG. 4 are given the same numbers. However, 6 is a non-doped GaAs layer. Man,
Gate 1 in thermal equilibrium state at this time! The entire energy band diagram at the bottom is shown in Figure 2. Here, 21 is a gate electrode region,
22 non-doped GaAs layer, 23 N-channel InP
The active layer 24 is formed over the entire area of the semi-insulating InP substrate.
第２図に示す様にＧａＡｓとＩｎＰの電子親和度ｒｒｉ
０．３３ｅＶ程度の違いがありＩｎＰの方が太きいため
に、ＧａＡｓとＩｎＰの界面ては０．３３ ｅＶの伝導
帯の不連続がありＩｎＰ中の電子はこのバリアによって
ＧａＡｓ中へ拡散ｔ−ることけ々い。一方ＧａＡｓのゲ
ートメタルに対するバリアハイドは約０．８ｅＶあり、
従ってゲートのリーク電流についてもこの大きなバリア
てよって十分小さくすることができる。す彦わち、上述
のことから明らかな様に本発明にエリＩｎＰに対する実
効的彦シ冒ットキーゲートのバリアハイドを大きくする
ことができ、かつ伝導帯不連続の存在によりゲートをあ
る程度順方向にバイアスしてもゲートヲ流れる電流を十
分小さくすることができる。As shown in Figure 2, the electron affinity of GaAs and InP is
There is a difference of about 0.33 eV, and since InP is thicker, there is a discontinuity in the conduction band of 0.33 eV at the interface between GaAs and InP, and electrons in InP are diffused into GaAs by this barrier. There are so many things. On the other hand, the barrier hydride for GaAs gate metal is about 0.8 eV,
Therefore, the gate leakage current can also be sufficiently reduced by this large barrier. In other words, as is clear from the above, the present invention can increase the barrier hide of the effective Hikoshi gate for InP, and also bias the gate in the forward direction to some extent due to the presence of conduction band discontinuity. Even if the current flows through the gate, the current flowing through the gate can be made sufficiently small.
一方、絶縁物とＩｎＰとの界面に比べてＧａＡｓとＩｎ
Ｐの界面の界面準位密度は極めて小さく、従ってＩｎＰ
の表面ツールミレベルはバンドギャップ中全体を動くこ
とができゲートバイアによりＩｎＰ中のチャネル電荷を
大きく変調することができてディプレッジ譚ン型のＦＥ
Ｔも得らレル。On the other hand, compared to the interface between an insulator and InP, GaAs and In
The interface state density at the interface of P is extremely small, so InP
The surface tool level of the InP can move throughout the bandgap, and the channel charge in InP can be significantly modulated by the gate via, resulting in a depression-type FE.
I also got T.
以上の様にリーク電流の小さい高電流のとれる高出力・
高耐圧１ｎＰ Ｆ Ｂ Ｔが容易に実現できる。As mentioned above, high output and high current with low leakage current.
A high breakdown voltage 1nP FBT can be easily realized.
本実施例の電界効果トランジスタの製造方法の一例を第
１図を用いて説１明する。An example of a method for manufacturing the field effect transistor of this embodiment will be explained with reference to FIG.
まず半絶縁性ＩｎＰ基板１上に例えば気相成長エピタキ
シー法（ｖｐｇ法）てより不純物濃度ＩＸＩＱ１７ｃｙ
−３のＮ形ＩｎＰ ｆ ０．２ Ａ”成長する。次（（
例えば分子線エピタキシー法（ＭＦ３Ｅ法）Ｋｊり／ノ
ンドープａＡ ｓ層を２ｏｏｉ成長してオーミックコン
タクト部のノンドープＧａＡｓ ？エツチング除去する
。最後に通常の方法でゲート電極及びソース・ドレイン
電極を形成して電界効果トランジスタが実現できる。First, an impurity concentration of IXIQ17cy is deposited on a semi-insulating InP substrate 1 by, for example, vapor phase epitaxy (VPG) method.
–3 N-type InP f 0.2 A” is grown.Next ((
For example, by using the molecular beam epitaxy method (MF3E method), two layers of KJ/non-doped AAs are grown and the non-doped GaAs layer is grown in the ohmic contact area. Remove by etching. Finally, a gate electrode and source/drain electrodes are formed using a conventional method to realize a field effect transistor.
第３図は本発明による電界効果トランジスタのゲート・
ソース間Ｏ電流−電圧特性を示したもので、図には従来
技術によるシロットキーゲートの電界効果トランジスタ
における電流−先玉％註も示しである。図に示す様に従
来技術て比べて、本発明による電界効果トランジスタの
ソース・ゲート間電流−躍圧特性は実効的な立上り１￥
Ｌ圧が太きく、シかも逆方向の電流も小さく、耐圧もき
わめて大きく、良好な特性が得られ友。FIG. 3 shows the gate of the field effect transistor according to the present invention.
This figure shows the source-to-source O current-voltage characteristics, and the figure also shows the current-to-lead % note in a conventional Sirotchi gate field effect transistor. As shown in the figure, compared to the conventional technology, the source-gate current-voltage characteristic of the field effect transistor according to the present invention has an effective rise of 1
The L voltage is large, the reverse current is small, the withstand voltage is extremely high, and good characteristics can be obtained.
一方トランジスタ動作も従来のＭＩＳＦＥＴでは実現で
き々かつ次良好なディプレッジ震ン型のＩｎＰ Ｆ Ｅ
Ｔが実現でき、ゲート特性とあわせて従来技術では困
難であった高出力・高耐圧のＦＥＴが得られ友。On the other hand, the transistor operation is impossible to achieve with conventional MISFETs, and the second best transistor operation is the depression-type InP FET.
This makes it possible to realize FETs with high output and high voltage resistance, which were difficult to achieve with conventional technology, along with good gate characteristics.
以上の説明から明らか々様に、本発明によれば高耐圧・
高出力の超高周波ＩｎＰ Ｆ Ｅ Ｔが実現でき、今後
の通信・情報技術に寄与するところが極めて大である。As is clear from the above explanation, according to the present invention, high voltage resistance and
High-power ultra-high frequency InP FET can be realized, which will greatly contribute to future communication and information technology.
第１図は本発明による電界効果トランジスタの構造断面
図、第２図はゲート電極下のエネルギー帯図、第３図は
ソース・ゲート間の電流−電圧特性、第４図第５図は各
々は従来技術による電界効果トランジスタの構造断面図
である。
図において、
１・・・半絶縁性ＩｎＰ基板
２・・・ＮチャネルＩｎＰ動作層
２′・・・Ｎ”ＩｎＰコンタクト層
３・・・ゲート電極
４・−・ソース電極
５・・・ドレイン電極
６・・・アンドープＧａＡｓ層
７・・・Ｓｉｎ、膜
である。
門人弁理上 内 原 替
第１図
第２図
第３図Fig. 1 is a cross-sectional view of the structure of a field effect transistor according to the present invention, Fig. 2 is an energy band diagram under the gate electrode, Fig. 3 is the current-voltage characteristic between the source and gate, and Fig. 4 and Fig. 5 are the respective diagrams. 1 is a structural cross-sectional view of a field effect transistor according to the prior art; FIG. In the figure, 1... Semi-insulating InP substrate 2... N channel InP active layer 2'... N'' InP contact layer 3... Gate electrode 4... Source electrode 5... Drain electrode 6 ...Undoped GaAs layer 7...Sin, film. Figure 1, Figure 2, Figure 3.
Claims (1)
にノンドープＧａＡｓ層を設け、該ノンドープＧａＡｓ
層上に前記ＩｎＰ層に形成されるチャネルを制御するゲ
ート電極と前記ＩｎＰ層にオーム性接触するソース電極
及びドレイン電極を具備したことを特徴とする電界効果
トランジスタ。An N-type InP layer is provided on a semi-insulating substrate, a non-doped GaAs layer is provided on the InP layer, and the non-doped GaAs
A field effect transistor comprising a gate electrode for controlling a channel formed in the InP layer, and a source electrode and a drain electrode in ohmic contact with the InP layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11217186A JPS62268165A (en) | 1986-05-15 | 1986-05-15 | Field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11217186A JPS62268165A (en) | 1986-05-15 | 1986-05-15 | Field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62268165A true JPS62268165A (en) | 1987-11-20 |
Family
ID=14580022
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11217186A Pending JPS62268165A (en) | 1986-05-15 | 1986-05-15 | Field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62268165A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01161874A (en) * | 1987-12-18 | 1989-06-26 | Hitachi Ltd | Semiconductor device and its manufacture |
| US5180681A (en) * | 1990-03-15 | 1993-01-19 | North Carolina State University | Method of making high current, high voltage breakdown field effect transistor |
| WO2001097274A3 (en) * | 2000-06-12 | 2002-04-11 | Motorola Inc | Heterostructure field effect transistor and method of manufacturing it |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5882570A (en) * | 1981-11-11 | 1983-05-18 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device |
| JPS62171164A (en) * | 1986-01-23 | 1987-07-28 | Sumitomo Electric Ind Ltd | Field-effect transistor |
-
1986
- 1986-05-15 JP JP11217186A patent/JPS62268165A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5882570A (en) * | 1981-11-11 | 1983-05-18 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device |
| JPS62171164A (en) * | 1986-01-23 | 1987-07-28 | Sumitomo Electric Ind Ltd | Field-effect transistor |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01161874A (en) * | 1987-12-18 | 1989-06-26 | Hitachi Ltd | Semiconductor device and its manufacture |
| US5180681A (en) * | 1990-03-15 | 1993-01-19 | North Carolina State University | Method of making high current, high voltage breakdown field effect transistor |
| WO2001097274A3 (en) * | 2000-06-12 | 2002-04-11 | Motorola Inc | Heterostructure field effect transistor and method of manufacturing it |
| US6821829B1 (en) | 2000-06-12 | 2004-11-23 | Freescale Semiconductor, Inc. | Method of manufacturing a semiconductor component and semiconductor component thereof |
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