JPS62266856A - Manufacture of hybrid ic - Google Patents
Manufacture of hybrid icInfo
- Publication number
- JPS62266856A JPS62266856A JP10969286A JP10969286A JPS62266856A JP S62266856 A JPS62266856 A JP S62266856A JP 10969286 A JP10969286 A JP 10969286A JP 10969286 A JP10969286 A JP 10969286A JP S62266856 A JPS62266856 A JP S62266856A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- lead frame
- lead
- soldering
- notch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 12
- 238000005476 soldering Methods 0.000 abstract description 11
- 238000007598 dipping method Methods 0.000 abstract description 7
- 239000004020 conductor Substances 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 description 7
- 210000000078 claw Anatomy 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011295 pitch Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3405—Edge mounted components, e.g. terminals
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明はハイブリッドＩＣ（以下、ＨＩＣという）の製
造方法、特に、そのハイブリッドＩＣのリードフレーム
の取り付けに関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a hybrid IC (hereinafter referred to as HIC), and particularly to mounting a lead frame of the hybrid IC.
（従来の技術）
従来、基板の端子パッド部にはリード片が接着されて、
入出力端子が形成されるようになっている。(Prior art) Conventionally, lead pieces were glued to the terminal pads of the board.
Input/output terminals are formed.
第３図はＳ ［Ｐ （Ｓｉｎｇｌｅ Ｉｎ−Ｌｉｎｅ
Ｐａｃｋａｇｅ）形ＨＩ Ｃの断面図であり、このを用
いて従来のＳＩＰ形ＨＩＣについて説明すると、ＨＩＣ
Ｉには基板１１の上面にパターン１２が印刷され、ＩＣ
、コンデンサ等の電子部品１３が半田付けによって搭載
され、裏面には厚膜パターン１４が印刷された両面構造
となっている。また、リードフレーム１５の接続部には
又状の爪１６ａ、１６ｂが形成され、それによって、基
板１１が挟持される状態で、半田ディツプ（半田浸漬）
法により半田付けされる。Figure 3 shows S [P (Single In-Line
This is a cross-sectional view of a conventional SIP type HIC using this cross-sectional view.
A pattern 12 is printed on the top surface of the substrate 11, and the IC
, a double-sided structure with electronic components 13 such as capacitors mounted by soldering and a thick film pattern 14 printed on the back side. Further, claw-like claws 16a and 16b are formed at the connection portion of the lead frame 15, and the solder dip (solder immersion) is performed while the board 11 is being sandwiched.
soldered according to the law.
第４図はそのＳＩＰ形ＨＩＣの実装断面図であり、ＨＩ
ＣＩを印刷配線基板２のスルーホールに挿入した後、こ
れをケース３に収納してモジュールとして完成する。Ｈ
ＩＣＩの小形、高密度化を図ると、リードフレーム１５
の裏面パッド部の無駄スペースや裏面爪１６ｂによるＨ
Ｉ Ｃ１の増大が問題となり、また、回路が高周波化
されるにつれて、パターンのクロストーク等の特性上の
問題から裏面爪１６ｂが裏面パターン１４に悪影響を及
ぼす可能性が生じるので、基板を上下から挟持するこれ
までのリードフレ−ムではなく、第５図に示されるよう
に、基板２１上に設けられるパターン２２に端子を表面
だけで実装する片面リードフレーム２３が用いられるこ
とが多くなってきている。Figure 4 is a cross-sectional view of the SIP type HIC.
After inserting the CI into the through hole of the printed wiring board 2, it is housed in the case 3 to complete the module. H
In order to make ICI smaller and more dense, the lead frame 15
H due to wasted space on the back pad part and the back claw 16b.
The increase in I C1 becomes a problem, and as the frequency of circuits becomes higher, there is a possibility that the back claw 16b has a negative effect on the back pattern 14 due to characteristic problems such as pattern crosstalk. Instead of the conventional lead frame that clamps the lead frame, a single-sided lead frame 23, in which terminals are mounted only on the surface of a pattern 22 provided on a substrate 21, is increasingly being used, as shown in FIG. .
（発明が解決しようとする問題点）
しかしながら、従来の第３図に示されるものに半田デイ
ツプ法を用いると端子が落下してしまい、また、第５図
に示されるものに半田リフローを用いると端子が転倒し
てしまうため、半田ゴテによる手付けを行う必要があり
、工数がかかり、かつ、品質の安定したものが供給でき
ないという問題があった・
本発明は、上記問題点を除去し、半田デイツプ法による
半田付けが可能な片面リードフレームを有するＨＩＧの
製造方法を提供することを目的とする。(Problems to be Solved by the Invention) However, if the conventional solder dip method is used for the device shown in FIG. 3, the terminals will fall off, and if solder reflow is used for the device shown in FIG. Since the terminals fall over, it is necessary to manually attach them with a soldering iron, which takes a lot of man-hours and makes it impossible to supply products of stable quality.The present invention eliminates the above problems and An object of the present invention is to provide a method for manufacturing a HIG having a single-sided lead frame that can be soldered by the dip method.
（問題点を解決するための手段）
本発明は、ＨＩＣの端子を取り付けるに際し、端子の表
面側と裏面側の境界部にノツチ部（ハーフカット部）が
形成される特殊端子をディッピングにて半田付けを行い
、その後に裏面側を上記ノツチ部より取り除き、片面リ
ードフレームとするようにしたものである。(Means for Solving the Problems) When attaching an HIC terminal, the present invention uses a special terminal in which a notch (half-cut part) is formed at the boundary between the front side and the back side of the terminal, and solders it by dipping. After that, the back side is removed from the notch part to form a single-sided lead frame.
（作用）
本発明によれば、ＨＩＣの端子を取り付けるに際し、端
子の表面側と裏面側の境界部にノツチ部（ハーフカット
部）が形成される特殊端子をディッピングにて半田付け
を行い、その後に裏面側を上記ノツチ部より取り除き、
片面リードフレームとするようにしたので、片面リード
フレームでありながら、半田デイツプ法による半田付け
を行うことができ、工数の低減及び信頼性の向上を図る
ことができる。(Function) According to the present invention, when attaching a HIC terminal, a special terminal having a notch (half-cut portion) formed at the boundary between the front side and the back side of the terminal is soldered by dipping, and then Remove the back side from the above notch,
Since the single-sided lead frame is used, soldering can be performed using the solder dip method even though the lead frame is single-sided, thereby reducing the number of man-hours and improving reliability.
（実施例）
以下、本発明の実施例について図面を参照しながら詳細
に説明する。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図は本発明の実施例を示すＨＩＣの製造方法を示す
工程断面図、第２図はそのリードフレームを示す斜視図
である。FIG. 1 is a process sectional view showing a method of manufacturing an HIC according to an embodiment of the present invention, and FIG. 2 is a perspective view showing a lead frame thereof.
第２図に示されるように、当該リードフレーム４０は、
端子部（リード部） ４１と連結部４２の境界部にノツ
チ部４３を存し、その連結部より一定ピッチ（現状では
２．５４ピツチ）で端子部４１を連結している。As shown in FIG. 2, the lead frame 40 is
A notch portion 43 is provided at the boundary between the terminal portion (lead portion) 41 and the connecting portion 42, and the terminal portions 41 are connected at a constant pitch (currently 2.54 pitches) from the connecting portion.
そこで、本発明のＨＩＣの製造方法を第１図に基づいて
詳細に説明する。Therefore, the method for manufacturing an HIC according to the present invention will be explained in detail with reference to FIG.
まず、第１図（ａ）に示されるように、片面に導体で形
成された端子パッド３２を有する基板３１を用意し、そ
の端子パッド３２に予め用意された第２図に示されるリ
ードフレーム４０を対応させる。First, as shown in FIG. 1(a), a substrate 31 having a terminal pad 32 formed of a conductor on one side is prepared, and a lead frame 40 shown in FIG. 2 prepared in advance on the terminal pad 32 is prepared. correspond.
次に、第１図（ｂ）に示されるように、基板３１の端子
パッド３２にリードフレーム４０を取り付け、ディッピ
ングにより半田付け４４を行う。Next, as shown in FIG. 1(b), a lead frame 40 is attached to the terminal pad 32 of the substrate 31, and soldering 44 is performed by dipping.
次に、第１図（ｃ）に示されるように、この半田付けの
後に連結部４２をあげる（Ｆ方向に曲げる）ことにより
、ノツチ部４３より連結部４２のみが容易に取り除かれ
、端子部４１が実装される。Next, as shown in FIG. 1(c), by raising the connecting part 42 after this soldering (bending it in the F direction), only the connecting part 42 can be easily removed from the notch part 43, and the terminal part 41 will be implemented.
このように、ＨＴ Ｃ５板の端子パッドと接続し、入出
力端子となるリードフレームを片側端に連結部を有し、
中央部には基板を挟持するように、コ字状部となし、こ
のコ字状部の角部又はその近傍にノツチ部を設け、この
ノツチ部によって、角部から連結部を容易に取り除くこ
とができる。In this way, the lead frame that connects to the terminal pad of the HT C5 board and becomes the input/output terminal has a connecting part at one end.
A U-shaped portion is formed in the center so as to sandwich the substrate, and a notch portion is provided at or near the corner of this U-shaped portion, and the connecting portion can be easily removed from the corner by the notch portion. Can be done.
この場合、連結部には複数の端子部４１が連設されてい
るため、連結部を曲げることにより、一度に複数のリー
ド部を形成することができて有利である。In this case, since a plurality of terminal portions 41 are connected to the connecting portion, it is advantageous that a plurality of lead portions can be formed at once by bending the connecting portion.
なお、本発明は上記実施例に限定されるものではな（、
本発明の趣旨に基づいて種々の変形が可能であり、これ
らを本発明の範囲から排除するものではない。Note that the present invention is not limited to the above embodiments (
Various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.
（発明の効果）
以上、詳細に説明したように、本発明によれば、基板に
リード片を接着してＨＩＣを製造する方法において、リ
ード部とリード支持部との間が応力により取り除けるリ
ードフレームを用意する工程と、上記リードフレームの
リード部と上記基板を接着する工程と、上記リード部か
らリード支持部を取り除く工程とを施すようにしたので
、ディッピングによる半田付けが可能となり、工数低減
及び偉績性の向上に寄与することができる。(Effects of the Invention) As described in detail above, according to the present invention, in the method of manufacturing an HIC by bonding lead pieces to a substrate, the lead frame can be removed by stress between the lead part and the lead support part. The process of preparing the lead frame, the process of bonding the lead part of the lead frame and the board, and the process of removing the lead support part from the lead part makes it possible to solder by dipping, reducing the number of man-hours and It can contribute to improving greatness.
第１図は本発明の実施例を示すＨ［Ｃの製造工程断面図
、第２図は本発明のリードフレームの斜視図、第３図は
従来のＳＩＰ形ＨＩＣの断面図、第４図は第３図に示さ
れるＨＩＣの実装断面図、第５図は従来の他の例を示す
Ｈ［Ｃの部分斜視図である。
３１・・・基板、３２・・・端子バッド、４０・・・リ
ードフレーム、４１・・・端子部（リード部）、４２・
・・連結部、４３・・・ノツチ部、４４・・・半田付け
。
特許出願人 沖電気工業株式会社
代 理 人 弁理士 清 水 守３２ 篇壬ハ
゛ソＦ
ン
（Ｃ） 第２図
末茫明のＨＩＣ虐鏝工名ｊπ面応
第１図Fig. 1 is a sectional view of the manufacturing process of H[C showing an embodiment of the present invention, Fig. 2 is a perspective view of the lead frame of the present invention, Fig. 3 is a sectional view of a conventional SIP type HIC, and Fig. 4 is FIG. 3 is a mounting sectional view of the HIC shown in FIG. 3, and FIG. 5 is a partial perspective view of H[C showing another conventional example. 31... Board, 32... Terminal pad, 40... Lead frame, 41... Terminal part (lead part), 42...
... Connecting part, 43... Notch part, 44... Soldering. Patent Applicant Oki Electric Industry Co., Ltd. Agent Patent Attorney Mamoru Shimizu 32 Edited by HIC Press Fn (C) Figure 1
Claims (1)
方法において、 （ａ）リード部とリード支持部との間が応力により取り
除けるリードフレームを用意する工程と、 （ｂ）上記リードフレームのリード部を上記基板の端子
パッド部に接着する工程と、 （ｃ）上記リード部からリード支持部を取り除く工程と
を有するハイブリッドＩＣの製造方法。[Claims] A method for manufacturing a hybrid IC by bonding a lead piece to a substrate, comprising: (a) preparing a lead frame in which the gap between the lead part and the lead support part can be removed due to stress; and (b) the above-mentioned steps. A method for manufacturing a hybrid IC, comprising: bonding a lead portion of a lead frame to a terminal pad portion of the substrate; and (c) removing a lead support portion from the lead portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61109692A JPH065702B2 (en) | 1986-05-15 | 1986-05-15 | How to attach the external lead-out terminal of the hybrid IC |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61109692A JPH065702B2 (en) | 1986-05-15 | 1986-05-15 | How to attach the external lead-out terminal of the hybrid IC |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62266856A true JPS62266856A (en) | 1987-11-19 |
| JPH065702B2 JPH065702B2 (en) | 1994-01-19 |
Family
ID=14516775
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61109692A Expired - Lifetime JPH065702B2 (en) | 1986-05-15 | 1986-05-15 | How to attach the external lead-out terminal of the hybrid IC |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH065702B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4985747A (en) * | 1988-06-09 | 1991-01-15 | Oki Electric Industry Co., Ltd. | Terminal structure and process of fabricating the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4865874A (en) * | 1971-12-11 | 1973-09-10 | ||
| JPS5572068A (en) * | 1978-11-27 | 1980-05-30 | Fujitsu Ltd | Lead parts and package of the same |
-
1986
- 1986-05-15 JP JP61109692A patent/JPH065702B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4865874A (en) * | 1971-12-11 | 1973-09-10 | ||
| JPS5572068A (en) * | 1978-11-27 | 1980-05-30 | Fujitsu Ltd | Lead parts and package of the same |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4985747A (en) * | 1988-06-09 | 1991-01-15 | Oki Electric Industry Co., Ltd. | Terminal structure and process of fabricating the same |
| US4989318A (en) * | 1988-06-09 | 1991-02-05 | Oki Electric Industry Co., Ltd. | Process of assembling terminal structure |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH065702B2 (en) | 1994-01-19 |
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