JPS6226606B2 - - Google Patents
Info
- Publication number
- JPS6226606B2 JPS6226606B2 JP55022967A JP2296780A JPS6226606B2 JP S6226606 B2 JPS6226606 B2 JP S6226606B2 JP 55022967 A JP55022967 A JP 55022967A JP 2296780 A JP2296780 A JP 2296780A JP S6226606 B2 JPS6226606 B2 JP S6226606B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- capacitive element
- terminal
- current
- pass filter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000010521 absorption reaction Methods 0.000 claims description 14
- 230000005669 field effect Effects 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/04—Frequency selective two-port networks
Landscapes
- Networks Using Active Elements (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
【発明の詳細な説明】
本発明は、１次伝達関数を有する１次低域通過
フイルタに関し、特に位相同期ループに適用して
好適なものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a first-order low-pass filter having a first-order transfer function, and is particularly suitable for application to a phase-locked loop.
斯種１次低域通過フイルタとして従来、第１図
に示す如き、１次伝達関数を有する１次低域通過
フイルタ回路１と、その入力端子２に接続され、
第１の入力端子Ｔ１よりの第１の入力信号Ｓ１に
より制御されることによりフイルタ回路１にその
入力端子２側より第１の電流I1を供給する電流供
給回路Ｈ１と、フイルタ回路１の入力端子２に接
続され、第２の入力端子Ｔ２よりの第１の入力信
号Ｓ１に対して逆極性の第２の入力信号Ｓ２によ
り制御されることによりフイルタ回路１よりその
入力端子２側から第２の電流I2を吸収する電流吸
収回路Ｈ２とを有し、而してフイルタ回路１の出
力端子３を出力端子TOとしてこれより出力信号
SOを導出する様になされ、この場合フイルタ回
路１が増巾度Ａを有する負帰還増巾器４と、一端
が負帰還増巾器４の入力端に他端が入力端子２に
接続せる抵抗５と、負帰還増巾器４の出力端及び
入力端間に接続せる抵抗６及び容量素子７の直列
回路とを以つて構成され、電流供給回路Ｈ１が、
ドレイン（又はソース）を正の電源端子８に、ソ
ース（又はドレイン）をフイルタ回路１の入力端
子２に、ゲートを入力端子Ｔ１に接続せるＰチヤ
ンネル電界効果トランジスタ９を以つて構成さ
れ、電流吸収回路Ｈ２が、ドレイン（又はソー
ス）をフイルタ回路１の入力端子２に、ソース
（又はドレイン）を接地に、ゲートを入力端子Ｔ
２に接続せるＮチヤンネル電界効果トランジスタ
１０を以つて構成されてなる構成のものが提案さ
れている。 Conventionally, this type of first-order low-pass filter is connected to a first-order low-pass filter circuit 1 having a first-order transfer function and its input terminal 2, as shown in FIG.
A current supply circuit H1 supplies a first current I1 to the filter circuit 1 from its input terminal 2 side by being controlled by a first input signal S1 from the first input terminal T1; The second input signal S1 from the input terminal 2 side of the filter circuit 1 is connected to the terminal 2 and controlled by the second input signal S2 having the opposite polarity to the first input signal S1 from the second input terminal T2. The output terminal 3 of the filter circuit 1 is used as the output terminal TO to output a signal from this.
In this case, the filter circuit 1 is connected to a negative feedback amplifier 4 having an amplification degree A, and a resistor whose one end is connected to the input terminal of the negative feedback amplifier 4 and the other end is connected to the input terminal 2. 5, and a series circuit of a resistor 6 and a capacitive element 7 connected between the output terminal and the input terminal of the negative feedback amplifier 4, and the current supply circuit H1 is
It consists of a P-channel field effect transistor 9 whose drain (or source) is connected to the positive power supply terminal 8, whose source (or drain) is connected to the input terminal 2 of the filter circuit 1, and whose gate is connected to the input terminal T1, and which absorbs current. A circuit H2 has a drain (or source) connected to the input terminal 2 of the filter circuit 1, a source (or drain) connected to the ground, and a gate connected to the input terminal T.
A configuration has been proposed which includes an N-channel field effect transistor 10 connected to a transistor 2.
所で斯る従来の１次低域通過フイルタの構成の
場合、これを位相比較回路より負極性のパルス波
でなる第１の比較出力電圧及び正極性のパルス波
でなる第２の比較出力電圧が時間を異にして得ら
れる様になされた位相同期ループに適用するもの
とすれば、第１の入力端子Ｔ１に第１の比較出力
電圧が入力信号Ｓ１として与えられることにより
電流供給回路Ｈ１のトランジスタ９がオンし、こ
れによりその電流供給回路Ｈ１よりフイルタ回路
１に電流I1を供給し、又第２の入力端子Ｔ２に第
２の比較出力電圧が入力信号Ｓ２として与えられ
ることにより電流吸収回路Ｈ２のトランジスタ１
０がオンし、これによりその電流吸収回路Ｈ２に
てフイルタ回路１より電流I2を吸収するという作
用をなすことで、出力端子TOより出力信号SOが
１次低域通過フイルタとしての出力信号として得
られるものであるが、この場合、フイルタ回路１
の抵抗５及び６の抵抗を夫々R1及びR2、容量素
子７の容量をＣとするとき、フイルタ回路１の伝
達関数Ｔ(s)（但しｓは複素変数）が、周知の如
く
Ｔ(s)＝１＋Ｒ２Ｃｓ／Ｒ１Ｃｓ＝１＋τ２ｓ／τ
１ｓ……(1)
で表わされる１次伝達関数を有するので、入力信
号Ｓ１及びＳ２を振幅の絶対値が互いに等しいも
のとし、又電流供給回路Ｈ１及び電流吸収回路Ｈ
２を、それ等のトランジスタ９及び１０の相互コ
ンダクタンスをして互いに等しいものとすること
により、互いに等しい相互コンダクタンスを有す
るものとし置けば、第１図に示す１次低域通過フ
イルタが上述せる(1)式で表わされる伝達関数を有
するものである。 In the case of such a conventional first-order low-pass filter configuration, the phase comparison circuit outputs a first comparison output voltage consisting of a pulse wave of negative polarity and a second comparison output voltage consisting of a pulse wave of positive polarity. If applied to a phase-locked loop in which the voltages are obtained at different times, the first comparison output voltage is applied to the first input terminal T1 as the input signal S1, so that the voltage of the current supply circuit H1 is The transistor 9 turns on, and the current supply circuit H1 supplies the current I1 to the filter circuit 1, and the second comparison output voltage is applied to the second input terminal T2 as the input signal S2, thereby absorbing the current. Transistor 1 of circuit H2
0 is turned on, and as a result, the current absorption circuit H2 absorbs the current I2 from the filter circuit 1, and the output signal SO from the output terminal TO is output as the output signal of the first-order low-pass filter. In this case, the filter circuit 1
When the resistances of the resistors 5 and 6 are R 1 and R 2 respectively, and the capacitance of the capacitive element 7 is C, the transfer function T (s) (where s is a complex variable) of the filter circuit 1 is expressed as T ( s) =1+ R2Cs / R1Cs =1+ τ2s /τ
1 s...(1) Therefore, the input signals S1 and S2 are assumed to have the same absolute value of amplitude, and the current supply circuit H1 and the current absorption circuit H
By setting the mutual conductances of the transistors 9 and 10 to be equal to each other, the first-order low-pass filter shown in FIG. 1) It has a transfer function expressed by the following equation.
従つて第１図に示す１次低域通過フイルタによ
れば、それを位相同期ループの低域フイルタとし
て用いた場合に於て、その位相同期ループの機能
がより安定に得られるべく、この場合の第１図に
示す１次低域通過フイルタでなる低域フイルタに
より、位相同期ループの位相比較回路に供給され
ている基準周波数信号の周波数を有する成分に対
する大なる損失効果を与えんとすれば、詳細説明
はこれを省略するも、τ１＝R1Cの値を大とする
を要し、この為フイルタ回路１に於ける容量素子
７及び抵抗５を、フイルタ回路１に於ける増巾器
４、電流供給回路Ｈ１及び電流吸収回路Ｈ２と共
に半導体集積回路化して第１図に示す１次低域通
過フイルタを半導体集積回路化せんとしてもそれ
に困難を伴うか、半導体集積回路化するとした場
合容量素子７及び抵抗５の半導体集積回路に占め
る面積が大となる等の欠点を有していた。 Therefore, according to the first-order low-pass filter shown in FIG. 1, when it is used as a low-pass filter of a phase-locked loop, the function of the phase-locked loop can be obtained more stably. If we want to give a large loss effect to the component having the frequency of the reference frequency signal supplied to the phase comparator circuit of the phase-locked loop by the low-pass filter consisting of the first-order low-pass filter shown in Fig. 1, Although the detailed explanation is omitted, it is necessary to increase the value of τ 1 =R 1 C, and for this reason, the capacitive element 7 and the resistor 5 in the filter circuit 1 are increased in width. 4, the current supply circuit H1, and the current absorption circuit H2 into a semiconductor integrated circuit, and the primary low-pass filter shown in FIG. 1 is not integrated into a semiconductor integrated circuit. The capacitive element 7 and the resistor 5 have drawbacks such as a large area occupied in the semiconductor integrated circuit.
依つて本発明は上述せる欠点を伴うことのない
新規な１次低域通過フイルタを提案せんとするも
ので、以下詳述する所より明らかとなるであろ
う。 The present invention therefore proposes a novel first-order low-pass filter that does not suffer from the above-mentioned drawbacks, as will become clear from the detailed description below.
第２図は本発明による１次低域通過フイルタの
一例を示し、第１図との対応部分には同一符号を
附して示すも、容量素子２１と、その第１の端子
ａ１に接続され、第１の入力端子Ｔ１よりの第１
の入力信号Ｓ１により制御されることにより容量
素子２１にその端子ａ１側から第１の電流I1を供
給する電流供給回路Ｈ１と、容量素子２１の端子
ａ１に接続され、第２の入力端子Ｔ２よりの第１
の入力信号Ｓ１に対して逆極性の第２の入力信号
Ｓ２により制御されることにより容量素子２１よ
りその端子ａ１側より第２の電流I2を吸収する電
流吸収回路Ｈ２と、容量素子２１の第２の端子ａ
２に接続され、入力信号Ｓ１及びＳ２に基き互い
に逆極性を呈する第１の電圧V1及び第２の電圧
V2を発生し、それ等電圧V1及びV2を容量素子２
１の端子ａ２に与える様になされた電圧発生回路
Ｇとを有し、而して容量素子２１の端子ａ１より
出力端子TOが導出され、これより出力信号SOを
導出する様になされている。 FIG. 2 shows an example of a primary low-pass filter according to the present invention, in which parts corresponding to those in FIG. , the first from the first input terminal T1
A current supply circuit H1 supplies a first current I1 to the capacitive element 21 from its terminal a1 side by being controlled by an input signal S1 of the capacitive element 21, and a second input terminal T2 connected to the terminal a1 of the capacitive element 21. First of all
A current absorption circuit H2 absorbs the second current I 2 from the terminal a1 side of the capacitive element 21 by being controlled by a second input signal S2 of opposite polarity to the input signal S1 of the capacitive element 21; second terminal a
a first voltage V 1 and a second voltage connected to V 2 and exhibiting mutually opposite polarities based on the input signals S 1 and S 2;
V 2 is generated, and the voltages V 1 and V 2 are applied to capacitive element 2.
1, and an output terminal TO is derived from the terminal a1 of the capacitive element 21, from which an output signal SO is derived.
この場合電流供給回路Ｈ１は、図示の如く、ド
レイン（又はソース）をカレントミラー回路２２
を通じて正の電源端子２３に、ソース（又はドレ
イン）を容量素子２１の端子ａ１に、ゲートが入
力端子Ｔ１に接続せるスイツチング用Ｐチヤンネ
ル電界効果トランジスタ２４を以つて構成し得、
この場合カレントミラー回路２２は、ドレイン
（又はソース）を電源端子２３に、ソース（又は
ドレイン）をトランジスタ２４のドレイン（又は
ソース）に、ゲートをバイアス電流源（図示せ
ず）に接続せるＰチヤンネル電界効果トランジス
タ２５と、ドレイン（又はソース）を電源端子２
３に、ソース（又はドレイン）及びベースをバイ
アス電流源（図示せず）に接続せるＰチヤンネル
電界効果トランジスタ２６とを以つて構成し得る
ものである。 In this case, the current supply circuit H1 connects the drain (or source) to the current mirror circuit 22 as shown in the figure.
A P-channel field effect transistor 24 for switching, whose source (or drain) is connected to the terminal a1 of the capacitive element 21, and whose gate is connected to the input terminal T1,
In this case, the current mirror circuit 22 is a P channel whose drain (or source) is connected to the power supply terminal 23, whose source (or drain) is connected to the drain (or source) of the transistor 24, and whose gate is connected to a bias current source (not shown). The field effect transistor 25 and the drain (or source) are connected to the power supply terminal 2.
3, a P-channel field effect transistor 26 whose source (or drain) and base are connected to a bias current source (not shown).
又電流吸収回路Ｈ２は、同様に図示の如く、ド
レイン（又はソース）を容量素子２１の端子ａ１
に、ソース（又はドレイン）をカレントミラー回
路２７を通じて接地に、ゲートを入力端子Ｔ２に
接続せるスイツチング用Ｎチヤンネル電界効果ト
ランジスタ２８を以つて構成し得、この場合カレ
ントミラー回路２７はドレイン（又はソース）を
トランジスタ２８のソース（又はドレイン）に、
ソース（又はドレイン）を接地に、ゲートをバイ
アス電流源（図示せず）に接続せるＮチヤンネル
電界効果トランジスタ２９と、ドレイン（又はソ
ース）及びゲートをバイアス電流源に、ソース
（又はドレイン）を接地に接続せるＮチヤンネル
電界効果トランジスタ３０とを以つて構成し得
る。 Similarly, the current absorption circuit H2 has its drain (or source) connected to the terminal a1 of the capacitive element 21, as shown in the figure.
In addition, the current mirror circuit 27 can be configured with a switching N-channel field effect transistor 28 whose source (or drain) is connected to ground through a current mirror circuit 27 and whose gate is connected to the input terminal T2. ) to the source (or drain) of the transistor 28,
An N-channel field effect transistor 29 whose source (or drain) is connected to ground, whose gate is connected to a bias current source (not shown), whose drain (or source) and gate are connected to a bias current source, and whose source (or drain) is connected to ground. The N-channel field effect transistor 30 may be connected to the N-channel field effect transistor 30.
更に電圧発生回路Ｇは、入力側が入力端子Ｔ１
及びＴ２に夫々接続され、これ等よりの入力信号
Ｓ１及びＳ２のレベルを夫々シフトするレベルシ
フト回路３１及び３２と、ドレイン（又はソー
ス）が正の電源端子３３に、ゲートがレベルシフ
ト回路３１の出力側に接続されてなるスイツチン
グ用Ｐチヤンネル電界効果トランジスタ３４と、
ドレイン（又はソース）がトランジスタ３４のソ
ース（又はドレイン）に、ソース（又はドレイ
ン）が負の電源端子３５に、ゲートがレベルシフ
ト回路３２の出力側に接続せるスイツチング用Ｎ
チヤンネル電界効果トランジスタ３６とを有し、
トランジスタ３４のソース（又はドレイン）及び
トランジスタ３６のドレイン（又はソース）が抵
抗３７及び３８の直列回路を通じて接地に接続さ
れ、而して抵抗３７及び３８の接続中点が容量素
子２１の端子ａ２に接続されてなる構成とし得
る。 Further, the voltage generation circuit G has an input terminal T1 on the input side.
and T2, and shift the levels of the input signals S1 and S2 from these circuits, respectively; the drain (or source) is connected to the positive power supply terminal 33, and the gate is connected to the level shift circuit 31. a switching P-channel field effect transistor 34 connected to the output side;
A switching N whose drain (or source) is connected to the source (or drain) of the transistor 34, whose source (or drain) is connected to the negative power supply terminal 35, and whose gate is connected to the output side of the level shift circuit 32.
a channel field effect transistor 36;
The source (or drain) of the transistor 34 and the drain (or source) of the transistor 36 are connected to ground through a series circuit of resistors 37 and 38, and the midpoint of the connection between the resistors 37 and 38 is connected to the terminal a2 of the capacitive element 21. The configuration may be such that they are connected.
以上で本発明による１次低域通過フイルタの一
例構成が明らかとなつたが、斯る構成を有する本
発明による１次低域通過フイルタは、これを第１
図にて前述せると同様に、位相比較回路より負極
性のパルス波でなる第１の比較出力電圧及び正極
性のパルス波でなる第２の比較出力電圧が時間を
異にして得られる様になされた位相同期ループに
適用するものとすれば、第１の入力端子Ｔ１に第
１の比較出力電圧が第３図Ａに示されている入力
信号Ｓ１として与えられることにより、電流供給
回路Ｈ１のトランジスタ２４がオンし、これによ
りその電流供給回路Ｈ１より容量素子２１にその
端子ａ１側から電流I1を供給し、又第２の入力端
子Ｔ２に第２の比較電圧が第３図Ｂに示されてい
る入力信号Ｓ２として与えられることにより、電
流吸収回路Ｈ２のトランジスタ２８がオンし、こ
れによりその電流吸収回路Ｈ２にて容量素子２１
よりその端子ａ１側から電流I2を吸収し、又入力
信号Ｓ１に基き電圧発生回路Ｇのトランジスタ３
４がオンし、これにより容量素子２１の端子ａ２
に第３図Ｃに示す如き正極性のパルス波でなる電
圧V1を与え、入力信号Ｓ２に基き電圧発生回路
Ｇのトランジスタ３６がオンし、これにより容量
素子２１の端子ａ２に第３図に示す如き負極性の
パルス波でなる電圧V2を与えるという作用をな
すことで、出力端子TOより第３図Ｄに示す如き
電圧V1の得られる区間に於て時間と共にレベル
が上昇し、電圧V2の得られる区間に於て時間と
共にレベルが降下するという正極性出力信号SO
が、１次低域通過フイルタとしての出力信号とし
て得られるものである。 The configuration of an example of the first-order low-pass filter according to the present invention has been clarified above, and the first-order low-pass filter according to the present invention having such a configuration is
As described above in the figure, the first comparison output voltage consisting of a negative polarity pulse wave and the second comparison output voltage consisting of a positive polarity pulse wave are obtained from the phase comparison circuit at different times. If applied to the phase-locked loop constructed in this way, the first comparison output voltage is applied to the first input terminal T1 as the input signal S1 shown in FIG. 3A, so that the current supply circuit H1 is The transistor 24 is turned on, so that the current supply circuit H1 supplies the current I1 to the capacitive element 21 from its terminal a1 side, and the second comparison voltage is applied to the second input terminal T2 as shown in FIG. 3B. The transistor 28 of the current absorption circuit H2 is turned on by being given as the input signal S2, which causes the capacitive element 21 to be turned on in the current absorption circuit H2.
The current I2 is absorbed from the terminal a1 side, and the transistor 3 of the voltage generating circuit G is absorbed based on the input signal S1.
4 is turned on, and as a result, the terminal a2 of the capacitive element 21
A voltage V 1 consisting of a pulse wave of positive polarity as shown in FIG. By applying the voltage V 2 consisting of a negative polarity pulse wave as shown in FIG. A positive output signal SO whose level decreases over time in the interval where V 2 is obtained.
is obtained as the output signal of the first-order low-pass filter.
但しこの場合入力信号Ｓ１及びＳ２の電圧を
夫々Ｖs1及びＶs2とするとき、
｜Ｖs1｜＝｜Ｖs2｜＝Ｖs ……(2)
なる関係が得られるべく、入力信号Ｓ１及びＳ２
の振幅の絶対値を互いに等しくし、又電流供給回
路Ｈ１及び電流吸収回路Ｈ２の相互コンダクタン
スを夫々ｇn1及びｇn2とするとき、
ｇn1＝ｇn2＝ｇn ……(3)
なる関係が得られるべく、電流供給回路Ｈ１及び
電流吸収回路Ｈ２を、それ等を構成せるトランジ
スタ乃至回路をして互いに等しい構成とすれば、
電流供給回路Ｈ１より容量素子２１に供給する電
流I1及び電流吸収回路Ｈ２にて容量素子２１から
吸収する電流I2が、
I1＝I2＝ｇnＶs＝I0 ……(4)
に示す如く互いに等しい電流I0として得られ、又
電圧発生回路Ｇの電圧利得をｈとすれば、その電
圧発生回路Ｇより得られる電圧V1及びV2の絶対
値｜V1｜及び｜V2｜が、
｜V1｜＝｜V2｜＝hVs＝V0′ ……(5)
に示す如く互いに等しい絶対電圧V0′で得られ、
更に出力端子TOより得られる出力信号SOの電圧
をV0、容量素子２１の容量をＣとし、又ｓを複
素変数とするとき、出力信号SOが、
V0＝（ｇｎ／ｓＣ＋ｈ）Ｖs ……(6)
で示される電圧V0で得られ、而してこの場合の
第２図に示す本発明による１次低域通過フイルタ
の伝達関数Ｔ(s)′が、詳細説明はこれを省略する
も、
で表わされる１次伝達関数を呈するものである。 However, in this case, when the voltages of the input signals S1 and S2 are V s1 and V s2 respectively, the following relationship is obtained: |V s1 |= |V s2 |=V s ...(2)
When the absolute values of the amplitudes of are made equal to each other, and the mutual conductances of the current supply circuit H1 and the current absorption circuit H2 are g n1 and g n2 respectively, the following relationship is obtained: g n1 = g n2 = g n ...(3) In order to obtain the following, if the current supply circuit H1 and the current absorption circuit H2 have the same structure as the transistors or circuits that constitute them,
The current I 1 supplied from the current supply circuit H1 to the capacitive element 21 and the current I 2 absorbed from the capacitive element 21 by the current absorption circuit H2 are: I 1 = I 2 = g n V s = I 0 ...(4) As shown in , if the voltage gain of the voltage generating circuit G is h , the absolute values of the voltages V 1 and V 2 obtained from the voltage generating circuit G are |V 1 | and |V 2 | are obtained at mutually equal absolute voltages V 0 ' as shown in (5), |V 1 |= |V 2 |=hV s =V 0 '...
Furthermore, when the voltage of the output signal SO obtained from the output terminal TO is V 0 , the capacitance of the capacitive element 21 is C, and s is a complex variable, the output signal SO is V 0 = ( gn / s C + h)V The transfer function T (s) ′ of the first-order low-pass filter according to the present invention shown in FIG. You can also omit It exhibits a first-order transfer function expressed as .
従つて第２図にて上述せる本発明による１次低
域通過フイルタによれば、その伝達関数Ｔ
（ｓ）′が、上述せる(1)及び(7)式を対比することに
より直ちに明らかな如く、第１図にて上述せる従
来の１次低域通過フイルタの伝達関数Ｔ（ｓ）に
全く対応しているを以つて、第１図にて上述せる
と同様に、それを位相同期ループの低域フイルタ
として用いた場合に於て、その位相同期ループの
機能がより安定に得られるべく、この場合の第２
図に示す本発明による１次低域通過フイルタでな
る位相同期ループの位相比較回路に供給されてい
る基準周波数信号の周波数を有する成分に対する
大なる損失効果を与えんとすれば、詳細説明はこ
れを省略するも、τ1′＝Ｃ／ｇｎの値を大とすれば良
い
ものであるが、この場合、電流供給回路Ｈ１及び
電流吸収回路Ｈ２は、これをそれ等の相互コンダ
クタンスｇn1及びｇn2の値をして十分小なる値を
呈するものとして構成することが出来、従つてτ
1′＝Ｃ／ｇｎを第１図にて上述せる従来の１次低域通
過
フイルタの場合に於けるτ1′＝R1Cと同じ値で得
るにつき、容量素子２１の容量Ｃを、第１図にて
上述せる１次低域通過フイルタの場合に於ける容
量素子７の容量Ｃに比し十分小なる値を得、この
為容量素子２１を、電流供給回路Ｈ１、電流吸収
回路Ｈ２、電圧発生回路Ｇと共に半導体集積回路
化して第２図に示す本発明による１次低域通過フ
イルタを半導体集積回路化するに、第１図にて上
述せる従来の１次低域通過フイルタの場合の如く
に困難を伴うことがなく、又斯く半導体集積回路
化しても容量２１の半導体集積回路に占める面積
が大になることがない等の大なる特徴を有するも
のである。 Therefore, according to the first-order low-pass filter according to the invention as described above in FIG. 2, its transfer function T
(s)' is completely different from the transfer function T(s) of the conventional first-order low-pass filter shown in FIG. As mentioned above with reference to FIG. The second in this case
If we want to give a large loss effect to the component having the frequency of the reference frequency signal supplied to the phase comparator circuit of the phase-locked loop consisting of the first-order low-pass filter according to the present invention shown in the figure, the detailed explanation will be as follows. Although it is possible to omit τ 1 '=C/g n , it is sufficient to increase the value of The value of g n2 can be constructed as a sufficiently small value, and therefore τ
1 ′=C/g n is obtained as the same value as τ 1 ′=R 1 C in the case of the conventional first-order low-pass filter described above in FIG. 1, and the capacitance C of the capacitive element 21 is In FIG. 1, a value sufficiently smaller than the capacitance C of the capacitive element 7 in the case of the first-order low-pass filter described above is obtained, and for this reason, the capacitive element 21 is In the case of the conventional first-order low-pass filter described above in FIG. 1, the first-order low-pass filter according to the present invention shown in FIG. This device does not involve any difficulties as described above, and has great features such as the fact that even if it is made into a semiconductor integrated circuit, the area occupied by the capacitor 21 in the semiconductor integrated circuit does not become large.
尚本発明に於てその電流供給回路Ｈ１、電流吸
収回路Ｈ２、及び電圧発生回路Ｇは、図示せる構
成に代えた種々の構成とし得ることが明らかであ
ろう。 It will be obvious that in the present invention, the current supply circuit H1, current absorption circuit H2, and voltage generation circuit G may have various configurations in place of the configuration shown in the drawings.
第１図は従来の１次低域通過フイルタを示す接
続図、第２図は本発明による１次低域通過フイル
タの一例を示す接続図、第３図はその説明に供す
る波形図である。
図中２１は容量素子、Ｈ１は電流供給回路、Ｈ
２は電流吸収回路、Ｔ１及びＴ２は入力端子、Ｔ
０は出力端子を夫々示す。
FIG. 1 is a connection diagram showing a conventional primary low-pass filter, FIG. 2 is a connection diagram showing an example of the primary low-pass filter according to the present invention, and FIG. 3 is a waveform diagram for explaining the same. In the figure, 21 is a capacitive element, H1 is a current supply circuit, and H
2 is a current absorption circuit, T1 and T2 are input terminals, T
0 indicates each output terminal.
Claims (1)
力信号により制御されることにより上記容量素子
にその第１の端子側から第１の電流を供給する電
流供給回路と、 上記容量素子の第１の端子に接続され、第１の
入力信号に対して逆極性の第２の入力信号により
制御されるにより上記容量素子よりその第１の端
子側から第２の電流を吸収する電流吸収回路と、 上記容量素子の第２の端子に接続され、上記第
１及び第２の入力信号に基き互いに逆極性を呈す
る第１及び第２の電圧を発生し、該第１及び第２
の電圧を上記容量素子の第２の端子に与える様に
なされた電圧発生回路とを有し、 上記容量素子の第１の端子より出力信号を導出
する様になされた事を特徴とする１次低域通過フ
イルタ。[Claims] 1. A capacitive element, which is connected to a first terminal of the capacitive element and is controlled by a first input signal to supply a first current to the capacitive element from the first terminal side. a current supply circuit connected to the first terminal of the capacitive element and controlled by a second input signal having a polarity opposite to the first input signal, so that the first terminal side is closer to the capacitive element than the first terminal; a current absorption circuit that absorbs a second current from the capacitive element; and a current absorption circuit that is connected to the second terminal of the capacitive element and generates first and second voltages having opposite polarities based on the first and second input signals. and the first and second
a voltage generating circuit configured to apply a voltage of Low pass filter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2296780A JPS56119520A (en) | 1980-02-26 | 1980-02-26 | Primary low-pass filter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2296780A JPS56119520A (en) | 1980-02-26 | 1980-02-26 | Primary low-pass filter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56119520A JPS56119520A (en) | 1981-09-19 |
| JPS6226606B2 true JPS6226606B2 (en) | 1987-06-10 |
Family
ID=12097344
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2296780A Granted JPS56119520A (en) | 1980-02-26 | 1980-02-26 | Primary low-pass filter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56119520A (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0775318B2 (en) * | 1985-01-31 | 1995-08-09 | 株式会社東芝 | Synthesizer circuit |
| JP2533518B2 (en) * | 1987-03-06 | 1996-09-11 | 株式会社日立製作所 | Phase synchronization circuit |
| JPS63196125U (en) * | 1987-05-30 | 1988-12-16 | ||
| JP2778421B2 (en) * | 1993-09-07 | 1998-07-23 | 日本電気株式会社 | Charge pump type phase locked loop |
| DE60304193T2 (en) * | 2002-05-22 | 2006-08-17 | Matsushita Electric Industrial Co., Ltd., Kadoma | LOW-PASS FILTERS FOR A PLL, LAMP CONTROL AND INTEGRATED SEMICONDUCTOR SWITCHING |
| JP4220843B2 (en) * | 2003-06-27 | 2009-02-04 | パナソニック株式会社 | Low-pass filter circuit and feedback system |
| KR100568538B1 (en) * | 2004-04-09 | 2006-04-07 | 삼성전자주식회사 | Self bias phase locked loop |
| US7307460B2 (en) * | 2005-12-12 | 2007-12-11 | Xilinx, Inc. | Method and apparatus for capacitance multiplication within a phase locked loop |
-
1980
- 1980-02-26 JP JP2296780A patent/JPS56119520A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56119520A (en) | 1981-09-19 |
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