JPS62262422A - Formation of tisi2 film - Google Patents

Formation of tisi2 film

Info

Publication number
JPS62262422A
JPS62262422A JP10594586A JP10594586A JPS62262422A JP S62262422 A JPS62262422 A JP S62262422A JP 10594586 A JP10594586 A JP 10594586A JP 10594586 A JP10594586 A JP 10594586A JP S62262422 A JPS62262422 A JP S62262422A
Authority
JP
Japan
Prior art keywords
film
tisi2
substrate
vacuum
silicon substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10594586A
Other languages
Japanese (ja)
Inventor
Akio Tanigawa
明男 谷川
Eiji Nagasawa
長澤 英二
Hidekazu Okabayashi
岡林 秀和
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP10594586A priority Critical patent/JPS62262422A/en
Publication of JPS62262422A publication Critical patent/JPS62262422A/en
Pending legal-status Critical Current

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  • Solid-Phase Diffusion Into Metallic Material Surfaces (AREA)
  • Physical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To prevent increase in electronic resistance caused by gaseous components, by depositing a film on a substrate and annealing the film in a vacuum without exposing it to the atmosphere. CONSTITUTION:A silicon substrate 1 which has been washed with an acid and treated with diluted fluoric acid is disposed on a substrate heater within a vacuum deposition apparatus. The vacuum deposition apparatus is evacuated to 1X10<-7> torr or below while the silicon substrate 1 is heated to 200 deg.C, so that titanium 2 is deposited on the substrate by means of electronic gun vapor deposition to form a 400Angstrom thick film. The silicon substrate 1 having the titanium film 2 on the surface thereof is heated to 900 deg.C and held at that level for three minutes for forming a TiSi2 film 3 having a thickness of about 1000Angstrom . The silicon substrate 1 is then taken out of the vacuum after the temperature thereof is lowered to 100 deg.C or below. The resulting TiSi2 film 3 has a resistivity of 11.4+0.4muOMEGA.cm. The TiSi2 film 3 may be formed at a temperature of at least 700 deg.C.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明はTiSi2膜の形成方法に関するものである。[Detailed description of the invention] (Industrial application field) The present invention relates to a method for forming a TiSi2 film.

(従来の技術) 従来、半導体装置等に用いるTiSi2膜は他の高融点
金属シリサイド膜の形成方法と同様に、1)Si層を有
する基板表面にTiのみを堆積する知、1i)TiとS
iとを同時に堆積するかした後、一旦大気中に出して電
気炉やランプアニール装置等でアニールする方法等が行
われている。
(Prior art) Conventionally, TiSi2 films used in semiconductor devices, etc. have been formed in the same way as other refractory metal silicide films: 1) depositing only Ti on the surface of a substrate having a Si layer, 1i) depositing Ti and S
A method is used in which, after simultaneously depositing 1 and 2, the material is exposed to the atmosphere and annealed using an electric furnace, a lamp annealing device, or the like.

(発明が解決しようとする問題点) しかしながら、上記従来方法によって形成したTiSi
2膜は大気中の運搬やアニールの際の雰囲気の影響で、
抵抗が増大している。例えば、ムラルカ(S、P、Mu
rarka)によるシリサイドフォアブイエルニスアイ
アプリケーション(Silicides for VL
SIApplications、 New York 
Academic Press、 1983)に記載さ
れている様に前記i)の方法で真空中で30分のアニー
ルを行った時は1311Ω・cm以上、ii)の方法で
水素中で900℃130分のアニールを行った時は〜2
511Ω。
(Problems to be Solved by the Invention) However, TiSi formed by the above conventional method
Due to the influence of the atmosphere during transport and annealing, the two films
Resistance is increasing. For example, Murarka (S, P, Mu
Silicides for VL
SI Applications, New York
Academic Press, 1983), when annealing was performed in vacuum for 30 minutes using method i), the resistance was 1311 Ω·cm or more, and when annealing was performed for 130 minutes at 900°C in hydrogen using method ii) When I went ~2
511Ω.

amの抵抗値である。It is the resistance value of am.

また、固体素子材料コンファレンス第16回国際大会(
1984年)概要集、P、49にあるように、i)の方
法でAr中、700℃のアニールをランプアニール装置
によって30〜120秒行って形成した場合、14〜1
6pΩ・cmである。これらの値は、200OA以上の
膜厚のTiSi2膜で得られたものであり、膜厚が本発
明の実施例のように1000人の膜では比抵抗が増大し
てしまう可能性がある。
In addition, the 16th International Solid State Device Materials Conference (
1984) Summary Collection, P. 49, when annealing is performed in Ar at 700°C for 30 to 120 seconds using a lamp annealing device using method i), 14 to 1
It is 6 pΩ·cm. These values were obtained for a TiSi2 film with a thickness of 200 OA or more, and if the film thickness is 1000 people as in the example of the present invention, the specific resistance may increase.

本発明の目的は低抵抗なTiSi2膜の形成方法を提供
することにある。
An object of the present invention is to provide a method for forming a low-resistance TiSi2 film.

(問題を解決するための手段) 本発明は少なくとも表面i’−8i層を有する基板表面
にTiを真空蒸着した後、700℃以上のアニールによ
ってTiSi2膜を形成する工程において、蒸着からア
ニールまでの工程を真空中で行うことを特徴とするTi
Si2膜の形成方法である。
(Means for solving the problem) The present invention provides a process for forming a TiSi2 film by annealing at 700°C or higher after vacuum-depositing Ti on the surface of a substrate having at least a surface i'-8i layer. Ti characterized in that the process is carried out in vacuum
This is a method of forming a Si2 film.

(作用) TiSi2膜は、気体分子を取り込み易いTiとSiの
反応によって生じる。膜堆積をスパッタによって行えば
、スパッタに用いるAr等の気体成分を取り込み、膜堆
積後に大気にさらせば大気中の02やN2を取り込んで
しまう。これら取り込まれた気体成分はアニール時にT
iSi2膜の成長を阻害し、その電気抵抗値を増大させ
る。
(Function) A TiSi2 film is formed by a reaction between Ti and Si, which easily incorporates gas molecules. If film deposition is performed by sputtering, gas components such as Ar used in sputtering will be taken in, and if the film is exposed to the atmosphere after deposition, O2 and N2 in the atmosphere will be taken in. During annealing, these incorporated gas components are
This inhibits the growth of the iSi2 film and increases its electrical resistance.

本発明のように、膜堆積とアニールを真空中で行い、し
かも、その間に一度も大気にさらすことがなければ気体
成分による電気抵抗の増大は防ぐことができる。
As in the present invention, if film deposition and annealing are performed in a vacuum and the film is never exposed to the atmosphere during the process, an increase in electrical resistance due to gas components can be prevented.

(実施例) 本発明の一実施例を第1図(aXb)の断面図を使って
説明する。
(Example) An example of the present invention will be described using a cross-sectional view of FIG. 1 (aXb).

第1図(a)に示すように酸洗浄及び希釈弗酸処理を施
したSi基板1を真空蒸着装置内の基板加熱装置にセッ
トし、lX1O−7Torr以下に真空排気し、Si基
板1を200℃に加熱してTi2を電子銃蒸着によって
400人堆積し、引き続き、Ti2を表面に有する前記
Si基板1を900℃に加熱して3分間保持し第1図(
b)に示すように、約1000人のTiSi2膜3を形
成した。
As shown in FIG. 1(a), a Si substrate 1 that has been acid-cleaned and treated with diluted hydrofluoric acid is set in a substrate heating device in a vacuum evaporation device, and evacuated to a temperature of 1×1 O−7 Torr or less. ℃, and deposited 400 Ti2 by electron gun evaporation.Subsequently, the Si substrate 1 having Ti2 on the surface was heated to 900℃ and held for 3 minutes, as shown in FIG.
As shown in b), about 1000 TiSi2 films 3 were formed.

その後、前記Si基板1の温度が1006C以下になっ
てから真空中より取り出した。形成されたTi512M
3の比抵抗は11.4±0.4μΩ・cmで報告された
いかなるTiSi2よりも低抵抗だった。TiSi2膜
3の形成温度は上記の900℃である必要はなく、70
0℃以上であればいずれも同様の結果を得た。
Thereafter, after the temperature of the Si substrate 1 became 1006 C or less, it was taken out from the vacuum. Formed Ti512M
The specific resistance of TiSi2 was 11.4±0.4 μΩ·cm, which was lower than any reported TiSi2. The formation temperature of the TiSi2 film 3 does not need to be the above-mentioned 900°C;
Similar results were obtained in all cases at temperatures above 0°C.

(発明の効果) 本発明によれば、極めて低抵抗なTiSi2膜が短い熱
処理時間で再現性よく形成することができる。
(Effects of the Invention) According to the present invention, an extremely low resistance TiSi2 film can be formed with good reproducibility in a short heat treatment time.

【図面の簡単な説明】[Brief explanation of drawings]

Claims (1)

【特許請求の範囲】[Claims] 少なくとも表面にSi層を有する基板表面にTiを真空
蒸着によって堆積した後、700℃以上のアニールによ
ってTiSi_2膜を形成する工程において、蒸着から
アニールまでの工程を真空中で行うことを特徴とするT
iSi_2膜の形成方法。
In the process of depositing Ti by vacuum evaporation on the surface of a substrate having a Si layer on at least the surface, and then annealing at 700°C or higher to form a TiSi_2 film, the process from evaporation to annealing is performed in a vacuum.
Method for forming iSi_2 film.
JP10594586A 1986-05-08 1986-05-08 Formation of tisi2 film Pending JPS62262422A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10594586A JPS62262422A (en) 1986-05-08 1986-05-08 Formation of tisi2 film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10594586A JPS62262422A (en) 1986-05-08 1986-05-08 Formation of tisi2 film

Publications (1)

Publication Number Publication Date
JPS62262422A true JPS62262422A (en) 1987-11-14

Family

ID=14420983

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10594586A Pending JPS62262422A (en) 1986-05-08 1986-05-08 Formation of tisi2 film

Country Status (1)

Country Link
JP (1) JPS62262422A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04226025A (en) * 1990-04-16 1992-08-14 Applied Materials Inc Method forming titanium silicide con- ducting layer on silicon wafer
JPH05102075A (en) * 1991-03-29 1993-04-23 Applied Materials Inc Method for forming tungsten contact having low resistance and low defect density for silicon semiconductor wafer
JPH07111252A (en) * 1990-04-20 1995-04-25 Applied Materials Inc Method for formation of titanium nitride on semiconductor wafer by reaction of nitrogen-contained gas with titanium in integrated treatment system
JP2002280290A (en) * 2001-03-21 2002-09-27 Nec Corp Mask for electron beam exposure, and method for electron beam exposure using the same
SG121692A1 (en) * 2001-07-31 2006-05-26 Inst Materials Research & Eng Improvements in or relating to silicidation techniques
WO2011043120A1 (en) * 2009-10-05 2011-04-14 住友電気工業株式会社 Method for manufacturing a semiconductor device

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04226025A (en) * 1990-04-16 1992-08-14 Applied Materials Inc Method forming titanium silicide con- ducting layer on silicon wafer
JPH07111252A (en) * 1990-04-20 1995-04-25 Applied Materials Inc Method for formation of titanium nitride on semiconductor wafer by reaction of nitrogen-contained gas with titanium in integrated treatment system
JPH05102075A (en) * 1991-03-29 1993-04-23 Applied Materials Inc Method for forming tungsten contact having low resistance and low defect density for silicon semiconductor wafer
JP2002280290A (en) * 2001-03-21 2002-09-27 Nec Corp Mask for electron beam exposure, and method for electron beam exposure using the same
SG121692A1 (en) * 2001-07-31 2006-05-26 Inst Materials Research & Eng Improvements in or relating to silicidation techniques
WO2011043120A1 (en) * 2009-10-05 2011-04-14 住友電気工業株式会社 Method for manufacturing a semiconductor device
JP2011082254A (en) * 2009-10-05 2011-04-21 Sumitomo Electric Ind Ltd Method for manufacturing semiconductor device
CN102549728A (en) * 2009-10-05 2012-07-04 住友电气工业株式会社 Method for manufacturing a semiconductor device
US8846531B2 (en) 2009-10-05 2014-09-30 Sumitomo Electric Industries, Ltd. Method of manufacturing an ohmic electrode containing titanium, aluminum and silicon on a silicon carbide surface
CN102549728B (en) * 2009-10-05 2015-06-03 住友电气工业株式会社 Method for manufacturing a semiconductor device

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