JPS62260353A - Qsemiconductor device - Google Patents

Qsemiconductor device

Info

Publication number
JPS62260353A
JPS62260353A JP10532486A JP10532486A JPS62260353A JP S62260353 A JPS62260353 A JP S62260353A JP 10532486 A JP10532486 A JP 10532486A JP 10532486 A JP10532486 A JP 10532486A JP S62260353 A JPS62260353 A JP S62260353A
Authority
JP
Japan
Prior art keywords
wiring substrates
functions
wiring
chips
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10532486A
Other languages
Japanese (ja)
Inventor
Miyoshi Yoshida
吉田　美義
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP10532486A priority Critical patent/JPS62260353A/en
Publication of JPS62260353A publication Critical patent/JPS62260353A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

PURPOSE:To prevent the large increase of the volume of the whole even when the number of LSI chips loaded for enlarging a functional scale is increased by laminating and mounting a plurality of wiring substrates so that the main surfaces of the wiring substrates mutually run parallel. CONSTITUTION:A plurality of semiconductor chips 11 having active functions consisting of P-N junctions are disposed onto a plurality of wiring substrates 13, 14, main surfaces of which have wirings mutually connecting and compounding the active functions of these semiconductor chips 11 and external electrodes extracting the functions of the chips to the outside. A plurality of these wiring substrates 13, 14 are laminated and fitted onto an insulating substrate 16 fixing and holding electrical functions acquired by said wiring substrates 13, 14 and having external pins 17 for transmitting the electrical functions over the outside so that the main surfaces of the wiring substrates mutually run parallel. Accordingly, a large number of the LSI chips can be loaded without enlarging the volume of the whole so much, and the number of the LSI chips can easily be increased only by the number of newly laminated layers when the number fo the wiring substrates laminated are increased.

Description

【発明の詳細な説明】 ［産業上の利用分野］ この発明は、半導体装置に関し、特に、１つのパッケー
ジ内に多数の半導体チップを組立てる、いわゆるマルチ
チップパッケージングを適用することのできる半導体装
置に関するものである。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device to which so-called multi-chip packaging, in which a large number of semiconductor chips are assembled in one package, can be applied. It is something.

［従来の技術］ 従来、この種の半導体装置では、パッケージ内に半導体
チップ（以下ＬＳＩチップと称す）を平面実装していた
。第６図は、このような従来の半導体装置の斜視図であ
り、第７図はその断面図である。図において、１は３ｉ
からなる多数個のＬＳＩチップで、その主面にＰＮ接合
を形成している。これら多数個のＬＳＩチップ１で半導
体装置の全体の機能を構成する。２はＬＳＩチップ１上
に形成されたＰｂ−８ｎ合金からなる′Ｒ極（以下バン
ブと称す）である。３はＬＳＩチップ１のは能を相互に
接続する配線基板、６は配ｍＷ仮３を収納する絶縁基板
、５はＰ２線基板３と絶縁基板６とを電気的に接続する
ワイヤ、７は半導体装置の８機能を外部に取出すための
外部ビンである。[Prior Art] Conventionally, in this type of semiconductor device, a semiconductor chip (hereinafter referred to as an LSI chip) is planarly mounted within a package. FIG. 6 is a perspective view of such a conventional semiconductor device, and FIG. 7 is a sectional view thereof. In the figure, 1 is 3i
A PN junction is formed on the main surface of a large number of LSI chips. These many LSI chips 1 constitute the entire function of the semiconductor device. Reference numeral 2 denotes an 'R pole (hereinafter referred to as bump) formed on the LSI chip 1 and made of a Pb-8n alloy. 3 is a wiring board that interconnects the functions of the LSI chip 1, 6 is an insulating board that houses the wiring board 3, 5 is a wire that electrically connects the P2 wire board 3 and the insulating board 6, and 7 is a semiconductor. This is an external bin for taking out the eight functions of the device.

次に動作について説明する。Next, the operation will be explained.

ＬＳＩチップ１の主面に形成したＰＮ接合による機能は
その主面と同一平面上の任意の位置から取出すことがで
きる。相互接続配線を形成した配線基板３の主面とＬＳ
Ｉチップ１の主面とを平行に対向して配置すれば、その
間隙に位置するバンブ２によってＬＳＩチップ１の機能
と配置ｉｔ基板３の相互接続配線を電気的に接続するこ
とができる。The function of the PN junction formed on the main surface of the LSI chip 1 can be taken out from any position on the same plane as the main surface. Main surface of wiring board 3 and LS on which interconnection wiring is formed
If the main surfaces of the I-chip 1 are arranged parallel to each other and facing each other, the functions of the LSI chip 1 and the interconnection wiring of the IT board 3 can be electrically connected by the bumps 2 located in the gap.

この配線基板３は、ワイヤ５によって絶縁基板６と電気
的につながる。外部ピン７は、この半導体装置の機能を
外部に取出すものであるので、結局ＬＳＩチップ１、バ
ンブ２、配Ｉ！１ＩＪ１板３、ワイヤ５、外部ピン７を
通じて半導体装置の機能が完成し、外部に伝達すること
ができる。これらの機能は絶縁基板６に取付ける蓋（図
示せず）によって保ｄされるので、通常の取扱いではこ
の機能が損傷するということはなく、マルチチップパッ
ケージングした半導体装置として動作する。This wiring board 3 is electrically connected to an insulating board 6 via wires 5. The external pins 7 are for taking out the functions of this semiconductor device to the outside, so in the end, the LSI chip 1, the bumps 2, and the wiring I! The functions of the semiconductor device are completed through the 1IJ1 board 3, wires 5, and external pins 7, and can be transmitted to the outside. Since these functions are maintained by a lid (not shown) attached to the insulating substrate 6, these functions are not damaged by normal handling, and the semiconductor device operates as a multi-chip packaged semiconductor device.

［発明が解決しようとする問題点］ 従来のマルチチップパッケージでは、ＬＳＩチップ１の
主面と配線基板３の主面とを平行対向して配置し、配線
基板３を１つだけ絶縁！Ｓ根６に搭載していたので、半
導体装置内に搭載し得るＬＳＩチップの数が制限されて
いた。これは、搭載するＬＳＩチップ１の主面の総面積
は配線基板３の主面の面積よりも小さくしなければなら
ないためである。したがって、その半導体装置の機能規
模を大きくしようとしてＬＳＩチップ１の数を増せば、
配線基板３の主面の面積を大きくしなければならず、結
局、半導体装置の平面が大きくなり、大型の装置になっ
てしまうという欠点があった。[Problems to be Solved by the Invention] In the conventional multi-chip package, the main surface of the LSI chip 1 and the main surface of the wiring board 3 are arranged parallel to each other, and only one wiring board 3 is insulated! Since they were mounted on the S root 6, the number of LSI chips that could be mounted within the semiconductor device was limited. This is because the total area of the main surfaces of the LSI chips 1 to be mounted must be smaller than the area of the main surfaces of the wiring board 3. Therefore, if the number of LSI chips 1 is increased in an attempt to increase the functional scale of the semiconductor device,
The area of the main surface of the wiring board 3 has to be increased, resulting in a large plane of the semiconductor device, resulting in a large device.

この発明は、上述のような従来の欠点を解消するために
なされたものであり、その目的は、標能規模を大きくプ
るために搭載するＬＳＩチップ数を増加させても、全体
の体積があまり増加しない。This invention was made in order to eliminate the above-mentioned drawbacks of the conventional technology.The purpose of this invention is to increase the number of LSI chips mounted in order to increase the standard scale, but the overall volume remains small. It doesn't increase much.

つまり実装密度の高い小形の半導体装置を提供すること
である。In other words, the objective is to provide a compact semiconductor device with high packaging density.

［問題点を解決するための手段］ この発明に従った半導体装置は、ＬＳＩチップを３次元
実装するものである。具体的には、この発明に従った半
導体＠茸は、複数個の半導体チップと、複数個の配線基
板と、絶縁基板とを備えている。半導体チップは、ＰＮ
接合からなる能動機能を有している。配線基板は、半導
体チップの能動機能を互いに接続、複合する配線と、そ
のｎ能を外８１ｉに取出す外部電極とをその主面に有し
ている６絶縁基板は、配Ｉｊ１基板によって得られる電
気的瀕能を固定、保持し、その電気的機能を外部に伝達
するための外部ピンを有している。[Means for Solving the Problems] A semiconductor device according to the present invention three-dimensionally mounts an LSI chip. Specifically, the semiconductor@mushroom according to the present invention includes a plurality of semiconductor chips, a plurality of wiring boards, and an insulating substrate. The semiconductor chip is PN
It has an active function consisting of bonding. The wiring board has on its main surface wiring that connects and combines the active functions of the semiconductor chips, and external electrodes that take out the n functions to the outside 81i. It has an external pin for fixing and holding the target and transmitting its electrical function to the outside.

そして、１！数個の配＆１基板は、その主面が互いに平
行になるように積層して設けられている。And 1! Several distribution &1 substrates are stacked and provided so that their main surfaces are parallel to each other.

しす１ミ用］ ＬＳＩチップを平面実装した配線基板の厚みは、その主
面の一辺の長さに比べて極めて小さい。したがって、複
数個の配Ｉ！ｉｌ！ｓ板を、その主面が互いに平１テに
なるように８！１層しても、その厚みは主面の一辺の長
さに比べて依然として小さい。半導体装置のＬＳＩチッ
プ実装密度は、半導体装置の体積あたりのしＳｌチップ
数である。ここで、半導体装置の体積は、絶ａ基板の厚
み、配Ｐｉｌ基板の厚み、伯の厚みなどの総厚みとその
平面面積との積である。したがって、配線基板の層数を
増せば、ＬＳＩチップ数はその層数倍だけ増えるが、全
体の体積はほとんど増加しない。つまり、この発明に従
った半導体装置によれば、全体の体積はそれほど増えな
いのに、そこに搭載したＬＳＩチップ数は積層したｍ数
倍だけ増加する。[For Shisu 1mm] The thickness of the wiring board on which the LSI chip is planarly mounted is extremely small compared to the length of one side of its main surface. Therefore, multiple distributions I! Il! Even if 8!1 layers of s-plates are stacked so that their main surfaces are flat with each other, the thickness is still small compared to the length of one side of the main surfaces. The LSI chip mounting density of a semiconductor device is the number of Sl chips per volume of the semiconductor device. Here, the volume of the semiconductor device is the product of the total thickness, such as the thickness of the absolute substrate, the thickness of the plate substrate, and the thickness of the plate, and its plane area. Therefore, if the number of layers of the wiring board is increased, the number of LSI chips will increase by the number of layers, but the overall volume will hardly increase. In other words, according to the semiconductor device according to the present invention, the number of LSI chips mounted therein increases by the number of m times the number of stacked LSI chips, although the overall volume does not increase that much.

［実［１］ 第１図は、この発明の一寅施例な示す斜視図であり、第
２図はその断面図である。図において、１１は３ｉから
なる半導体チップ（ＬＳＩチップ）で、ＰＮ接合をその
主面に形成している。１２は電極（バンブ）である。１
３は、ＬＳＩチップ１１を相互に接続する配線をその主
面に形成したＳｌからなる第１の配ｓｉ板である。１４
は、ＬＳＩチップ１１を相互に接続する配線と第１配′
６基ｔｆｉ１３の機能を接続する配線をその主面に形成
したＳｌからなる１ｇ２の配Ｐｉｎ板である。１５ａｕ
、第１配緑基板１３と第２配線逢板１４とを電気的に接
続するワイヤ、１５ｂは、第２配線基板１４と絶縁基板
１６とを電気的に接続するワイヤである。なあ、絶縁基
板１６は、第１配線基板１３と第２配線基板１４とを収
納している。１７は半導体５Ａ茸の機能を外部に取出す
ための外部ピン、１８は第１配＄５ｉｔ塁板１３と第２
配線塾仮１４との間に位置し、それらを空間的に分這す
るための同一の厚みを有するＳｉからなるスペーサであ
る。[Example 1] Fig. 1 is a perspective view showing one embodiment of the present invention, and Fig. 2 is a sectional view thereof. In the figure, 11 is a semiconductor chip (LSI chip) made of 3i and has a PN junction formed on its main surface. 12 is an electrode (bump). 1
Reference numeral 3 denotes a first Si distribution board made of Sl and having wiring for interconnecting the LSI chips 11 formed on its main surface. 14
are the wiring interconnecting the LSI chips 11 and the first wiring.
It is a 1g2 pin board made of Sl and has wiring connecting the functions of six TFIs 13 formed on its main surface. 15au
A wire 15b electrically connects the first green board 13 and the second wiring board 14, and a wire 15b electrically connects the second wiring board 14 and the insulating board 16. Incidentally, the insulating substrate 16 houses the first wiring board 13 and the second wiring board 14. 17 is an external pin for taking out the function of the semiconductor 5A mushroom to the outside, 18 is the first base plate 13 and the second
This is a spacer made of Si and having the same thickness and located between the wiring school temporary 14 and spatially separating them.

次に動作について説明する。Next, the operation will be explained.

ＬＳＩチップ１１の有する機能は、バンブ１２を介して
、第１配ｍＭ仮１３・の配線につながり、相互に接続さ
れる。そして、この第１配口式板には、この半導体装置
の全機能のうらの一部の機能であるサブシステムが完成
する。他のＬＳＩチップ１は、バンブ１２を介して第２
の配線基板１４に同様に接続され、ここでも半導体装置
全機能の一部であるサブシステムを形成する。この両サ
ブシステムによって半導体装置の金券能が揃ったことに
なる。第２配線基板１４は、絶縁基板１６に固定される
。第１配ＩｉＩ！ｓ板１３は、その主面が第２配線！！
［１４の主面と互いに平行になるように、スペーサ１８
を介して第２配線基板１４の上に積層される。第１配線
基板１３と第２配線任板１４とは、ワイヤ１５ａを介し
て電気的に接続され、第２配ｇｉ１基板１４と絶縁基板
１６とはワイヤ１５ｂを介して電気的に接続される。こ
うすることによって、第１配ＦｉｌｔＭ１３のサブシス
テムと第２配線曇板１４のサブシステムとを複合し、か
つその全機能を絶縁基板１６に接続したことになる。The functions of the LSI chip 11 are connected via the bumps 12 to the wiring of the first mm temporary 13, and are connected to each other. A subsystem, which is a part of all the functions of this semiconductor device, is completed in this first port type plate. The other LSI chip 1 is connected to the second LSI chip via the bump 12.
The semiconductor device is similarly connected to the wiring board 14 of the semiconductor device, and here also forms a subsystem that is part of the overall functionality of the semiconductor device. These two subsystems complete the functionality of the semiconductor device. The second wiring board 14 is fixed to the insulating substrate 16. 1st distribution IiI! The main surface of the S board 13 is the second wiring! !
[Spacer 18 so that it is parallel to the main surface of 14
It is laminated on the second wiring board 14 via. The first wiring board 13 and the second wiring board 14 are electrically connected via a wire 15a, and the second wiring board 14 and the insulating board 16 are electrically connected via a wire 15b. By doing this, the subsystem of the first wiring board M13 and the subsystem of the second wiring board 14 are combined, and all their functions are connected to the insulating substrate 16.

外部ピン１７は、半導体装置の機能を外部に取出す構造
になっているので、このサブシステムを組合わせた全ａ
ｍが外部ピン１７によって外部に取出せる。The external pin 17 has a structure that extracts the functions of the semiconductor device to the outside, so the entire a
m can be taken out to the outside by an external pin 17.

このようにして、第１図および第２図に示した実施例に
よれば、従来のものに比べて、２倍のＬＳＩチップ数を
同一絶縁基板の中に搭載してかつその機能を外部に取出
すことができる。この場合、積＠された配ＪＩＢ板の厚
みはその主面の一辺の長さに比べて小さいので、半導体
Ｖ４ｆｆｉ全体としての体積は従来のものとあまり異な
らない。なお、ＬＳＩチップ１１、バンブ１２、第１　
配ａａｌＨｆ２１３、第２配！９塁板１４、ワイヤ１５
ａ、１５＋１等はそれらを取囲む蓋（図示せず）によっ
て保護されるので、通常の取板いによってはその機能が
屓傷を受けるということはない。このようにしてＬＳＩ
チップ１１を搭載した第１配線基板１３と第２配線基板
１４とをその主面が互いに平行になるように積層して配
置、構成したので、従来のものに比べて２倍の機能を同
一絶縁基板内に搭載したフルチチップパッケージング半
導体装置として動作する。In this way, according to the embodiment shown in FIGS. 1 and 2, twice the number of LSI chips can be mounted on the same insulating substrate compared to the conventional one, and the functions can be transferred externally. It can be taken out. In this case, since the thickness of the stacked JIB boards is smaller than the length of one side of the main surface, the volume of the semiconductor V4ffi as a whole does not differ much from that of the conventional one. Note that the LSI chip 11, the bump 12, the first
Distribution aalHf213, 2nd distribution! 9th base board 14, wire 15
A, 15+1, etc. are protected by a lid (not shown) surrounding them, so that their functions will not be compromised by normal mounting. In this way, LSI
The first wiring board 13 on which the chip 11 is mounted and the second wiring board 14 are stacked and configured so that their main surfaces are parallel to each other, so that the same insulation function has twice the function as the conventional one. It operates as a full-chip packaging semiconductor device mounted within a substrate.

なお、第１図および第２図に示した実施例では、第２配
Ｉ２基板１４上に積層される第１配Ｐｉｌ基板１３の層
数はただ１層であったが、その層数に限定されるもので
はない。たとえば、第３図に示した他の実施例では、第
１配ｍ塁板１３として、２層の配Ｉ！ｉ１基板が用いら
れている。また、他の例として、第２配Ｐｉｌ基板１４
を絶縁Ｍ板１６の中に形成し、絶１！１根１６と一体化
したものであってもよい。Note that in the embodiment shown in FIGS. 1 and 2, the number of layers of the first Pil board 13 laminated on the second I2 board 14 is only one, but the number of layers is limited to one. It is not something that will be done. For example, in another embodiment shown in FIG. i1 substrate is used. In addition, as another example, the second distribution Pil board 14
may be formed in the insulating M plate 16 and integrated with the 1!1 base 16.

第４図は、この発明のさらに他の実施例を示す断面図で
ある。第１図および第２図に示した実施例では、１個の
第１配＄１塁板１３を１個の第２配線塁仮１４の上に積
層したが、この実施例では、はぼ同一平面内に配置され
た複ａ個の７ｇ４１配線基板１３を第２配ｍ基板１４上
に積層している。FIG. 4 is a sectional view showing still another embodiment of the invention. In the embodiments shown in FIGS. 1 and 2, one first base board 13 is laminated on one second base board 14, but in this embodiment, they are almost identical. A plurality of 7G41 wiring boards 13 arranged in a plane are stacked on the second m distribution board 14.

第５図は、この発明のざらに他の実施例を示す断面図で
ある。この実施例では、第１配線１＃ｆｉ１３と第２配
線基板１４とは、その主面が互いに対向するように積層
して設けられており、さらにその内憂板１３．１４はコ
ネクタ１５Ｃを介して接続されている。FIG. 5 is a sectional view showing roughly another embodiment of the present invention. In this embodiment, the first wiring 1 #fi 13 and the second wiring board 14 are stacked so that their main surfaces face each other, and furthermore, the wiring boards 13 and 14 are connected via the connector 15C. It is connected.

なお、ワイヤ１５’ａ、１５ｂ、：Ｉネクタ１５Ｃが他
の配線、たとえばフィルム上に形成されｔ＝　ＣｕＰｉ
ｉ線であってもよい。また、第１配Ｉ！基板１３トｉ　
２　配５１Ｍ板１４　ト（７）ｆ１１１’、１１配置１
１１ｓｌｆ２［、あるいはＬＳＩチップ裏面に放熱のた
めの伝熱媒体を配置してもよいことは当然である。Note that if the wires 15'a, 15b, :I connector 15C are formed on other wiring, for example, a film, t=CuPi
It may be i-line. Also, the first distribution I! Board 13 toi
2 arrangement 51M plate 14 g (7) f111', 11 arrangement 1
11slf2 [or a heat transfer medium for heat radiation may be arranged on the back surface of the LSI chip.

（発明の効果］ 以上のように、この発明によれば、ＬＳＩチップを接続
した複数の配ＰｉＩ基板を、その主面が互いに平行にな
るように積層して設置ブているので、全体の体積をあま
り増加させることなく多ｖｊ１個のＬＳＩチップを搭載
することができる。積層される配線基板の暦数を増加さ
せれば、ＬＳＩチップ数をその層数倍だけ容易に増加す
ることができる。(Effects of the Invention) As described above, according to the present invention, a plurality of PiI boards to which LSI chips are connected are stacked and installed so that their main surfaces are parallel to each other, so that the overall volume is reduced. One LSI chip can be mounted without significantly increasing the number of layers.By increasing the number of wiring boards to be stacked, the number of LSI chips can be easily increased by twice the number of layers.

その結果、半導体装置の高密度大規模化を容易に実現す
ることができる。As a result, higher density and larger scale semiconductor devices can be easily realized.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、この発明の一実施例を示す概略斜視図である
。第２図は、第１図に示した実施例の概略断面図である
。第３図は、この発明の他の実施例の概略断面図である
。第４図は、この発明のざらに他の実施例の概略断面図
である。第５図は、この発明のざらに他の実施例の概略
断面図である。 第６図は、従来の半導体装置の概略斜視図である。第７
図は、第６図に示した半導体！ｉｆｊ＃の概略断面図で
ある。 図において、１１は半導体チップ（ＬＳＩチップ）、１
３は第１配ｌ！ｉＡ基根、１４は第２配ｍ基板、１６は
絶縁基板を示す。 なお、図中、同一符号は同一、または相当部分を示す。 代理人　　　大　　岩　　増　　雄 萬１図 １６：胞球基杖 萬３図 １ビ 第４図 第Ｓ図FIG. 1 is a schematic perspective view showing an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of the embodiment shown in FIG. FIG. 3 is a schematic cross-sectional view of another embodiment of the invention. FIG. 4 is a schematic sectional view of another embodiment of the invention. FIG. 5 is a schematic sectional view of another embodiment of the invention. FIG. 6 is a schematic perspective view of a conventional semiconductor device. 7th
The diagram shows the semiconductor shown in Figure 6! It is a schematic sectional view of ifj#. In the figure, 11 is a semiconductor chip (LSI chip);
3 is the first choice! The iA base, 14 is a second molar board, and 16 is an insulating board. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Agent Masu Oiwa Yuman 1 Figure 16: Kyoko Kijo Man 3 Figure 1 B Figure 4 Figure S

Claims (1)

【特許請求の範囲】 　ＰＮ接合からなる能動機能を有する複数個の半導体チ
ップ、 前記半導体チップの能動機能を互いに接続、複合する配
線と、その機能を外部に取出す外部電極とをその主面に
有する複数個の配線基板、および前記配線基板によつて
得られる電気的機能を固定、保持し、その電気的機能を
外部に伝達するための外部ピンを有する絶縁基板を備え
、 前記複数個の配線基板は、その主面が互いに平行になる
ように積層して設けられている、半導体装置。[Scope of Claims] A plurality of semiconductor chips each having an active function consisting of a PN junction, having on its main surface wiring that connects and combines the active functions of the semiconductor chips with each other and an external electrode that extracts the function to the outside. a plurality of wiring boards, and an insulating board having external pins for fixing and holding electrical functions provided by the wiring boards and transmitting the electrical functions to the outside, the plurality of wiring boards are semiconductor devices that are stacked so that their main surfaces are parallel to each other.
JP10532486A 1986-05-06 1986-05-06 Qsemiconductor device Pending JPS62260353A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10532486A JPS62260353A (en) 1986-05-06 1986-05-06 Qsemiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10532486A JPS62260353A (en) 1986-05-06 1986-05-06 Qsemiconductor device

Publications (1)

Publication Number Publication Date
JPS62260353A true JPS62260353A (en) 1987-11-12

Family

ID=14404533

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10532486A Pending JPS62260353A (en) 1986-05-06 1986-05-06 Qsemiconductor device

Country Status (1)

Country Link
JP (1) JPS62260353A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0720232A4 (en) * 1993-09-14 1996-11-13 Toshiba Kk Multi-chip module
US5650920A (en) * 1995-07-27 1997-07-22 Motorola, Inc. Mount for supporting a high frequency transformer in a hybrid module
US5856915A (en) * 1997-02-26 1999-01-05 Pacesetter, Inc. Vertically stacked circuit module using a platform having a slot for establishing multi-level connectivity
US6717275B2 (en) 2001-10-29 2004-04-06 Renesas Technology Corp. Semiconductor module
US6867496B1 (en) 1999-10-01 2005-03-15 Seiko Epson Corporation Interconnect substrate, semiconductor device, methods of fabricating, inspecting, and mounting the semiconductor device, circuit board, and electronic instrument
US7211884B1 (en) 2002-01-28 2007-05-01 Pacesetter, Inc. Implantable medical device construction using a flexible substrate
CN110337178A (en) * 2019-04-25 2019-10-15 维沃移动通信有限公司 A kind of circuit board assemblies and electronic equipment

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0720232A4 (en) * 1993-09-14 1996-11-13 Toshiba Kk Multi-chip module
US5650920A (en) * 1995-07-27 1997-07-22 Motorola, Inc. Mount for supporting a high frequency transformer in a hybrid module
US5856915A (en) * 1997-02-26 1999-01-05 Pacesetter, Inc. Vertically stacked circuit module using a platform having a slot for establishing multi-level connectivity
US6867496B1 (en) 1999-10-01 2005-03-15 Seiko Epson Corporation Interconnect substrate, semiconductor device, methods of fabricating, inspecting, and mounting the semiconductor device, circuit board, and electronic instrument
US7009293B2 (en) 1999-10-01 2006-03-07 Seiko Epson Corporation Interconnect substrate, semiconductor device, methods of fabricating, inspecting, and mounting the semiconductor device, circuit board, and electronic instrument
US6717275B2 (en) 2001-10-29 2004-04-06 Renesas Technology Corp. Semiconductor module
US7211884B1 (en) 2002-01-28 2007-05-01 Pacesetter, Inc. Implantable medical device construction using a flexible substrate
CN110337178A (en) * 2019-04-25 2019-10-15 维沃移动通信有限公司 A kind of circuit board assemblies and electronic equipment
CN110337178B (en) * 2019-04-25 2021-03-23 维沃移动通信有限公司 Circuit board assembly and electronic equipment

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