JPS62254240A - System switching method - Google Patents
System switching methodInfo
- Publication number
- JPS62254240A JPS62254240A JP61096795A JP9679586A JPS62254240A JP S62254240 A JPS62254240 A JP S62254240A JP 61096795 A JP61096795 A JP 61096795A JP 9679586 A JP9679586 A JP 9679586A JP S62254240 A JPS62254240 A JP S62254240A
- Authority
- JP
- Japan
- Prior art keywords
- processor
- bus
- active
- spare
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims description 5
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
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- Hardware Redundancy (AREA)
- Monitoring And Testing Of Exchanges (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野］
本発明は、二重化された内蔵プログラム制御方式の装置
において、現用系から予備系装置へ切替る系切替方式に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a system switching method for switching from an active system to a standby system in a duplex built-in program control system.
従来、冗長構成を用いた現用系から予備系への系切替方
式については、ＮＴＴ、研究実用化報告第３１巻第１１
号（１９８２） 、 ”ディジタル加入者線交換機の
プログラム構成″の中で論じられているが、この方式で
は、メモリバス及び入出力用バスが各々個別に切替られ
る長所はあるが、系切替の制御が複雑になり、ハードウ
ェア量も多くなり非常に高価なものとなる。Conventionally, regarding the system switching system from the active system to the standby system using redundant configuration, NTT, Research and Practical Application Report Vol. 31, No. 11
No. (1982), ``Program structure of digital subscriber line switching equipment'', this method has the advantage of switching the memory bus and input/output bus individually, but it is difficult to control system switching. becomes complicated, requires a large amount of hardware, and becomes very expensive.
本発明の目的は、現用系の一時的な障害で系切替が発生
しても、新たな現用系とは全く独立に障害系の初期設定
を行い、障害が回復した場合に速やかに正常な予備系と
してシステムに組み込むことを可能とし、安価にシステ
ムの高信頼性を確保する系切替方法を提供することにあ
る。The purpose of the present invention is to perform the initial settings of the faulty system completely independently of the new active system even if system switching occurs due to a temporary failure of the active system, and to quickly restore the normal backup system when the failure is recovered. It is an object of the present invention to provide a system switching method that can be incorporated into a system as a system and that ensures high reliability of the system at low cost.
上記目的を達成するため、バス交絡制御装置に現用／予
備の系切替手段と、系切替時に新たな現用系のバスと障
害系バスの分離する手段と、障害系のイニシャルプログ
ラムロードを起動する手段を設け、一時的な障害発生に
よる系切替時、新たな現用系は障害系とは独立に運転を
継続し、かつ障害系はイニシャルプログラムロードによ
り初期設定を行い、障害回復後は速やかにシステムに組
み込むことを可能にする。In order to achieve the above object, the bus confounding control device includes working/standby system switching means, means for separating the new working system bus and faulty bus at the time of system switching, and means for activating the initial program load of the faulty system. When a system is switched due to a temporary failure, the new active system continues to operate independently of the failed system, and the failed system performs initial settings by loading an initial program, and after the failure is recovered, the system is quickly restored. allow for embedding.
次に、本発明の実施例について、図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of the present invention.
第１図の２重化されたプロセッサシステム構成において
、現用系及び予備系のプロセッサシステムは、各々プロ
セッサ１０，１．１．メインメモリ２０．２１．ファイ
ルメモリ３０，３１．プロセッサバス４０，４１から構
成され、現用系と予備系はバス交絡制御装置１００で系
交絡されている。In the dual processor system configuration shown in FIG. 1, the active and standby processor systems each include processors 10, 1.1. Main memory 20.21. File memory 30, 31. It is composed of processor buses 40 and 41, and the active system and standby system are interlaced by a bus interlacing control device 100.
通常のシステム運転においては、現用系プロセッサ１０
は現用系メインメモリ２０．現用系ファイルメモリ３０
だけでなく、予備系メインメモリ２１、予備系ファイル
モメリ３１にもアクセス可能である６一方、予備系のプ
ロセッサ１１は予備系メモリ２１及びファイルメモリ３
１にはアクセスできない。During normal system operation, the active processor 10
is the active main memory 20. Active file memory 30
In addition, the backup main memory 21 and the backup file memory 31 can also be accessed.6 Meanwhile, the backup processor 11 can access the backup main memory 21 and file memory 3.
1 cannot be accessed.
第２図は第１図のシステムの構成において、バス交絡制
御袋［１００により、プロセッサバス４０．４１が分離
され、現用系プロセッサシステムは現用系メインメモリ
と現用系ファイルのみにアクセス可能で、同様に予備系
プロセッサシステムは予備系メインメモリと予備系ファ
イルのみにアクセス可能である。FIG. 2 shows that in the system configuration of FIG. 1, the processor buses 40 and 41 are separated by the bus entanglement control bag [100], and the active processor system can access only the active main memory and the active files. In this case, the spare processor system can only access the spare main memory and spare files.
次に第１図の状態でシステムを運転中に系切替が発生し
た場合の動作について説明する。現用系プロセッサシス
テムにおいて、現用系プロセッサ１０が現用系ハードウ
ェアの一時的障害を検出し、予備系プロセッサシステム
に切替る場合、現用系プロセッサ１０はプロセッサバス
４０を介して、バス交絡制御装置１００に系切替オーダ
を送出する。系切替オーダを受けたバス交絡制御装置１
００は現用系と予備系のモードの切替を行い、新たに現
用系となったプロセッサ１１に系切替割込を発生すると
ともに、新たに予備系となったプロセッサ１０にはリセ
ット信号を送出し、プロセッサバス４０と４１を分離す
る。Next, the operation when system switching occurs while the system is operating in the state shown in FIG. 1 will be described. In the active processor system, when the active processor 10 detects a temporary failure in the active hardware and switches to the backup processor system, the active processor 10 communicates with the bus confounding control device 100 via the processor bus 40. Send system switching order. Bus confounding control device 1 that received a system switching order
00 switches the mode between the active system and the standby system, generates a system switching interrupt to the processor 11 that has newly become the active system, and sends a reset signal to the processor 10 that has newly become the standby system. Separate processor buses 40 and 41.
系切替後、系切替割込を受けた現用系プロセッサ１１は
現用系としての初ｆｌｌｌｌ設定を行ったのち、現用系
メモリ２１と現用系ファイルメモリ３１により運転を継
続する。一方、リセット信号を受けた予備系プロセッサ
］Ｏは、プロセッサバス４０が現用系プロセッサバス４
１と分離されているため、予備系独自に、予備系ファイ
ルメモリ３０から予ゼ８系メインメモリ２０ヘイニシャ
ルプログラムロードを行い、初期設定を行う。After system switching, the active system processor 11 that has received the system switching interrupt performs the initial full setting as the active system, and then continues operation using the active system memory 21 and the active system file memory 31. On the other hand, the standby processor [0] that received the reset signal has a processor bus 40 that is connected to the active processor bus 4.
1, the backup system independently loads the initial program from the backup file memory 30 to the main memory 20 of the 8 system and performs initial settings.
予備系プロセッサシステムが正常に初期設定が終了すれ
ば、パス交絡制御！ｆ！ｌ装置１００を介して、予備系
メインメモリ２０と予備系ファ・ｒルメモリ３０を現用
系プロセッサ１１からアクセス可能にする。If the backup processor system completes the initial settings successfully, path confounding control is started! f! The standby main memory 20 and the standby file memory 30 are made accessible to the active processor 11 via the l device 100.
次に、第３図を用いて系切替時のバス交絡制御装置１０
０の詳細動作について説明する。バス交絡制御装置１０
０は系切替信号発生回路１０１゜現用／予備制御回路１
０２．切替パルス発生回路１ｏ３２割込信号発生回路１
０４．システムモード設定回路１０５．リセットパルス
発生回路１０６から構成され、現用系プロセッサから系
切替オーダ６が発行されると、系切替信号発生回路１０
１より現用／予備制御回路１０２へ系切替信号Ｃが送出
され、現用系が予備系に切り替る。同時に系状態信号ｄ
により他系の現用／予備制御回路１０２が予備系から現
用系に切り替る。そして、現用系／予備系の系切替が実
施されると現用／予備信号ｅにより切替パルス発生回路
１０３を起動し、現用系においては割込指示信号ｆが割
込み信号発生回路１０４に送出され、現用系プロセッサ
に対し系切替割込信号ｇを送出し、予備系においては、
切替パルス信号りによりシステムモード設定回路１０５
を分離モードに設定し、両系分離モード信号ｊが送出さ
れると現用系のプロセッサバス４１と障害系のプロセッ
サバス４０を交絡する系交絡バスａを切り離すことによ
り、現用系、予備系が独立に運用できるようになる。Next, using FIG. 3, the bus entanglement control device 10 at the time of system switching
The detailed operation of 0 will be explained. Bus entanglement control device 10
0 is system switching signal generation circuit 101゜active/standby control circuit 1
02. Switching pulse generation circuit 1o32 interrupt signal generation circuit 1
04. System mode setting circuit 105. It consists of a reset pulse generation circuit 106, and when the system switching order 6 is issued from the active processor, the system switching signal generation circuit 10
1 sends a system switching signal C to the working/standby control circuit 102, and the working system is switched to the standby system. At the same time, the system status signal d
As a result, the active/standby control circuit 102 of the other system is switched from the standby system to the active system. Then, when system switching between the active system and the standby system is performed, the switching pulse generation circuit 103 is activated by the active system/standby signal e, and in the active system, an interrupt instruction signal f is sent to the interrupt signal generating circuit 104, and the active system A system switching interrupt signal g is sent to the system processor, and in the standby system,
System mode setting circuit 105 by switching pulse signal
is set to the separation mode, and when the both systems separation mode signal j is sent, the system confounding bus a that confounds the active system processor bus 41 and the failed system processor bus 40 is separated, thereby making the active system and the standby system independent. It will be possible to operate it.
分離運転モードになると同時に障害系には、リセットパ
ルス発生回路１０６によりリセット信号ｉを発生し、予
備系のイニシャルプログラムロードを行う。At the same time as the separation operation mode is entered, the reset pulse generation circuit 106 generates a reset signal i to the faulty system, and loads the initial program of the standby system.
以上述べたように本発明によれば、プロセッサとメイン
メモリ及びファイルメモリが二重化されたシステムにお
いて、一時的な障害による系切替時に、バス交絡制御装
置により新たな現用系プロセッサバスと障害系プロセッ
サバスを分離し、新たな現用系は障害系とは独立にシス
テムの運転が継続でき、さらに、障害系は新たな現用系
に悪影響を与することなく、イニシャルプログラムロー
ザにより初期設定できるため、障害回復後は速やかに予
備系をシステムに組み込むことができる。As described above, according to the present invention, in a system in which a processor, a main memory, and a file memory are duplicated, when a system is switched due to a temporary failure, a new active processor bus and a faulty processor bus are connected by a bus confounding control device. The new active system can continue to operate independently of the faulty system, and the faulty system can be initialized using the initial program roser without adversely affecting the new active system, allowing for failure recovery. After that, you can quickly incorporate the backup system into your system.
これによりシステムの高信頼性を確保できるという効果
が期待できる。This can be expected to have the effect of ensuring high system reliability.
第１図及び第２図はいずれも本発明の実施例のブロック
構成図、第３図は本発明の実施例に使用されるバス交絡
制御装置内の系切替制御部のブロック構成図例である。
１０．１１・・・プロセッサ、２０．２１・・・メイン
メモリ、３０．３１・・・ファイルメモリ、４０．４１
・・・プロセッサバス、１００・・・バス交絡制御装置
、１０１・・・系切替信号発生回路、１０２・・・現用
／予備制御回路、１０３・・・切替パルス発生回路、１
０４・・・割込み信号発生回路、１０５・・・システム
モード設定回路、１０６・・・リセットパルス発生回路
、ａ・・・交絡バス、ｂ・・・系切替オーダ、Ｃ・・・
系切替信号、ｄ・・・系状態信号、ｅ・・・現用／予備
信号、ｆ・・・割込指示信号、ｇ・・・系切替割込信号
、ｈ・・・切替パルス信号、ｉ・・・リセット信号、ｊ
・・・両系分離ｔ １ 図
■２図FIG. 1 and FIG. 2 are both block diagrams of an embodiment of the present invention, and FIG. 3 is an example of a block diagram of a system switching control section in a bus interlacing control device used in an embodiment of the present invention. . 10.11... Processor, 20.21... Main memory, 30.31... File memory, 40.41
. . . Processor bus, 100 . . . Bus confounding control device, 101 . . . System switching signal generation circuit, 102 .
04...Interrupt signal generation circuit, 105...System mode setting circuit, 106...Reset pulse generation circuit, a...Confounding bus, b...System switching order, C...
System switching signal, d...System status signal, e...Working/standby signal, f...Interrupt instruction signal, g...System switching interrupt signal, h...Switching pulse signal, i. ...Reset signal, j
...Both systems separated t 1 Figure ■2 Figure
Claims (1)
アイルメモリをバスで接続し、バス交絡制御装置を介し
て系交絡し、通常は現用系プロセツサから前記二重化メ
インメモリに対し、同時アクセス可能で、二重化フアイ
ルメモリに対しては各々の系に対してアクセス可能なシ
ステムにおいて、上記バス交絡制御装置に現用系から予
備系の系切替手段と、系切替時に二重化バスを分離運転
可能にする手段と、系切替を要求した系に対しイニシヤ
ルプログラムロードを起動する手段を設け、現用系に障
害が発生した場合、予備系を新たに現用系とし、且つ新
たな現用系とは独立に障害系のイニシヤルプログラムロ
ードを行い、予備系の初期設定を行うことを特徴とする
系切替方式。1. Each duplexed processor, main memory, and file memory are connected via a bus, and the system is interlaced via a bus interlacing control device, and normally the active processor can access the duplexed main memory simultaneously, and the duplexed file In a system in which memory can be accessed from each system, the bus interlacing control device includes system switching means from the active system to the standby system, means for enabling separate operation of the redundant bus at the time of system switching, and system switching. If a failure occurs in the active system, the standby system becomes the new active system, and the initial program of the failed system is loaded independently from the new active system. A system switching method characterized by performing loading and initializing the standby system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61096795A JPH0831050B2 (en) | 1986-04-28 | 1986-04-28 | System switching method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61096795A JPH0831050B2 (en) | 1986-04-28 | 1986-04-28 | System switching method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62254240A true JPS62254240A (en) | 1987-11-06 |
| JPH0831050B2 JPH0831050B2 (en) | 1996-03-27 |
Family
ID=14174561
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61096795A Expired - Lifetime JPH0831050B2 (en) | 1986-04-28 | 1986-04-28 | System switching method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0831050B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0778122A (en) * | 1993-06-23 | 1995-03-20 | Koninkl Ptt Nederland Nv | Processor circuit composed of first processor, of memory and of peripheral circuit and system composed of said processor circuit and of second processor |
| JP2009217358A (en) * | 2008-03-07 | 2009-09-24 | Mitsubishi Electric Corp | Duplex programmable controller |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103208887A (en) * | 2013-03-21 | 2013-07-17 | 沈阳新城石油机械制造有限公司 | Fixing method of stator and casing of submersible linear motor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS601995A (en) * | 1983-06-17 | 1985-01-08 | Hitachi Ltd | Control system of microprocessor |
| JPS60156146A (en) * | 1984-01-25 | 1985-08-16 | Hitachi Ltd | Bus connection controlling system |
| JPS60159902A (en) * | 1984-01-31 | 1985-08-21 | Toshiba Corp | Duplex system programmable controller |
-
1986
- 1986-04-28 JP JP61096795A patent/JPH0831050B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS601995A (en) * | 1983-06-17 | 1985-01-08 | Hitachi Ltd | Control system of microprocessor |
| JPS60156146A (en) * | 1984-01-25 | 1985-08-16 | Hitachi Ltd | Bus connection controlling system |
| JPS60159902A (en) * | 1984-01-31 | 1985-08-21 | Toshiba Corp | Duplex system programmable controller |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0778122A (en) * | 1993-06-23 | 1995-03-20 | Koninkl Ptt Nederland Nv | Processor circuit composed of first processor, of memory and of peripheral circuit and system composed of said processor circuit and of second processor |
| JP2009217358A (en) * | 2008-03-07 | 2009-09-24 | Mitsubishi Electric Corp | Duplex programmable controller |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0831050B2 (en) | 1996-03-27 |
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