JPS62241355A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS62241355A
JPS62241355A JP61084154A JP8415486A JPS62241355A JP S62241355 A JPS62241355 A JP S62241355A JP 61084154 A JP61084154 A JP 61084154A JP 8415486 A JP8415486 A JP 8415486A JP S62241355 A JPS62241355 A JP S62241355A
Authority
JP
Japan
Prior art keywords
pellet
package substrate
groove
semiconductor device
paste material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61084154A
Other languages
Japanese (ja)
Inventor
Junichi Arita
順一 有田
Shunji Koike
俊二 小池
Toshiaki Ono
俊昭 小野
Yujiro Kajiwara
祐二郎 梶原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Ltd
Hitachi Microcomputer Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Microcomputer Engineering Ltd filed Critical Hitachi Ltd
Priority to JP61084154A priority Critical patent/JPS62241355A/en
Publication of JPS62241355A publication Critical patent/JPS62241355A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051—Forming additional members, e.g. dam structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To house an excess paste material in a groove and prevent the positional displacement of a pellet or the contamination, etc. of the pellet, and to improve reliability by forming the groove on the outer circumference of a pellet-fitting section on a package substrate. CONSTITUTION:A semiconductor device 1 has a package substrate 2 consisting of ceramics such as alumina, the package substrate 2 is formed in structure in which a cavity 4 in which a pellet 3 is mounted is shaped, and a groove 5 is formed along the periphery of the base of the cavity 4 to the base of the cavity 4. The package substrate 2 having such groove structure is monolithic- molded by a material such as a section, and the groove 5 can also be formed easily by previously shaping a corresponding projecting section to the section. Accordingly, an excess paste material or bubbles are housed in the groove, thus preventing the positional displacement of the pellet or the contamination of the pellet.

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、半導体装置、特にペレットが接合材によって
パッケージ基板に取付けられてなる半導体装置に利用し
て有効な技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technique that is effective for use in semiconductor devices, particularly semiconductor devices in which pellets are attached to a package substrate with a bonding material.

［従来の技術］ ペレットをペースト材で接合した半導体装置Ｓこついて
は、たとえば日経マグロウヒル社１９８４年６月１１日
発行、日経エレクトロニクス別冊「マイクロデバイセズ
１１ｍ２ＪＰ１６０〜Ｐ１６８に記載されている。その
概要は、プラスチックの基板にペレットがペースト材で
固定された構造のものである。[Prior Art] A semiconductor device S in which pellets are bonded together using a paste material is described, for example, in the Nikkei Electronics special issue "Micro Devices 11m2 JP160-P168, published by Nikkei McGraw-Hill on June 11, 1984. It has a structure in which pellets are fixed to a substrate using a paste material.

ところで本発明者は、半導体’ＡＷＩＩのパッケージ基
板へのペレットの取付けについて検討した。以下は、本
発明者によって検討された技術であり、その概要は次の
とおりである。By the way, the present inventor has studied the attachment of pellets to the package substrate of the semiconductor 'AWII. The following are the techniques studied by the present inventor, and the outline thereof is as follows.

すなわち、たとえばサーディツプ型（ＣＥ　ＲＤＩＰ）
のパッケージ構造を有する半導体装置では、パッケージ
基板への半導体ペレット（以下車にペレットという）の
接合を金−シリコン共晶法により行うことが知られてい
る。That is, for example, CERDIP
In a semiconductor device having a package structure, it is known that a semiconductor pellet (hereinafter referred to as a pellet) is bonded to a package substrate by a gold-silicon eutectic method.

ところで、上記接合技術によれば、材料である金が高価
であるため製造コストが高くなることが知られている。By the way, it is known that according to the above bonding technique, the manufacturing cost is high because gold, which is a material, is expensive.

そのため、接合材として金よりも安価な銀（Ａｇ）ある
いはアルミニウム（ＡＩ）等を添加したペースト材を用
いてパッケージ基板とペレットとの接合を行うことが考
えられる。Therefore, it is conceivable to bond the package substrate and the pellet using a paste material to which silver (Ag), aluminum (AI), or the like, which is cheaper than gold, is added as a bonding material.

［発明が解決しようとする問題点］ ところが、平坦に形成されているパッケージ基板の所定
位置にペースト材を介してペレットの接合を行った場合
、パッケージ基板面とペレットとの間のペースト材がキ
ャビティ底面にはみ出し、ペレットの位置ずれを生じる
場合がある。また、パッケージ封止の際の加熱によって
ペースト材の内部に気泡を生じ、これによりペレットの
表面もしくはリードフレーム等が汚染されるおそれのあ
ることが本発明者によって見い出された。[Problems to be Solved by the Invention] However, when a pellet is bonded to a predetermined position of a flat package substrate via a paste material, the paste material between the package substrate surface and the pellet may form a cavity. It may protrude from the bottom surface and cause the pellet to become misaligned. Furthermore, the inventors have discovered that air bubbles are generated inside the paste material due to heating during package sealing, which may contaminate the surface of the pellet or the lead frame.

本発明は、上記問題点に着目してなされたものであり、
その目的は信顛性の高いペレット接合技術を提供するこ
とにある。The present invention has been made focusing on the above problems,
The purpose is to provide a highly reliable pellet bonding technology.

さらに、本発明の他の目的は、信較性の高い半導体装置
を提供することにある。Furthermore, another object of the present invention is to provide a highly reliable semiconductor device.

本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

［問題点を解決するための手段］ 本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows.

すなわち、パッケージ基板上のペレット取付部位の外周
に溝を形成するものである。That is, a groove is formed on the outer periphery of the pellet attachment site on the package substrate.

［作用］ 上記した手段によれば、溝に余剰ペースト材を収容する
ことができ、このためにペレットの位置ずれもしくはペ
レットの汚染等を防止して信顛性の高い半導体装置の提
供が可能となるものである。[Function] According to the above-mentioned means, excess paste material can be accommodated in the groove, thereby preventing pellet misalignment or pellet contamination, thereby making it possible to provide a highly reliable semiconductor device. It is what it is.

［実施例］ 第１図は本発明の一実施例である半導体装置を示す断面
図である。[Embodiment] FIG. 1 is a sectional view showing a semiconductor device which is an embodiment of the present invention.

本実施例の半導体装置はペレットがセラミックからなる
パッケージにより気密封止されてなるいわゆるサーディ
ンブ型の半導体装置である。The semiconductor device of this embodiment is a so-called sardine type semiconductor device in which a pellet is hermetically sealed in a ceramic package.

半導体装置ｌは、アルミナ等のセラミックからなるパッ
ケージ基板２を有しており、このパッケージ基板２はペ
レット３の取付けられるキャビティ４を形成する構造と
なっており、このキャビティ４の底面にはキャビティ４
の底面終端に沿って溝５が形成されている。このような
溝構造を有するパッケージ基板２は、たとえば図示しな
い型材によって一体成形されるものであり、該溝５も予
め型材に対応する凸部を形成しておくことにより容易に
形成可能なものである。The semiconductor device 1 has a package substrate 2 made of ceramic such as alumina, and this package substrate 2 has a structure that forms a cavity 4 in which a pellet 3 is attached.
A groove 5 is formed along the end of the bottom surface. The package substrate 2 having such a groove structure is, for example, integrally molded using a mold material (not shown), and the groove 5 can also be easily formed by forming a convex portion corresponding to the mold material in advance. be.

上記溝５は、キャビティ４の底面の全終端に設けられな
くてもよい、第２図は、大容量ダイナミック型ＲＡＭの
ような細長い平面外形を持つ半導体ペレット３が取付け
られるパッケージ基板２の平面を示している。外部リー
ド８がパンケージ基板２の長辺側に配置される場合、外
部リード８とパンケージ基板２との接合面積を可能な限
り大きくさせるためには、キャビティ４のサイズを小さ
くする必要が生ずる。これに応じて、取付けられるべき
半導体ペレット３の長辺に沿う側面と、キャビティ４の
側面との距離が著しく制限される。The groove 5 does not need to be provided at the entire end of the bottom surface of the cavity 4. FIG. It shows. When the external lead 8 is arranged on the long side of the pan cage substrate 2, it is necessary to reduce the size of the cavity 4 in order to make the bonding area between the external lead 8 and the pan cage substrate 2 as large as possible. Accordingly, the distance between the side surface along the long side of the semiconductor pellet 3 to be attached and the side surface of the cavity 4 is significantly limited.

他方、パッケージ基板２の短辺に沿う部分においては、
半導体ペレット３の側面とキャビティ４の側面との距離
を比較的大きく設定できることが多い。On the other hand, in the part along the short side of the package substrate 2,
In many cases, the distance between the side surface of the semiconductor pellet 3 and the side surface of the cavity 4 can be set relatively large.

そこで、第２図のパッケージ基板２においては、溝５は
パッケージ基板２の長辺に沿う部分にのみ選択的に設け
られている。Therefore, in the package substrate 2 shown in FIG. 2, the grooves 5 are selectively provided only in the portions along the long sides of the package substrate 2.

前記キャビティ４の底面中央部分にはペレット３がペー
スト材６により取付けられている。A pellet 3 is attached to the center portion of the bottom surface of the cavity 4 using a paste material 6.

このペースト材６は、たとえばポリイミド樹脂からなる
ペースト母材に＄１１（Ａｇ）あるいはアルミニウム（
／１７りからなる金属粉末を添加したものから構成され
る。ペースト材に添加される金属はペースト材の熱伝導
性を良好にさせ、その結果として、ペレット３からパッ
ケージ基板２への放熱性を高める上で有効である。This paste material 6 is made of $11 (Ag) or aluminum (
/17 metal powder is added. The metal added to the paste material improves the thermal conductivity of the paste material, and as a result, is effective in improving heat dissipation from the pellet 3 to the package substrate 2.

また、耐熱性の面では、現在のところその詳細な理由は
明らかになっていないが、種々の実験の結果、ペースト
材６に混入される金属粉末がアルミニウムからなる場合
、耐熱性が良好であることが明らかになっている。した
がって耐熱性の点からペースト材６に混入される金属は
アルミニウムからなる方が望ましい。In addition, in terms of heat resistance, although the detailed reason is not clear at present, as a result of various experiments, heat resistance is good when the metal powder mixed in the paste material 6 is made of aluminum. It has become clear that Therefore, from the viewpoint of heat resistance, it is preferable that the metal mixed into the paste material 6 be made of aluminum.

ところで、上記ペレット３の取付けはまず、パッケージ
基板２の所定位置にペースト材６を塗布して、次に図示
しないコレット等の治具でペレット３を保持し、それを
前記パッケージ基板２のキャビティ底面の所定位置に該
ペレット３を押圧することによって行われる。このペレ
ット３の押圧の際に、予め塗布されたペースト材６がペ
レット３の裏面からはみ出すことが考えられるが、本実
施例によれば、前述のようにペレット３の取付部位の周
囲、すなわちキャビティ４の底面周囲に沿って溝５が形
成されているため、はみ出した余剰ペースト材６ａは該
溝５に収容される。したがって、過剰なペースト材６に
よってペレット３がキャビティ４の底面所定位置から浮
き上がって位置ずれを生じることを防止できる。By the way, to attach the pellet 3, first apply the paste material 6 to a predetermined position on the package substrate 2, then hold the pellet 3 with a jig such as a collet (not shown), and place it on the bottom surface of the cavity of the package substrate 2. This is done by pressing the pellet 3 into a predetermined position. It is conceivable that the paste material 6 applied in advance may protrude from the back surface of the pellet 3 when the pellet 3 is pressed, but according to this embodiment, as described above, the paste material 6 is Since a groove 5 is formed along the periphery of the bottom surface of 4, the surplus paste material 6a that protrudes is accommodated in the groove 5. Therefore, it is possible to prevent the pellets 3 from being lifted up from a predetermined position on the bottom surface of the cavity 4 due to excessive paste material 6 and being misaligned.

パンケージ基板２のキャビティ底面の所定位置にペレッ
ト３を押圧した後、パンケージ基板２を加熱することに
よってペースト材６を硬化し、ペレット３の取付けを完
了するが、この際にキャビティ４に露出したペースト材
６が急加熱のために沸騰して気泡を生じる場合がある。After pressing the pellet 3 into a predetermined position on the bottom of the cavity of the pan cage substrate 2, the paste material 6 is hardened by heating the pan cage substrate 2, and the installation of the pellet 3 is completed, but at this time, the paste exposed in the cavity 4 is The material 6 may boil due to rapid heating and produce bubbles.

しかし、本実施例によれば、ペレット３の裏面からはみ
出したペースト材６は溝５内に収容されることになる。However, according to this embodiment, the paste material 6 protruding from the back surface of the pellet 3 is accommodated in the groove 5.

したがって、気泡の発生も溝５内で生じることになる。Therefore, bubbles will also occur within the groove 5.

そのため、該気泡がペレット３の表面あるいはインナー
リード８ａの表面に達して、キャビティ４の内部を汚染
することを防止できる。Therefore, the air bubbles can be prevented from reaching the surface of the pellet 3 or the surface of the inner lead 8a and contaminating the inside of the cavity 4.

第１図において、前記パッケージ基板２のキャビティ４
の周囲には低融点ガラス７によってり一ド８が取付けら
れており、該リード８のキ中ビティ４内に封止される部
分は実質的にインナーリード８ａを構成している。この
インナーリード８ａとペレット３の表面に形成されたバ
ッド３ａとはアルミニウム（ＡＩ）等のワイヤ９により
電気的導通が達成されている。このワイヤ９の張設は、
たとえば以下のように行われるものである。すなわち、
ワイヤ９の一端をボンディングツールであるウェッジ（
図示せず）と前記バッド３ａとで挟むようにして超音波
振動を印加しながら押圧することによってワイヤ９の一
端をバッド３ａに接合して第一ボンディングを行う０次
に、ウェッジの先端からワイヤ９を繰り出しながらワイ
ヤ９がループを描くように張設し、さらに、上記と同様
にワイヤ９の他端側をウェッジとインナーリード８ａと
で挟むようにして超音波振動を印加することによってワ
イヤ９の他端側をインナーリード８ａに接合し、第二ボ
ンディングを行う、最後に、ワイヤ９の余線部分を切断
してワイヤボンディングを完了するものである。In FIG. 1, the cavity 4 of the package substrate 2
A lead 8 is attached around the lead 8 using a low melting point glass 7, and the portion of the lead 8 sealed within the cutout 4 substantially constitutes an inner lead 8a. Electrical continuity between the inner lead 8a and the pad 3a formed on the surface of the pellet 3 is achieved by a wire 9 made of aluminum (AI) or the like. The tensioning of this wire 9 is as follows:
For example, this is done as follows. That is,
Connect one end of the wire 9 to a wedge (
One end of the wire 9 is bonded to the pad 3a by pressing the wire 9 between the pad 3a (not shown) and the pad 3a while applying ultrasonic vibration.Next, the wire 9 is inserted from the tip of the wedge. While being fed out, the wire 9 is stretched so as to draw a loop, and then the other end of the wire 9 is sandwiched between the wedge and the inner lead 8a in the same way as described above, and ultrasonic vibration is applied to the other end of the wire 9. is bonded to the inner lead 8a and second bonding is performed.Finally, the extra line portion of the wire 9 is cut to complete the wire bonding.

一方、前記パッケージ基板２の上面は低融点ガラス１０
によって取付けられた断面コ字状のキャップ１１によっ
て覆われている。このキャップｌｌの取付けは以下のよ
うにして行われる。すなわち、パッケージ基板２上の所
定位置にキャップ１１を当接させて封止炉を通過させる
ことによってキャップ１１の当接部の低融点ガラスＩＯ
が溶融してキャップ１１がパッケージ基板２に接合され
るのである。On the other hand, the upper surface of the package substrate 2 is covered with a low melting point glass 10.
It is covered with a cap 11 having a U-shaped cross section and attached to the cap 11. Attachment of this cap 11 is carried out as follows. That is, by bringing the cap 11 into contact with a predetermined position on the package substrate 2 and passing it through a sealing furnace, the low melting point glass IO at the contact portion of the cap 11 is removed.
is melted and the cap 11 is bonded to the package substrate 2.

このように、本実施例によれば以下の効果を得ることが
できる。As described above, according to this embodiment, the following effects can be obtained.

（ｌ）、パッケージ基板のキャビティ底面のペレット取
付部位の周囲に溝を形成することにより、ペレットの裏
面からはみ出した余剰ペースト材が上記溝に収容される
ため、余剰ペースト材が原因となるペレットの浮き、さ
らにこれにともなうペレットの位置ずれを効果的に防止
することができる。(l) By forming a groove around the pellet mounting area on the bottom of the cavity of the package substrate, excess paste material protruding from the back surface of the pellet is accommodated in the groove. It is possible to effectively prevent floating and the resulting displacement of the pellets.

（２）、上記（１）により、ペースト材が沸騰した際に
生じる気泡の上昇を溝によって防止することができるた
め、気泡の発生によるペレット表面あるいはインナーリ
ード表面の汚染を防止することができる。(2) According to (1) above, the grooves can prevent the rise of bubbles generated when the paste material boils, so that contamination of the pellet surface or inner lead surface due to the generation of bubbles can be prevented.

（３）、上記（１）〜（２）により、さらにペレットの
取付位置を正確に維持することができ、キャビティ内部
の汚染を防止することができるため、ワイヤボンディン
グにおける接合効率を向上させることができ、信頬性の
高い半導体装置を提供することができる。(3) Due to (1) and (2) above, it is possible to maintain the pellet mounting position accurately and prevent contamination inside the cavity, thereby improving the bonding efficiency in wire bonding. Therefore, it is possible to provide a highly reliable semiconductor device.

以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。たとえば、ワイヤの張設
に際しては、超音波方式による接合法を例に説明したが
、これに限らず熱圧着方式によるもの等であってもよい
。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the case of tensioning the wire, although an ultrasonic bonding method has been described as an example, the present invention is not limited to this, and a thermocompression bonding method may also be used.

さらに、ペレットの表面にα線等の電子線対策としてポ
リイミド樹脂等を被着したものであってもよい。Furthermore, a polyimide resin or the like may be coated on the surface of the pellet as a countermeasure against electron beams such as alpha rays.

アルミニウム混入のポリイミド樹脂からなるペースト材
を使用するペレット付は技術は、溝５が設けられないパ
ッケージ基板にも適用可能である。The pellet attaching technique using a paste material made of aluminum-containing polyimide resin can also be applied to a package substrate in which the groove 5 is not provided.

以上の説明では主として本発明者によってなされた発明
をその利用分野である、サーディツプ型の半導体装置に
適用した場合について説明したが、これに限定されるも
のではなく、たとえばフラットパッケージ型（ＰＰＰ）
、あるいはビングリッドアレイ型（ＰＧＡ）等、ペレッ
トをペーストでパッケージ基板に固定する構造の半導体
装置であれば如何なるパッケージ型のものに適用しても
有効な技術である。In the above explanation, the invention made by the present inventor is mainly applied to a cerdip type semiconductor device, which is the field of use thereof, but the invention is not limited to this, and for example, a flat package type (PPP)
It is an effective technique that can be applied to any type of package, such as a bin grid array type (PGA) or a semiconductor device having a structure in which pellets are fixed to a package substrate with paste.

［発明の効果］ 本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記の通りである
。[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly described below.

すなわち、パッケージ基板上のペレット取付部位の外周
に溝を形成することにより、余剰ペースト材もしくは気
泡を該溝に収容して、ペレットの位置ずれもしくはペレ
ットの汚染を防止できるため、信頼性の高い半導体装置
が提供できるものである。In other words, by forming a groove on the outer periphery of the pellet mounting area on the package substrate, surplus paste material or air bubbles can be accommodated in the groove to prevent pellet misalignment or pellet contamination. This is what the equipment can provide.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例である半導体装置を３・　・
　・ペレット、３ａ・・　・パッド、４・・　・キャビ
ティ、５・・・溝、６・・・ペースト材、６ａ・・・余
剰ペースト材、７・・・低融点ガラス、８・・・リード
、８ａ・・・インナーリード、９・・・ワイヤ、１０・
・・低融点ガラス、１１・・・キャップ。 一一＼、 代理人　弁理士　小　川　勝　男 第　　１　　図 ３−　へ０し・・／Ｙ ／　／　−フｒマ・ソー／９FIG. 1 shows a semiconductor device according to an embodiment of the present invention.
- Pellet, 3a... - Pad, 4... - Cavity, 5... Groove, 6... Paste material, 6a... Surplus paste material, 7... Low melting point glass, 8... Lead, 8a... Inner lead, 9... Wire, 10.
...Low melting point glass, 11...Cap. 11\, Agent Patent Attorney Katsuo Ogawa No. 1 Figure 3 - 0.../Y//-Free Market So/9

Claims (1)

【特許請求の範囲】 １、半導体ペレットがパッケージ基板上にペースト材を
出発材料とする接合材を介して接合されている半導体装
置であって、前記パッケージ基板上のペレット取付部位
の外周に溝が形成されてなることを特徴とする半導体装
置。 ２、パッケージ基板がセラミックからなり、かつ上記接
合材に銀またはアルミニウムが添加されてなる樹脂から
なることを特徴とする特許請求の範囲第１項記載の半導
体装置。 ３、サーディップ型のパッケージ形状を有することを特
徴とする特許請求の範囲第１項または第２項記載の半導
体装置。[Scope of Claims] 1. A semiconductor device in which a semiconductor pellet is bonded onto a package substrate via a bonding material starting from a paste material, wherein a groove is formed on the outer periphery of the pellet mounting portion on the package substrate. A semiconductor device characterized by being formed. 2. The semiconductor device according to claim 1, wherein the package substrate is made of ceramic and made of a resin made by adding silver or aluminum to the bonding material. 3. The semiconductor device according to claim 1 or 2, which has a cerdip type package shape.
JP61084154A 1986-04-14 1986-04-14 Semiconductor device Pending JPS62241355A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61084154A JPS62241355A (en) 1986-04-14 1986-04-14 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61084154A JPS62241355A (en) 1986-04-14 1986-04-14 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS62241355A true JPS62241355A (en) 1987-10-22

Family

ID=13822586

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61084154A Pending JPS62241355A (en) 1986-04-14 1986-04-14 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS62241355A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0215728U (en) * 1988-07-13 1990-01-31
EP0650658A4 (en) * 1992-07-13 1996-03-13 Olin Corp Electronic package having controlled epoxy flow.
WO2004074168A3 (en) * 2003-02-20 2005-04-14 Analog Devices Inc Packaged microchip with thermal stress relief
US6946742B2 (en) 2002-12-19 2005-09-20 Analog Devices, Inc. Packaged microchip with isolator having selected modulus of elasticity
US7166911B2 (en) 2002-09-04 2007-01-23 Analog Devices, Inc. Packaged microchip with premolded-type package
JP2012195323A (en) * 2011-03-14 2012-10-11 Omron Corp Sensor package
US9676614B2 (en) 2013-02-01 2017-06-13 Analog Devices, Inc. MEMS device with stress relief structures
US10167189B2 (en) 2014-09-30 2019-01-01 Analog Devices, Inc. Stress isolation platform for MEMS devices
US11981560B2 (en) 2020-06-09 2024-05-14 Analog Devices, Inc. Stress-isolated MEMS device comprising substrate having cavity and method of manufacture

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0215728U (en) * 1988-07-13 1990-01-31
EP0650658A4 (en) * 1992-07-13 1996-03-13 Olin Corp Electronic package having controlled epoxy flow.
US7166911B2 (en) 2002-09-04 2007-01-23 Analog Devices, Inc. Packaged microchip with premolded-type package
US6946742B2 (en) 2002-12-19 2005-09-20 Analog Devices, Inc. Packaged microchip with isolator having selected modulus of elasticity
WO2004074168A3 (en) * 2003-02-20 2005-04-14 Analog Devices Inc Packaged microchip with thermal stress relief
JP2012195323A (en) * 2011-03-14 2012-10-11 Omron Corp Sensor package
US9676614B2 (en) 2013-02-01 2017-06-13 Analog Devices, Inc. MEMS device with stress relief structures
US10167189B2 (en) 2014-09-30 2019-01-01 Analog Devices, Inc. Stress isolation platform for MEMS devices
US11981560B2 (en) 2020-06-09 2024-05-14 Analog Devices, Inc. Stress-isolated MEMS device comprising substrate having cavity and method of manufacture

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