JPS62238691A - Ceramic circuit board with built-in resistance - Google Patents
Ceramic circuit board with built-in resistanceInfo
- Publication number
- JPS62238691A JPS62238691A JP61082865A JP8286586A JPS62238691A JP S62238691 A JPS62238691 A JP S62238691A JP 61082865 A JP61082865 A JP 61082865A JP 8286586 A JP8286586 A JP 8286586A JP S62238691 A JPS62238691 A JP S62238691A
- Authority
- JP
- Japan
- Prior art keywords
- inner layer
- paste
- resistance
- resistor
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 title claims description 19
- 238000013035 low temperature curing Methods 0.000 claims description 2
- 238000010304 firing Methods 0.000 claims 1
- 239000004020 conductor Substances 0.000 description 26
- 239000012212 insulator Substances 0.000 description 18
- 239000000758 substrate Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 6
- 238000009966 trimming Methods 0.000 description 6
- 239000011521 glass Substances 0.000 description 5
- 238000002844 melting Methods 0.000 description 5
- 230000008018 melting Effects 0.000 description 5
- 238000001723 curing Methods 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
本発明はハイブリッドＩＣ分野で使用される抵抗内蔵型
セラミック回路基板だ関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a ceramic circuit board with a built-in resistor used in the field of hybrid ICs.
従来の技術
第２図は抵抗内蔵型セラミック回路基板の一般的な断面
図である。第２図において、１２はセラミック基板、１
３は内層導体、１４は内層抵抗、１５は表面導体、１６
は内層導体１３と表面導体１５を連結するビア導体、１
７は表面抵抗、１８は内層絶縁体、１９は表面カバーコ
ート用絶縁体、２０はチップ部品である。以下従来例に
よる抵抗内蔵型セラミック回路基板の形成法を順を追っ
て説明する。BACKGROUND OF THE INVENTION FIG. 2 is a general cross-sectional view of a ceramic circuit board with a built-in resistor. In FIG. 2, 12 is a ceramic substrate;
3 is an inner layer conductor, 14 is an inner layer resistor, 15 is a surface conductor, 16
1 is a via conductor connecting the inner layer conductor 13 and the surface conductor 15;
7 is a surface resistance, 18 is an inner layer insulator, 19 is an insulator for surface cover coating, and 20 is a chip component. A method of forming a conventional ceramic circuit board with a built-in resistor will be explained step by step below.
■セラミック基板１２上に導体用無機ペースト（例えば
Ａｇ−Ｐｄペースト）をスクリーン印刷し、その後、乾
燥、焼成（約８５０℃）し、内層導体１３を形成する。(2) An inorganic conductor paste (for example, Ag-Pd paste) is screen printed on the ceramic substrate 12, and then dried and fired (about 850° C.) to form the inner layer conductor 13.
■抵抗用無機ペースト （例えば進Ｏｔペースト）をス
クリーン印刷し、その後、乾燥、焼成（約８５０℃）、
トリミングを行い、内層抵抗１４を形成する。■Screen print an inorganic paste for resistance (for example, Susumu Ot paste), then dry and bake (approximately 850℃).
Trimming is performed to form the inner layer resistor 14.
■内層絶縁体用ペースト （例えば高融点ガラスペース
ト）をスクリーン印刷し、その後、乾燥、焼成（約８５
０℃）し、内層絶縁体１８を形成する。■Screen print paste for inner layer insulator (e.g. high melting point glass paste), then dry and bake (approximately 85%
0° C.) to form the inner layer insulator 18.
■導体用ペースト （■で使用したペーストに同じ）を
スクリーン印刷し、その後乾燥、焼成（約８５０℃）し
、表面導体１５を形成する。(2) A conductor paste (same as the paste used in (2)) is screen printed, then dried and fired (about 850°C) to form the surface conductor 15.
■抵抗用ペースト （■で使用したペーストに同じ）を
スクリーン印刷し、その後乾燥、焼成（約８５０℃）、
トリミングを行い、表面抵抗１７を形成する。■Screen print the resistor paste (same as the paste used in ■), then dry and bake (approximately 850℃).
Trimming is performed to form a surface resistor 17.
０表面カバーコート用ペースト （例えば低融点ガラス
ペースト）をスクリーン印刷し、その後乾燥、焼成（約
５２０℃）し、表面カバーコート絶縁体１９を形成する
。A surface cover coat insulator 19 is formed by screen printing a surface cover coat paste (for example, a low melting point glass paste), followed by drying and baking (about 520° C.).
■チップ部品２０をリフローはんだ接合し、抵抗内蔵型
セラミック回路基板が完成する。■The chip component 20 is reflow soldered and a ceramic circuit board with a built-in resistor is completed.
発明が解決しようとする問題点
しかしながら、この方法により形成された回路基板では
、内層抵抗１４が数回高温（８００〜９００℃）で再焼
成されるので、抵抗値が±２０〜３０％の範囲でバラツ
キ、抵抗値の精度を要求される回路には使えないという
問題があった。Problems to be Solved by the Invention However, in the circuit board formed by this method, the inner layer resistor 14 is refired several times at high temperature (800 to 900°C), so the resistance value is within the range of ±20 to 30%. There was a problem that it could not be used in circuits that required precision in resistance values due to variations in resistance values.
本発明はこのような従来の問題を解決し、精度の良い内
層抵抗をもつ抵抗内蔵型セラミック回路基板を提供する
ことを目的とするものである。It is an object of the present invention to solve these conventional problems and provide a ceramic circuit board with a built-in resistor having a highly accurate inner layer resistance.
問題点を解決するための手段
本発明は上記目的を達成するために、内層抵抗は約８５
０℃高温で処理する無機ペーストを用いて形成し、内層
絶縁体は約５２０℃で処理する無機ペースト又は約１５
０℃で処理する有機ペーストで形成し、しかる後、表面
配線、表面抵抗を約１５０ ℃の低温で処理できる有機
ペーストで形成して抵抗内蔵型セラミック回路基板を完
成するようにしたものである。Means for Solving the Problems In order to achieve the above object, the present invention provides an inner layer resistance of about 85
The inner layer insulator is formed using an inorganic paste processed at a high temperature of about 520°C or an inorganic paste processed at a high temperature of about 15°C.
It is formed using an organic paste that can be processed at 0°C, and then surface wiring and surface resistance are formed using an organic paste that can be processed at a low temperature of about 150°C to complete a resistor-embedded ceramic circuit board.
作用
したがって、本発明によれば内層抵抗の形成温度と、内
層絶縁体の形成温度および表面抵抗の形成温度に差をも
たせることによって、内層絶縁体および表面抵抗を形成
する際に内層抵抗の値を変化させることがほとんどなく
なる。従って精度の高い内層抵抗を作成できる。Therefore, according to the present invention, the value of the inner layer resistance can be adjusted when forming the inner layer insulator and surface resistor by creating a difference between the forming temperature of the inner layer resistor, the forming temperature of the inner layer insulator, and the forming temperature of the surface resistor. There will be little to change. Therefore, highly accurate inner layer resistance can be created.
実施例 第１図は本発明の一実施例の構成を示す断面図である。Example FIG. 1 is a sectional view showing the configuration of an embodiment of the present invention.
第１図において、１はセラミック基板、２は内層導体、
３は内層抵抗、４は表面配線導体、５は表面抵抗、６は
チップ部品をはんだ付けする電極、７は表面抵抗５と表
面配線導体４を連結する電極、８は内層導体２と表面抵
抗５又は表面配線導体４を連結するビア導体、９は内層
絶縁体、ｌＯは表面カバーコート用絶縁体、１１はチッ
プ部品である。以下本発明による抵抗内蔵型セラミック
回路基板の形成法について説明する。In FIG. 1, 1 is a ceramic substrate, 2 is an inner layer conductor,
3 is an inner layer resistance, 4 is a surface wiring conductor, 5 is a surface resistance, 6 is an electrode for soldering chip components, 7 is an electrode connecting the surface resistance 5 and the surface wiring conductor 4, 8 is an inner layer conductor 2 and the surface resistance 5 Alternatively, 9 is an inner layer insulator, 10 is an insulator for surface cover coating, and 11 is a chip component. A method for forming a resistor built-in ceramic circuit board according to the present invention will be described below.
（１）セラミック基板１上に導体用無機ペースト（例え
ばＡｇ−Ｐｄペースト）をスクリーン印刷し、その後乾
燥、焼成（約８５０℃）し、内層導体２を形成する。(1) An inorganic conductor paste (for example, Ag-Pd paste) is screen printed on the ceramic substrate 1, and then dried and fired (about 850° C.) to form the inner layer conductor 2.
（２）抵抗用無機ペースト （例えばＲｕｂｓペースト
）をスクリーン印刷し、その後乾燥、焼成（約８５０℃
）、トリミングを行い内層抵抗３を形成する。(2) Screen print an inorganic paste for resistance (e.g. Rubs paste), then dry and bake (approximately 850℃)
), and trimming is performed to form the inner layer resistor 3.
（３）内層絶縁体用ペースト （例えば低融点ガラスペ
ースト）をスクリーン印刷し、その後乾燥、焼成（約５
２０℃）し、内層絶縁体９を形成する。この場合ペース
トとして、低温（約１５０℃）硬化型の有機ペースト又
は紫外線硬化型の有機ペーストを用いてもよい。(3) Screen print paste for inner layer insulator (e.g. low melting point glass paste), then dry and bake (approximately 5
20° C.) to form the inner layer insulator 9. In this case, as the paste, a low temperature (approximately 150° C.) curing type organic paste or an ultraviolet curing type organic paste may be used.
（４）表面配線導体用有機ペースト （例えば導電性銅
ペースト）をスクリーン印刷し、低温（約１５０℃）硬
化し、表面配線導体４を形成する。(4) An organic paste for surface wiring conductors (for example, conductive copper paste) is screen printed and cured at a low temperature (about 150° C.) to form surface wiring conductors 4.
（５）表面抵抗用有機ペースト （例えばカーボンペー
スト）をスクリーン印刷し、低温（約１５０℃）硬化し
、トリミングを行い表面抵抗５を形成する。(5) An organic paste for surface resistance (for example, carbon paste) is screen printed, cured at a low temperature (approximately 150° C.), and trimmed to form the surface resistance 5.
（６）チップ部品をはんだ付けする電極６、表面抵抗５
と表面配線導体４を結ぶ電極７および内層導体２と表面
抵抗５又は表面配線導体４を結ぶピア導体８を形成する
為、導電性有機ペースト （例えば銀ペースト）をスク
リーン印刷し、低温（１５０℃）硬化する。(6) Electrode 6 for soldering chip components, surface resistance 5
In order to form the electrode 7 that connects the surface wiring conductor 4 and the inner layer conductor 2 and the surface resistor 5 or the peer conductor 8 that connects the surface wiring conductor 4, a conductive organic paste (for example, silver paste) is screen printed and heated at a low temperature (150°C). ) to harden.
（７）表面カバコート用有機ペースト （例えば紫外線
硬化型ペースト、低温硬化型ペースト）をスクリーン印
刷し、紫外線又は低温（約１５０℃）で硬化し、表面カ
バーコート用絶縁体１０を形成する。(7) Screen print an organic paste for surface cover coat (for example, ultraviolet curing paste, low temperature curing paste) and cure with ultraviolet rays or low temperature (about 150° C.) to form insulator 10 for surface cover coat.
（８）チップ部品１１をリフローはんだ接合し、抵抗内
蔵型セラミック回路基板が完成する。(8) The chip components 11 are joined by reflow soldering, and a ceramic circuit board with a built-in resistor is completed.
本形成法による内層抵抗の精度を示すと、内層絶縁体９
に低融点ガラスを用いた時は抵抗は若干変化し、精度は
±５％以内、有機ペーストを用いた時は抵抗の変化はな
く、トリミング精度である±１チ以内に入る。又内層絶
縁体に低融点ガラスを用いた時に、内層抵抗のトリミン
グを内層絶縁体の形成後実施すれば、その後の抵抗の変
化はなくトリミング精度である±１％以内に入る。但し
この場合はトリミングされた切り溝が露出するので表面
配線導体を形成する時に、抵抗体を逃げて形成しなけれ
ばならないという制約が生まれる。To show the accuracy of the inner layer resistance by this formation method, the inner layer insulator 9
When low melting point glass is used, the resistance changes slightly and the accuracy is within ±5%, while when organic paste is used, the resistance does not change and is within ±1 inch, which is the trimming accuracy. Furthermore, when low melting point glass is used for the inner layer insulator, if trimming of the inner layer resistance is performed after the inner layer insulator is formed, there will be no change in resistance after that and the trimming accuracy will be within ±1%. However, in this case, since the trimmed grooves are exposed, there is a restriction that when forming the surface wiring conductor, the resistor must be formed in a way that escapes the resistor.
本実施例では二層配線回路について説明したが、セラミ
ック基板の他の面に同様の回路を形成し、基板の両面を
一般的なスルーホール形成法で作られたスルーホールで
連結すれば、基板の両面に内層抵抗をもった四層配線の
回路基板もできる。In this example, a two-layer wiring circuit was explained, but if a similar circuit is formed on the other side of the ceramic substrate and both sides of the substrate are connected with through holes made by a general through hole forming method, the substrate can be It is also possible to create a four-layer wiring circuit board with internal layer resistance on both sides.
発明の効果
本発明は上記実施例より明らかなように、内層抵抗の形
成温度とその他の部分例えば表面配線導体、表面抵抗等
の形成温度との間にかなりの温度差（約３３０℃、又は
約７００℃）を設けて内層抵抗および表面抵抗を形成し
たものであり、内層抵抗の値がその後の工程で加えられ
る熱の影響をほとんど受けないという利点を有し、各種
の回路に自由に適用しうる抵抗内蔵型セラミック回路基
板を提供できる。Effects of the Invention As is clear from the above embodiments, the present invention has a considerable temperature difference (approximately 330°C, or approximately 700℃) to form the inner layer resistance and surface resistance, and has the advantage that the value of the inner layer resistance is almost unaffected by the heat added in subsequent processes, and can be freely applied to various circuits. A ceramic circuit board with a built-in resistor can be provided.
第１図は本発明の一実施例における抵抗内蔵型セラミッ
ク回路基板の断面図、第２図は従来の抵抗内蔵型セラミ
ック回路基板の断面図である。
１．１２・・・セラミック基板、２．１３・・・内層導
体、３．１４・・・内層抵抗、４・・・表面配線導体、
５．１７・・・表面抵抗、６．７・・・電極、８．１６
・・・ビア導体、９．１８・・・内層絶縁体、１０．１
９・・・表面カバーコート用絶縁体、１１．２０・・・
チップ部品、１５・・・表面導体。FIG. 1 is a cross-sectional view of a ceramic circuit board with a built-in resistor according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a conventional ceramic circuit board with a built-in resistor. 1.12... Ceramic substrate, 2.13... Inner layer conductor, 3.14... Inner layer resistance, 4... Surface wiring conductor,
5.17...Surface resistance, 6.7...Electrode, 8.16
... Via conductor, 9.18 ... Inner layer insulator, 10.1
9...Insulator for surface cover coat, 11.20...
Chip parts, 15...Surface conductor.
Claims (1)
を形成し、基板表面配線面に低温硬化型有機ペーストに
より抵抗を形成した抵抗内蔵型セラミック回路基板。A ceramic circuit board with a built-in resistor, in which a resistor is formed on the inner wiring surface of the board using a high-temperature firing inorganic paste, and a resistor is formed on the wiring surface of the board using a low-temperature curing organic paste.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61082865A JPS62238691A (en) | 1986-04-10 | 1986-04-10 | Ceramic circuit board with built-in resistance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61082865A JPS62238691A (en) | 1986-04-10 | 1986-04-10 | Ceramic circuit board with built-in resistance |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62238691A true JPS62238691A (en) | 1987-10-19 |
Family
ID=13786219
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61082865A Pending JPS62238691A (en) | 1986-04-10 | 1986-04-10 | Ceramic circuit board with built-in resistance |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62238691A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5374903A (en) * | 1976-12-13 | 1978-07-03 | Nippon Steel Corp | Device for marking type during movement |
-
1986
- 1986-04-10 JP JP61082865A patent/JPS62238691A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5374903A (en) * | 1976-12-13 | 1978-07-03 | Nippon Steel Corp | Device for marking type during movement |
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