JPS62237744A - Cassette containing ic substrate - Google Patents
Cassette containing ic substrateInfo
- Publication number
- JPS62237744A JPS62237744A JP8145986A JP8145986A JPS62237744A JP S62237744 A JPS62237744 A JP S62237744A JP 8145986 A JP8145986 A JP 8145986A JP 8145986 A JP8145986 A JP 8145986A JP S62237744 A JPS62237744 A JP S62237744A
- Authority
- JP
- Japan
- Prior art keywords
- cassette
- groove
- wafer
- angle
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title abstract description 6
- 230000002093 peripheral effect Effects 0.000 claims abstract description 14
- 235000012431 wafers Nutrition 0.000 description 23
- 230000000694 effects Effects 0.000 description 2
- 102100027340 Slit homolog 2 protein Human genes 0.000 description 1
- 101710133576 Slit homolog 2 protein Proteins 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Packaging Frangible Articles (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、ＩＣ基板を収納するカセットに関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cassette for storing an IC board.
従来のＩＣ基板収納用カセットとしては、第２図に示す
ウェハ収納用カセツＦがある。As a conventional IC board storage cassette, there is a wafer storage cassette F shown in FIG.
図において１はウェハ収納用カセット、２はこのカセッ
ト１に設けられた互に向かい合う複数対の断面がＶ字形
のＶ形溝、３は向かい合う一対のＶ形溝２に両側端部に
おいて挿入されたウェハである。In the figure, 1 is a wafer storage cassette, 2 is a plurality of mutually facing V-shaped grooves provided in the cassette 1, each having a V-shaped cross section, and 3 is a cassette inserted into a pair of opposing V-shaped grooves 2 at both ends thereof. It's a wafer.
ところが、このような、従来のウェハ収納用力七ツ）
Ｉ ＶＣあっては、■形溝２の角度θが６度３６分と可
成りの鋭角になっているため、Ｖ形溝２の傾斜面とウェ
ハ３の周表面との接触面積がその溝２の深さ方向の幅Ｗ
で約３Ｍと大きくなり、ウェハ３の周表面にキズが付き
、製品としての歩留まりが悪くなることがあった。また
、カセット１の変形やウェハ３の反りが発生した場合に
は、スリット２とウェハ３の周表面との接触面積がさら
に大きくなり、（上記１隔Ｗでいえば約８．５鯖にもな
り）これが原因で製品としての歩留まりがさらに悪化す
ることがあった。However, the conventional wafer storage capacity (7)
In the case of IVC, the angle θ of the ■-shaped groove 2 is a fairly acute angle of 6 degrees and 36 minutes, so the contact area between the inclined surface of the V-shaped groove 2 and the circumferential surface of the wafer 3 is smaller than that of the groove 2. Width W in the depth direction of
The size of the wafer 3 was about 3M, which caused scratches on the peripheral surface of the wafer 3, resulting in poor product yield. Furthermore, if the cassette 1 is deformed or the wafer 3 is warped, the contact area between the slit 2 and the circumferential surface of the wafer 3 becomes even larger (approximately 8.5 mm in terms of 1 interval W). ) This caused the yield of the product to deteriorate even further.
この発明ｒユ、上記のような問題点を解決するためにな
されたもので、ＩＣ基板の製品としての歩留まりを向上
させることのできるＩＣ基板収納用カセットヲ得ること
を目的とする。This invention was made to solve the above-mentioned problems, and an object of the present invention is to provide a cassette for storing an IC board that can improve the yield of IC board products.
この発明に係るＩＣ基板用収納用カセットは、ＩＣ基板
がその周端部において挿入される互に向かい合う複数対
のＶ形溝を有するカセットにおいて、前記Ｖ形溝の角度
を８度以上にしたものである。The cassette for storing IC boards according to the present invention is a cassette having a plurality of pairs of V-shaped grooves facing each other into which the IC boards are inserted at the peripheral edge thereof, and in which the angle of the V-shaped grooves is 8 degrees or more. It is.
この発明におけるＶ形溝は、その角度？８変以上にして
従来より大きくしたので、このＶ形溝に収納したＩＣ基
板の表面とＶ形溝の傾斜面とのなす角度は大きくなる。What is the angle of the V-shaped groove in this invention? Since it is made larger than the conventional one by making it more than 8, the angle formed between the surface of the IC board housed in this V-shaped groove and the inclined surface of the V-shaped groove becomes large.
このため、ｘｃ３板の周１部表面と前記傾斜面との接触
面積は小さくなり、ＩＣ基板の周端部表面にキズが付く
おそれは殆んどなくなる。また、カセットの変形やＩＣ
基板の度りが発生した場合でも、上記接触面積は左程大
きくならないので、ＩＣ基板の周端部表面におけるキズ
も最小限に抑えられる。Therefore, the contact area between the peripheral surface of the xc3 plate and the inclined surface becomes small, and there is almost no possibility that the peripheral end surface of the IC board will be scratched. In addition, cassette deformation and IC
Even if the board warps, the contact area does not become as large as shown in the left, so that scratches on the surface of the peripheral edge of the IC board can be minimized.
以下、この発明の一実施例を図につい゛Ｃ説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図において、１１はウェハ収納用カセット、１２に
このカセット１１シて設けられ互に向かい合う複数対の
Ｖ形溝、１３は向かい合う一対のＶ形溝１２ごとに周端
部において挿入されだウェハである。上記Ｖ形溝１２の
角度θは８度以上にしである。ここにいう■形溝１２は
、向かい合う２つの傾斜面の断面形状が実質的にＶ字形
をなしている溝をいう。また、上記角度θは、向がい合
う２つの傾斜面をこれに垂直な面で切断したとき前記２
つの傾斜面がなす角度である。In FIG. 1, reference numeral 11 denotes a cassette for storing wafers, 12 a plurality of pairs of V-shaped grooves facing each other provided in the cassette 11, and 13 a wafer inserted into each pair of V-shaped grooves 12 at the peripheral end thereof. It is. The angle θ of the V-shaped groove 12 is 8 degrees or more. The ■-shaped groove 12 herein refers to a groove in which the cross-sectional shape of two opposing inclined surfaces is substantially V-shaped. In addition, the above angle θ is the above 2 when two opposing inclined surfaces are cut by a plane perpendicular to these.
It is the angle formed by two inclined planes.
このように、実施例のカセット１１は、そのＶ形溝１２
の角度θが８度以上となっているので、収納さ、またウ
ェハ１３の表面とＶ形溝１２の傾斜面とのなす角度は、
従来に比べて大きくなる。このため、ウェハ１３の周端
部表面と前記傾斜面との接触面積は小さくなり、Ｖ形溝
１２の深さ方向の幡Ｗで言えば約１闘と小さくなる。し
たがって、ウェハ１３の周端部表面にキズが付くおそれ
は殆んどなくなる。In this way, the cassette 11 of the embodiment has its V-shaped groove 12
Since the angle θ is 8 degrees or more, the angle between the surface of the wafer 13 and the inclined surface of the V-shaped groove 12 is
It will be larger than before. Therefore, the contact area between the peripheral end surface of the wafer 13 and the inclined surface becomes small, and the height W of the V-shaped groove 12 in the depth direction becomes as small as about 1 inch. Therefore, there is almost no possibility that the peripheral end surface of the wafer 13 will be scratched.
また、仮りに、カセット１１の変形やウェハ１３の反り
が発生しても、同じ理由で、上記接触面積は左程大きく
ならないので、ウェハ１３の周端 一部表面における
キズも最小限に抑えることができる。Furthermore, even if the cassette 11 is deformed or the wafer 13 is warped, for the same reason, the above-mentioned contact area will not become as large as shown on the left, so scratches on the peripheral and partial surface of the wafer 13 can also be minimized. I can do it.
上記実施例では、ウェハ収納用カセットについて説明し
たが、石英ボードやウェハ移し替え装置等のように、ウ
ェハ収納用カセットと同様の■形溝を有するものであっ
てもよく、上記実施例と同様の効果を奏する。In the above embodiment, a wafer storage cassette was explained, but it may also be a wafer storage cassette, such as a quartz board or a wafer transfer device, which has a ■-shaped groove similar to the wafer storage cassette. It has the effect of
以上のように、この発明によれば■形溝の角度ｔ６度３
６分から８度以上に広げることによって、カセットのＶ
形溝とＩＣ基板との接触面積を小さくし、ＩＣ基板の周
端部表面にキズが付かないようにするとともに、カセッ
トの変形、ＩＣ基板の反りが発生しても■形溝とＩＣ基
板との接触面積が左程大ざくならないようにしたから、
ＩＣ基板の製品とじての歩留まりを向上させることがで
きる。As described above, according to this invention, the angle t of the ■-shaped groove is 6 degrees 3
By widening the cassette to more than 6 to 8 degrees,
The contact area between the groove and the IC board is reduced to prevent scratches on the peripheral edge surface of the IC board, and even if the cassette is deformed or the IC board is warped, the contact area between the groove and the IC board is minimized. Because the contact area of the is not as large as the left,
The yield of IC substrates as products can be improved.
第１図はこの発明の実施例であるつ；ハ収納用カセット
を示し、同図（ａ）はその斜視図、同図（ｂ）は要部拡
大平面図、第２図は従来のウェハ収納用カセットを示し
、同図（、）はその斜視図、同図伽）は要部拡大平面図
である。
図中、１１はウェハ収納用カセット、１２はＶ形１１４
．１３はウェハである。FIG. 1 shows a wafer storage cassette which is an embodiment of the present invention, FIG. 1A is a perspective view thereof, FIG. Figures 1 and 2 are perspective views, and Figures 3 and 5 are enlarged plan views of the main parts. In the figure, 11 is a wafer storage cassette, 12 is a V-shaped 114
．． 13 is a wafer.
Claims (1)
合う複数対のＶ形溝を有するカセットにおいて、前記Ｖ
形溝の角度を８度以上にしたことを特徴とするＩＣ基板
収納用カセット。A cassette having a plurality of pairs of V-shaped grooves facing each other into which an IC board is inserted at a peripheral end thereof,
A cassette for storing IC boards, characterized by a shape groove having an angle of 8 degrees or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8145986A JPS62237744A (en) | 1986-04-07 | 1986-04-07 | Cassette containing ic substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8145986A JPS62237744A (en) | 1986-04-07 | 1986-04-07 | Cassette containing ic substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62237744A true JPS62237744A (en) | 1987-10-17 |
Family
ID=13746983
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8145986A Pending JPS62237744A (en) | 1986-04-07 | 1986-04-07 | Cassette containing ic substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62237744A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7648888B2 (en) * | 2001-08-07 | 2010-01-19 | S.O.I.Tec Silicon On Insulator Technologies | Apparatus and method for splitting substrates |
| CN102569139A (en) * | 2012-02-24 | 2012-07-11 | 中利腾晖光伏科技有限公司 | Flower basket for flock preparing of single-crystalline-silicon solar cell |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS606504A (en) * | 1983-05-18 | 1985-01-14 | マイクロ・グラス・インコ−ポレ−テツド | System and method of transporting wafer |
-
1986
- 1986-04-07 JP JP8145986A patent/JPS62237744A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS606504A (en) * | 1983-05-18 | 1985-01-14 | マイクロ・グラス・インコ−ポレ−テツド | System and method of transporting wafer |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7648888B2 (en) * | 2001-08-07 | 2010-01-19 | S.O.I.Tec Silicon On Insulator Technologies | Apparatus and method for splitting substrates |
| CN102569139A (en) * | 2012-02-24 | 2012-07-11 | 中利腾晖光伏科技有限公司 | Flower basket for flock preparing of single-crystalline-silicon solar cell |
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