JPS62230063A - Manufacture of hetero structure field-effect transistor - Google Patents
Manufacture of hetero structure field-effect transistorInfo
- Publication number
- JPS62230063A JPS62230063A JP7357786A JP7357786A JPS62230063A JP S62230063 A JPS62230063 A JP S62230063A JP 7357786 A JP7357786 A JP 7357786A JP 7357786 A JP7357786 A JP 7357786A JP S62230063 A JPS62230063 A JP S62230063A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gallium arsenide
- type
- electrode
- arsenide layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 125000005842 heteroatom Chemical group 0.000 title abstract description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims abstract description 50
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 50
- 239000012535 impurity Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 14
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 9
- 239000013078 crystal Substances 0.000 claims abstract description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 abstract description 6
- 239000002184 metal Substances 0.000 abstract description 6
- 230000007423 decrease Effects 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 62
- 239000007789 gas Substances 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000011084 recovery Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 230000005533 two-dimensional electron gas Effects 0.000 description 3
- 239000012808 vapor phase Substances 0.000 description 3
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はゲート電極とソース及びドレインの間隔を自己
整合方式により短く制御できるヘテロ構造電界効果トラ
ンジスタの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a heterostructure field effect transistor in which the distance between a gate electrode and a source and drain can be controlled to be short by a self-alignment method.
従来の技術
一般に電界効果トランジスタのしゃ断固波数ｆｔは次式
で表わされる。BACKGROUND OF THE INVENTION In general, the cutoff wave number ft of a field effect transistor is expressed by the following equation.
ｆｔ＝ｇ−’／２πｃｐｓ
ｇｌＩ゛ ：相互コンダクタンス、Ｃｇｓ：ゲート・ソ
ース間容量
従って、しゃ断固波数ｆｔを高くし、高周波特性を改善
するためにはｇ、を大きくし、ｃｗｓを減少しなければ
ならない。ｇｍ’ は見掛上の値であで表される。ｒ５
はソース・ゲート間の直列抵抗であり、ｒ、を減少させ
ることにより、相互コンダクタンスｇｖ＝” を改善さ
せることができる。ところで第２図に従来のへテロ接合
電界効果トランジスタの構造図を示す。ｒ８はソース・
コンタクト抵抗Ｒｃとソース・ゲート間の２次元電子ガ
ス層による抵抗Ｒ３との和である。２次元ガス濃度がｔ
ｏ”／ｃａと低いためにシート抵抗値が大きく、ＲＳを
減少させるためにはソース・ゲート間の距離を極力小さ
くする必要がある。しかし現在のフォトリソグラフィー
の技術ではマスク合せ精度の限界は０．５μｍぐらいで
あり、この方法ではソース・ゲート間の距離を１μｍ以
下にすることは困難であり、従ってゲート・ソース間の
直列抵抗ｒｓが増大して相互コンダクｇ、“が減少する
。またソースコンタクト抵抗ＲｃがＭＥＳＦＥＴに比べ
て高いためにソース・コンタクト部にＳｔイオン注入に
よりＮ型高濃度不純物層を形成してＲｃを低くしている
。そこで高精度のマスク合せを必要とせずに直列抵抗ｒ
、を減少させることが可能であるイオン注入を用いた種
々の自己整合方式が提案されている。第３図は耐熱ゲー
ト自己整合方式であり、不純物を含有しない砒化ガリウ
ムの単結晶よりなるチャンネル層２を形成し、チャンネ
ル層２上にＮ型アルミニウムガリウム砒素の単結晶層よ
りなる電子供給層３を形成した後、Ｗｓｉ等の高耐熱性
金属からなるゲート４をマスクにしてイオン注入を行い
、自己整合的にＮ型高濃度不純物層７を形成し、ゲート
金属を付着したまま高温の熱処理によるＮ型高協度不に
物層７の結晶性を回復後、ソース電極５．ドレイン電極
６を形成する。（６０年応物秋季講演１ｐ−Ｂ−９等）
。この方法では、高温による結晶性回復の工程により、
ヘテロ界面が損傷を受け、電子移動度が低下するなど特
性が劣下する。またイオン注入により形成されたＮ型高
濃度不純物層とＡ、Ｇ、とのオーミック抵抗はＧ□Ａ、
ＭＵＳＦＥＴの場合と比較してかなり大きい。ft=g-'/2πcps glI゛: mutual conductance, Cgs: gate-source capacitance Therefore, in order to increase the blocking wave number ft and improve high frequency characteristics, g must be increased and cws must be decreased. It won't happen. gm' is expressed as an apparent value. r5
is the series resistance between the source and gate, and by reducing r, the mutual conductance gv='' can be improved. By the way, FIG. 2 shows a structural diagram of a conventional heterojunction field effect transistor. r8 is the source
This is the sum of the contact resistance Rc and the resistance R3 due to the two-dimensional electron gas layer between the source and gate. The two-dimensional gas concentration is t
o"/ca, which results in a large sheet resistance, and in order to reduce RS, it is necessary to minimize the distance between the source and gate. However, with current photolithography technology, the limit of mask alignment accuracy is 0. With this method, it is difficult to reduce the distance between the source and the gate to 1 μm or less, so that the series resistance rs between the gate and the source increases and the mutual conductance g, " decreases. Furthermore, since the source contact resistance Rc is higher than that of a MESFET, an N-type high concentration impurity layer is formed in the source contact portion by St ion implantation to lower Rc. Therefore, without the need for high-precision mask alignment, the series resistance r
Various self-alignment schemes using ion implantation have been proposed that can reduce . FIG. 3 shows a heat-resistant gate self-alignment method, in which a channel layer 2 made of a single crystal of gallium arsenide containing no impurities is formed, and an electron supply layer 3 made of a single crystal layer of N-type aluminum gallium arsenide is formed on the channel layer 2. After forming, ion implantation is performed using the gate 4 made of a highly heat-resistant metal such as WSi as a mask, an N-type high concentration impurity layer 7 is formed in a self-aligned manner, and then high-temperature heat treatment is performed with the gate metal still attached. After recovering the crystallinity of the N-type high-cooperation material layer 7, the source electrode 5. A drain electrode 6 is formed. (1960 Autumn Lecture 1p-B-9, etc.)
. In this method, through the process of crystallinity recovery by high temperature,
The hetero-interface is damaged and the properties deteriorate, such as the electron mobility being reduced. Also, the ohmic resistance between A, G and the N-type high concentration impurity layer formed by ion implantation is G□A,
It is quite large compared to the case of MUSFET.
発明が解決しようとする問題点
このように従来の製造方法では、高温の結晶性の回復工
程を要するためにＮ型アルミニウムガリウム砒素の電子
供給層から不純物を含有しない砒化ガリウムよりなるチ
ャンネル層中にもＮ型の不純物が拡散され、電子蓄積層
（２次元電子ガス）の電子移動度を低下させる欠点があ
る。Problems to be Solved by the Invention As described above, in the conventional manufacturing method, since a high-temperature crystallinity recovery process is required, the electron supply layer of N-type aluminum gallium arsenide is transferred to the channel layer made of gallium arsenide containing no impurities. However, N-type impurities are diffused, which reduces the electron mobility of the electron storage layer (two-dimensional electron gas).
本発明は高温の熱処理工程を用いることなく、ゲート電
極の極めて近傍までソース・ドレインの電極形成領域と
なるＮ＋型砒化ガリウム層自己整合的に形成でき、電子
蓄積ＪＷ（２次元電子ガス層）内の電子移動度の低下等
の問題点も改善できるヘテロ構造電界効果型トランジス
タの製造方法を提供することを目的としている。The present invention enables the formation of an N+ type gallium arsenide layer, which serves as the source/drain electrode formation region, in a self-aligned manner up to the very vicinity of the gate electrode without using a high-temperature heat treatment process. It is an object of the present invention to provide a method for manufacturing a heterostructure field effect transistor, which can also improve problems such as a decrease in electron mobility.
問題点を解決するための手段
本発明は上記問題点を解決するために、半絶縁性砒化ガ
リウム基板上に実質的に不純物を含有しない砒化ガリウ
ムからなるチャンネル層とＮ型アルミニウムガリウム砒
素からなる電子供給層とＰ＋型砒化ガリウムらなる層を
連続して形成し、該Ｐ＋型砒化ガリウム層上選択的にゲ
ート電極を形成し、前記ゲート電極をマスクにしてＰＩ
型型化化ガリウム層選択的にエツチングしてＰ−Ｎ型制
御電極を形成し、エツチングされたＰ＋型砒化ガリウム
層側壁に絶縁膜を設けて、Ｐ＋型砒化ガリウム層び絶縁
膜をマスクとして、電子供給層をエツチングし、Ｎ＋型
砒化ガリウムらなる単結晶をエピタキシャル成長し、ソ
ース・ドレインの電極形成領域を工程を有することを特
徴とするヘテロ構造電界効果トランジスタを製造する方
法を提供する。Means for Solving the Problems The present invention solves the above problems by forming a channel layer made of gallium arsenide substantially free of impurities and an electron layer made of N-type aluminum gallium arsenide on a semi-insulating gallium arsenide substrate. A supply layer and a layer made of P+ type gallium arsenide are successively formed, a gate electrode is selectively formed on the P+ type gallium arsenide layer, and PI is formed using the gate electrode as a mask.
A patterned gallium arsenide layer is selectively etched to form a P-N type control electrode, an insulating film is provided on the side wall of the etched P+ type gallium arsenide layer, and the P+ type gallium arsenide layer and the insulating film are used as a mask. A method for manufacturing a heterostructure field effect transistor is provided, which comprises etching an electron supply layer, epitaxially growing a single crystal of N+ type gallium arsenide, and forming source/drain electrode formation regions.
作用
上記した手段による作用は次のようになる。すなわちＰ
−Ｎ型制御電極の側壁に設けられた絶縁膜の膜厚により
ゲート電極とＮ°型型化化ガリウム層の間隔が自己整合
的に決り、再現よく均一にゲート電極とＮ＋型砒化ガリ
ウム層の間隔を短（できるので、ソース・ゲート間の抵
抗Ｒ８を小さくでき、またソース・ドレインの電極形成
領域がＮ０型砒化ガリウム層により構成されているので
、従来のＮ型アルミニウムガリウム砒素と砒化ガリウム
層からなる電極形成領域に比較して、コンタクト抵抗Ｒ
ｃを小さくできるので、ソース・ゲート間の直列抵抗に
ｒ、を著しく低減できる。Effect The effect of the above-mentioned means is as follows. That is, P
- The distance between the gate electrode and the N° type gallium arsenide layer is determined in a self-aligned manner by the thickness of the insulating film provided on the side wall of the N type control electrode, and the distance between the gate electrode and the N+ type gallium arsenide layer is uniformly reproducibly determined. Since the distance between the source and the gate can be shortened, the resistance R8 between the source and gate can be reduced, and since the source/drain electrode formation region is composed of the N0 type gallium arsenide layer, it is possible to reduce the resistance R8 between the source and the gate. Contact resistance R compared to the electrode formation region consisting of
Since c can be made small, the series resistance r between the source and gate can be significantly reduced.
イオン注入を用いていないので、高温の結晶性回復工程
がなく、ヘテロ界面が損傷を受けないので、電子蓄積Ｎ
（２次元電子ガスＮ）内の電子移動度の低下等の特性の
劣下がない。ショットキバリヤ型制御電極に代えてＰ−
Ｎ接合型制御電極を用いているので、Ｎ′″型砒化ガリ
ウム層のエピタキシャル成長温度によっても接合の界面
は影響を受けない。またＰ＋砒化ガリウム層とオーミッ
クコンタクトを取る制御電極用金属は低抵抗のものが使
用でき、耐熱性金属を用いたシヨ・ノトキバリャ型制御
電極に比べて、ゲート抵抗を小さくできる。Since ion implantation is not used, there is no high-temperature crystallinity recovery process, and the hetero interface is not damaged, so the electron storage N
(Two-dimensional electron gas N) There is no deterioration in characteristics such as a decrease in electron mobility. P- instead of Schottky barrier type control electrode
Since an N-junction type control electrode is used, the junction interface is not affected by the epitaxial growth temperature of the N''' type gallium arsenide layer. Also, the control electrode metal that makes ohmic contact with the P+ gallium arsenide layer is a low-resistance metal. The gate resistance can be lower than that of a short-circuit control electrode using a heat-resistant metal.
この結果、高い相互コンダクタンスｇ、′を有し、ゲー
ト抵抗も極めて小さいヘテロ構造電界効果トランジスタ
を再現よく製造することができる。As a result, a heterostructure field effect transistor having high mutual conductance g,' and extremely low gate resistance can be manufactured with good reproducibility.
実施例
以下、本発明のへテロ構造電界効果トランジスタの製造
方法の一実施例について図面を参照しながら説明する。EXAMPLE Hereinafter, an example of the method for manufacturing a heterostructure field effect transistor of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｅ）は本発明の製造方法を説明するた
めの図で主要工程における素子断面を示す。FIGS. 1(a) to 1(e) are diagrams for explaining the manufacturing method of the present invention and show cross sections of the element in main steps.
ｌはＧ、Ａ、半絶縁性基板、２はノンドープ砒化ガリウ
ム層、３はＮ型アルミニウムガリウム砒素層、４はゲー
ト電極、５はソース電極、６はドレイン電極、ｌＯはＰ
＋砒化ガリウム層、１１は気相成長Ｓ８０□膜、１２は
Ｎ＋型砒化ガリウム層１２゛はポリ砒化ガリウム層であ
る。l is G, A is a semi-insulating substrate, 2 is a non-doped gallium arsenide layer, 3 is an N-type aluminum gallium arsenide layer, 4 is a gate electrode, 5 is a source electrode, 6 is a drain electrode, lO is P
+ gallium arsenide layer, 11 is a vapor phase grown S80□ film, 12 is an N+ type gallium arsenide layer 12' is a polygallium arsenide layer.
（ａｌのように半絶縁性砒化ガリウム基板１に、モレキ
ュラービームエピタキシャル成長法を使用して、厚さ３
０００人程度０実質的に不純物を含有していない砒化ガ
リウム層２ （チャンネルＮ）と、６ＸＩＯ”］／ｃｄ
のＮ型不純物を含有する厚さ８００人のＮ型アルミニウ
ムガリウム砒素（、ｌ。、３Ｇ、。、。(Molecular beam epitaxial growth method is used on a semi-insulating gallium arsenide substrate 1 such as Al, and
Approximately 000 gallium arsenide layer 2 (channel N) and 6
800 N-type aluminum gallium arsenide (,l.,3G,.,.
Ａ、）層３（電子供給装置）及び高濃度にＰ型不純物を
含有する厚さ５０００人のＰ型（Ｐ”型）砒化ガリウム
層１０を連続して形成する。（ｂ）のようにチタン・白
金・金（Ｔｔ ／Ｐｔ ／Ａ、）の三重層よりなる制御
′Ｉａ電極４を制御電極形成領域に選択的に形成し、平
行平板型リアクティブイオンエツチング（ＲＩ Ｅ）装
置によりエツチングガスとしてＣＣｌ２ Ｆ２とＨｌの
混合ガスを用いて、制御電極４をマスクにしてＰ＋型砒
化ガリウム層１０選択的にエツチングして、制御電極下
部にＰ＋型砒化ガリウム層１０’ を形成する。次に厚
さ０．２μｍの気相成長Ｓ、０□膜で全面を覆い、ＲＩ
Ｅ装置によりエツチングガスとしてＣＦ、と酸素の混合
ガスを用いてエツチングして（Ｃ）のようにＰ１１型砒
化ガリウム１０゛ の側壁に気相成長膜Ｓ、Ｏ□膜１１
を形成し、Ｒ■Ｅ装置によりエツチングガスとしてＣＣ
ｌ４とＣ１２の混合ガスを用いてＮ型アルミニウムガリ
ウム砒素Ｎ３と実質的に不純物を含まない砒化ガリウム
層２の一部をエツチングし、（ｄ）のようにモレキュラ
ービームエピタキシャル成長法を使用して、３Ｘ１０”
／ｃｓＪのＮ型不純物を含有する厚さ４０００人のＮ型
（Ｎ”型）砒化ガリウム層１２を形成し、この時ゲート
電極４上にはポリ砒化ガリウム１２′が形成される。Ｎ
０型砒化ガリウム層１２上に（ｅｌのようにＮｉ ／Ａ
、Ｇ、／Ｎｉ ／Ａｕの４重層からなるソース電極５及
びドレイン電極６を選択的に形成してヘテロ構造電界効
果トランジスタが完成する。A.) A layer 3 (electron supply device) and a P-type (P'' type) gallium arsenide layer 10 containing a high concentration of P-type impurities and having a thickness of 5000 are successively formed. - A control 'Ia electrode 4 consisting of a triple layer of platinum/gold (Tt/Pt/A) is selectively formed in the control electrode formation area, and etched as an etching gas using a parallel plate reactive ion etching (RIE) device. Using a mixed gas of CCl2 F2 and Hl, the P+ type gallium arsenide layer 10' is selectively etched using the control electrode 4 as a mask to form a P+ type gallium arsenide layer 10' under the control electrode. The entire surface was covered with a 0.2 μm vapor-grown S, 0□ film, and RI
Etching is performed using a mixed gas of CF and oxygen as an etching gas using E equipment to form vapor phase grown films S and O□ film 11 on the side walls of P11 type gallium arsenide 10゛ as shown in (C).
CC is formed as an etching gas using an R
A part of the N-type aluminum gallium arsenide N3 and substantially impurity-free gallium arsenide layer 2 is etched using a mixed gas of l4 and C12, and a 3×10 layer is etched using a molecular beam epitaxial growth method as shown in (d). ”
An N-type (N"-type) gallium arsenide layer 12 containing N-type impurities of /csJ and having a thickness of 4000 layers is formed, and at this time, polygallium arsenide 12' is formed on the gate electrode 4.
On the type 0 gallium arsenide layer 12 (Ni/A like el)
, G, /Ni 2 /Au are selectively formed to form a source electrode 5 and a drain electrode 6, thereby completing a heterostructure field effect transistor.
実施例では第１の絶縁膜として気相成長Ｓｔｏｗ膜を用
いたが、スパッタＳ、０□膜やプラズマ窒化膜等でもよ
い。In the embodiment, a vapor phase grown Stow film was used as the first insulating film, but a sputtered S, 0□ film, plasma nitride film, etc. may also be used.
またチャンネル部を構成する際に実質的に不純物を含有
しない砒化ガリウム層（チャンネル層）とＮ型アルミニ
ウムガリウム砒素層（電子供給Ｎ）の２層構造を用いた
が、不純物を含有しない砒化ガリウム層にＮ型不純物た
るシリコンが拡散することを防止するために、５０〜６
０人の厚さを有する実質的に不純物を含有しないアルミ
ニウムガリウム砒素からなるバッファ層をチャンネル層
と電子供給層間に介在させてもよい。In addition, when forming the channel part, we used a two-layer structure consisting of a gallium arsenide layer (channel layer) that does not substantially contain impurities and an N-type aluminum gallium arsenide layer (electron supply N), but the gallium arsenide layer that does not contain impurities In order to prevent silicon, which is an N-type impurity, from diffusing into the
A buffer layer made of substantially impurity-free aluminum gallium arsenide having a thickness of 0.035 mm may be interposed between the channel layer and the electron supply layer.
またアルミニウムガリウム砒素層３のエツチングはＲＩ
Ｅ装置によるドライエツチングを用いたが、エツチング
液として硫酸と過酸化水素水との混合液（ＨｚＳＯａ：
ＨｚＯｚ：ＨｔＯ： １ ： １ ：２０）を用いてエ
ツチングしてもよい。Also, the etching of the aluminum gallium arsenide layer 3 is performed using RI.
Dry etching using E equipment was used, but a mixed solution of sulfuric acid and hydrogen peroxide solution (HzSOa:
Etching may be performed using HzOz:HtO: 1:1:20).
またゲート電極の材料は６００℃前後で砒化ガリウム層
と強く反応しないものであればよい。Further, the material of the gate electrode may be any material as long as it does not react strongly with the gallium arsenide layer at around 600°C.
発明の効果
以上要するに、本発明によれば、ゲート電極とソース電
極形成領域であるＮ＋型砒化ガリウム層の間隔を自己整
合的に絶縁膜の膜厚により決定され、上記間隔を０．２
〜０．３μｍ程度のものとし、またソース部・ドレイン
の電極形成領域がＮ＋型砒化ガリウム層形成されている
ので、ソース電極とゲート電極間の直列抵抗を低減でき
る。高温の結晶性回復工程がないので、ヘテロ界面に損
傷を与えることはなく、またＰ−Ｎ接合型制御電極を用
いているためにゲート抵抗も低減できる。従って本発明
を用いることにより、非常に高周波特性の優れたヘテロ
構造電界効果トランジスタが提供でき、また素子の集積
化は容易であり、きわめて有用である。Effects of the Invention In short, according to the present invention, the distance between the gate electrode and the N+ type gallium arsenide layer, which is the source electrode formation region, is determined in a self-aligned manner by the thickness of the insulating film, and the distance is set to 0.2.
The thickness is approximately 0.3 μm, and the N+ type gallium arsenide layer is formed in the source and drain electrode formation regions, so the series resistance between the source electrode and the gate electrode can be reduced. Since there is no high-temperature crystallinity recovery process, there is no damage to the hetero interface, and since a PN junction type control electrode is used, gate resistance can be reduced. Therefore, by using the present invention, a heterostructure field effect transistor with extremely excellent high frequency characteristics can be provided, and the device can be easily integrated, making it extremely useful.
第１図（ａｌ〜（８１は本発明の一実施例におけるヘテ
ロ構造電界効果トランジスタの製造工程図、第２図は従
来のプレナー構造のへテロ構造電界効果トランジスタの
構造図、第３図は高耐熱性ゲートをマスクにして自己整
合的にイオン注入を行いＮ一層を形成したヘテロ構造ト
ランジスタの構造図である。
１・・・・・・半絶縁性砒化ガリウム基板、２・・・・
・・実質的に不純物を含有しない（ノンドープ）砒化ガ
リウム層、３・・・・・・Ｎ型アルミニウムガリウム砒
素層、４・・・・・・ゲート電極、５・・・・・・ソー
ス電極、６・・・・・・ドレイン電極、７・・・・・・
高濃度不純物層（Ｎ”層）、１０・・・・・・Ｐ°砒化
ガリウム層、１１・・・・・・気相成長Ｓ五〇□膜、１
２・・・・・・Ｎ＋型砒化ガリウム層１２゛ ・・・・
・・ポリ砒化ガリウム層。
代理人の氏名 弁理士 中尾敏男 ばか１名第２図
第３図Figure 1 (al~(81) is a manufacturing process diagram of a heterostructure field effect transistor according to an embodiment of the present invention, Figure 2 is a structural diagram of a conventional planar structure heterostructure field effect transistor, and Figure 3 is a It is a structural diagram of a heterostructure transistor in which a single layer of N is formed by performing ion implantation in a self-aligned manner using a heat-resistant gate as a mask. 1... Semi-insulating gallium arsenide substrate, 2...
... Gallium arsenide layer that does not substantially contain impurities (non-doped), 3 ... N-type aluminum gallium arsenide layer, 4 ... Gate electrode, 5 ... Source electrode, 6...Drain electrode, 7...
High concentration impurity layer (N'' layer), 10...P° gallium arsenide layer, 11...Vapor phase growth S50□ film, 1
2...N+ type gallium arsenide layer 12゛...
...Polygallium arsenide layer. Name of agent Patent attorney Toshio Nakao One idiot Figure 2 Figure 3
Claims (1)
純物を含有しない砒化ガリウムの単結晶よりなるチャン
ネル層を形成し、前記チャンネル層上にＮ型アルミニウ
ムガリウム砒素の単結晶よりなる電子供給層を形成し、
前記電子供給層上に高濃度のＰ型不純物を含むＰ型（Ｐ
＾＋型）砒化ガリウムの単結晶層を成長して、前記Ｐ＾
＋型砒化ガリウム層上にゲート電極を形成し、前記ゲー
ト電極をマスクにして前記Ｐ＾＋型砒化ガリウム層を選
択的にエッチングしてゲート電極下部のみに前記Ｐ＾＋
砒化ガリウム層を残しＰ−Ｎ接合型制御電極を形成する
工程と、エッチングして残された前記Ｐ＾＋型砒化ガリ
ウム層の側壁に絶縁膜を形成する工程と、前記Ｐ＾＋型
砒化ガリウム層と前記絶縁膜をマスクにして電子供給層
を選択的にエッチングし、高濃度のＮ型不純物を含むＮ
型（Ｎ＾＋型）砒化ガリウム層をエピタキシャル成長し
、ソース・ドレインの電極形成領域を形成する工程を具
備することを特徴とするヘテロ構造電界効果トランジス
タの製造方法。A channel layer made of a single crystal of gallium arsenide containing substantially no impurities is formed on a substrate made of semi-insulating gallium arsenide, and an electron supply layer made of a single crystal of N-type aluminum gallium arsenide is formed on the channel layer. form,
P-type (P) containing a high concentration of P-type impurity on the electron supply layer
By growing a single crystal layer of gallium arsenide (^+ type), the above P^
A gate electrode is formed on the +-type gallium arsenide layer, and the P^+-type gallium arsenide layer is selectively etched using the gate electrode as a mask to form the P^+ only under the gate electrode.
a step of forming a P-N junction type control electrode while leaving the gallium arsenide layer; a step of forming an insulating film on the side wall of the P^+ type gallium arsenide layer left after etching; The electron supply layer is selectively etched using the insulating layer and the insulating film as a mask, and N containing a high concentration of N-type impurities is etched.
A method for manufacturing a heterostructure field effect transistor, comprising the step of epitaxially growing a type (N^+ type) gallium arsenide layer to form source/drain electrode formation regions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7357786A JPS62230063A (en) | 1986-03-31 | 1986-03-31 | Manufacture of hetero structure field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7357786A JPS62230063A (en) | 1986-03-31 | 1986-03-31 | Manufacture of hetero structure field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62230063A true JPS62230063A (en) | 1987-10-08 |
Family
ID=13522284
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7357786A Pending JPS62230063A (en) | 1986-03-31 | 1986-03-31 | Manufacture of hetero structure field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62230063A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5448086A (en) * | 1993-06-01 | 1995-09-05 | Nec Corporation | Field effect transistor |
| WO2014154120A1 (en) * | 2013-03-25 | 2014-10-02 | 复旦大学 | High-electron-mobility transistor employing gate first process and manufacturing method for the transistor |
-
1986
- 1986-03-31 JP JP7357786A patent/JPS62230063A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5448086A (en) * | 1993-06-01 | 1995-09-05 | Nec Corporation | Field effect transistor |
| WO2014154120A1 (en) * | 2013-03-25 | 2014-10-02 | 复旦大学 | High-electron-mobility transistor employing gate first process and manufacturing method for the transistor |
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