JPS62219531A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS62219531A
JPS62219531A JP61063475A JP6347586A JPS62219531A JP S62219531 A JPS62219531 A JP S62219531A JP 61063475 A JP61063475 A JP 61063475A JP 6347586 A JP6347586 A JP 6347586A JP S62219531 A JPS62219531 A JP S62219531A
Authority
JP
Japan
Prior art keywords
frames
chips
integrated circuit
semiconductor integrated
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61063475A
Other languages
Japanese (ja)
Inventor
Hideo Kameda
亀田　英夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP61063475A priority Critical patent/JPS62219531A/en
Publication of JPS62219531A publication Critical patent/JPS62219531A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce the external measurements as well as to enhance the degree of integration of the titled device by a method wherein two IC chip-mounted frames are adhered together back to back, and a prescribed wire bonding is performed. CONSTITUTION:IC chips 12a and 12b are die-bonded to frames 13a and 13b respectively, and they are assembled in the same flow as the assembling of the ordinary integrated circuit until a wire bonding is completed. These two kinds of frames 13a and 13b are superposed back to back based on the positioning pin on a molding metal mold in a molding process, they are sealed with resin molding material, and the frames 13a and 13b and the IC chips 12a and 12b are fixed. After the resin molding has been finished, the pins 14a, 14b and 14c are electrically connected to the upper and the lower pins 14a, 14b and 14c respectively using the method such as plating, solder dipping and the like.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、小型化と構成の簡略化を図った半導体集積
回路装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device that is miniaturized and has a simplified configuration.

〔従来の技術〕[Conventional technology]

第４図は従来の複数のＩＣを使用した半導体集積回路装
置の平面図で、この例では２個のＩＣを基板にマウント
し、基板上の配線で２個のＩＣのインタフェイスを接続
したものを示している。Figure 4 is a plan view of a conventional semiconductor integrated circuit device using multiple ICs. In this example, two ICs are mounted on a board, and the interfaces of the two ICs are connected by wiring on the board. It shows.

この図において、１はモールド樹脂で、２ａ　。In this figure, 1 is mold resin and 2a.

２ｂは樹脂モールドされたＩＣチップをそれぞれ示して
いる。４ａは前記ＩＣチップ２ａの入出力ピン、４ｂは
前記ＩＣチップ２ｂの入出力ピン、４ｃは前記ＩＣチッ
プ２ａと２ｂのインタフェイス用のピンを示す。また６
は基板、７ａは前記ＩＣチップ２ａの入出力用の配線、
７ｂは前記ＩＣチップ２ｂの入出力用の配線、７ｃは前
記ＩＣチップ２ａと２ｂのインタフェイス用の配線を示
す。2b each shows an IC chip molded with resin. 4a is an input/output pin of the IC chip 2a, 4b is an input/output pin of the IC chip 2b, and 4c is an interface pin between the IC chips 2a and 2b. Also 6
7a is a substrate, input/output wiring for the IC chip 2a,
Reference numeral 7b indicates wiring for input/output of the IC chip 2b, and reference numeral 7c indicates wiring for an interface between the IC chips 2a and 2b.

従来、２つ以上のＩＣを用いる場合、第４図に示すよう
に、基板６の上に２つのＩＣチップ２ａ、２ｂをマウン
トし、基板６上にプリントされた配線によって、ＩＣチ
ップ２ａの入出力ピン４ａおよびＩＣチップ２ｂの入出
力ピン４ｂの取り出しと、配線７ｃによるＩＣチップ２
ａと２ｂのインタフェイスの接続を行う。Conventionally, when using two or more ICs, as shown in FIG. Taking out the output pin 4a and the input/output pin 4b of the IC chip 2b, and connecting the IC chip 2 with the wiring 7c.
Connect the interfaces a and 2b.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の基板６上で２つのＩＣチップ２ａ、２ｂのインタ
フェイスを接続する方法では、２つのＩＣチップ２ａ、
２ｂをマウントする面積に加え、インタフェイスの配線
部分の面積が必要となり、平面的に非常に大きな面積が
必要となるという欠点があった。In the conventional method of connecting the interfaces of two IC chips 2a, 2b on the board 6, the two IC chips 2a,
In addition to the area for mounting the 2b, an area for the wiring part of the interface is required, resulting in a drawback that a very large area is required in terms of plane.

また面積的に制約のある場合は、基板６の両面側にＩＣ
チップ２ａ、２ｂをマウントすることが可能であるが、
基板６を２層にする等で、基板６のコストが非常に上が
る等の欠点があった。In addition, if there are area constraints, ICs may be placed on both sides of the board 6.
Although it is possible to mount chips 2a and 2b,
Since the substrate 6 is made of two layers, the cost of the substrate 6 increases significantly.

この発明は、」二記のような問題点を解消するためにな
されたもので、小型で工程数を減少せしめた半導体集積
回路装置を得ることを目的とする。This invention has been made to solve the problems mentioned in section 2 above, and aims to provide a semiconductor integrated circuit device that is small in size and has a reduced number of manufacturing steps.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る半導体集積回路装置は、２つのＩＣチッ
プを同形同寸法のフレームにそれぞれ独立にダイポンド
およびワイヤボンドをした後、この２つのフレームを樹
脂モールドする際に位置決めピンにより位置決めして背
中合わせに固定して樹脂モールドを行い、その後、メッ
キやハンダディップ等の方法により背中合せにされたリ
ードピン同士を電気的に接続したものである。In the semiconductor integrated circuit device according to the present invention, two IC chips are independently die bonded and wire bonded to frames of the same shape and size, and then positioned back to back with positioning pins when molding the two frames with resin. After that, the lead pins placed back to back are electrically connected to each other by a method such as plating or solder dipping.

〔作用〕[Effect]

この発明においては、ＩＣチップをそれぞれマウントし
たフレームを背中合わせに固定することにより、外形寸
法が小さくなるとともに、２つのＩＣチップのインタフ
ェイスの外部配線も省略できる。In this invention, by fixing the frames on which the IC chips are respectively mounted back to back, the external dimensions can be reduced and external wiring for the interface between the two IC chips can be omitted.

〔実施例〕〔Example〕

第１図〜第３図はこの発明の一実施例を示すもので、第
１図は半導体集積回路装置の側断面図、第２図、第３図
は第１図をそれぞれ拡大して示した上面図と下面図であ
る。1 to 3 show an embodiment of the present invention, in which FIG. 1 is a side sectional view of a semiconductor integrated circuit device, and FIGS. 2 and 3 are enlarged views of FIG. 1. They are a top view and a bottom view.

これらの図において、１１は樹脂モールドパッケージ、
１２ａは上面側のＩＣチップ、１２ｂは下面側のＩＣチ
ップを示し、これらのＩＣチップ１２ａ、１２ｂはそれ
ぞれフレーム１３ａ。In these figures, 11 is a resin mold package,
Reference numeral 12a indicates an IC chip on the upper surface side, 12b indicates an IC chip on the lower surface side, and these IC chips 12a and 12b each form a frame 13a.

１３ｂにダイポンドされる。１４ａは前記ＩＣチップ１
２ａの入出力ピン、１４ｂは前記ＩＣチップ１２ｂの入
出力ピン、１４ｃは前記ＩＣチ・ンプ１２ａと１２ｂの
インタフェイスビンである。工Ｃチップ１２ａ、１２ｂ
がそれぞれダイボンドされた２つのフレーム１３ａ、１
３ｂは背中合わせにはり合わされ、ざらにＩＣチップ１
２ａは第２図に示すように入出力ピン１４ａおよびイン
タフェイスピン１４ｃにそれぞれワイヤ１５ａによりワ
イヤボンドされ、ＩＣチップ１２ｂは第３図に示すよう
に入出力ビン１４ｂおよびインタフェイスビン１４ｃに
それぞれワイヤ１５ｂによりワイヤボンドされた後、モ
ールド樹脂によってモールドされ樹脂モールドパッケー
ジ１１が形成される。また背中合せにされた各ピン１４
ａ。It is die pounded to 13b. 14a is the IC chip 1
2a is an input/output pin, 14b is an input/output pin of the IC chip 12b, and 14c is an interface bin between the IC chips 12a and 12b. Engineering C chips 12a, 12b
two frames 13a, 1 to which are die-bonded, respectively.
3b are pasted back to back, and the IC chip 1 is roughly inserted.
2a is wire-bonded to the input/output pin 14a and the interface pin 14c by wires 15a, respectively, as shown in FIG. After wire bonding, the resin molded package 11 is formed by molding with a molding resin. Each pin 14 is also placed back to back.
a.

１４ｂ、１４ｃはその後にメッキもしくはハンダデツプ
等で電気的に接続される。14b and 14c are then electrically connected by plating or solder dip.

この発明における半導体集積回路装置の製造過程におい
て、ＩＣチップ１２ａ、１２ｂをフレーム１３ａ、１３
ｂのそれぞれにダイボンドし、ワイヤボンドを完了する
までは、通常の集積回路の組み立てと同一のフローで行
う。この２種類のフレーム１３ａ、１３ｂをモールド工
程において、モールド金型上で位置決めピン（図示せず
）を基準にして、背中合わせに重ね合わせて、樹脂モー
ルドによって封入してフレーム１３ａ、１３ｂおよびＩ
Ｃチップ１２ａ、１２ｂを固定する。この状態では２つ
のフレーム１３ａ、１３ｂｔ−３よび各ピン１４ａ　＊
　１４ｂ　；　１４ｃは機械的に接触しているだけであ
るので、接触不良を起こす恐れがある。In the manufacturing process of the semiconductor integrated circuit device according to the present invention, the IC chips 12a and 12b are mounted on the frames 13a and 13.
The process of die bonding to each of the parts b and completing the wire bonding is carried out in the same flow as the assembly of a normal integrated circuit. In the molding process, these two types of frames 13a, 13b are stacked back to back on a molding die with positioning pins (not shown) as a reference, and the frames 13a, 13b and I
Fix the C chips 12a and 12b. In this state, two frames 13a, 13bt-3 and each pin 14a *
Since 14b and 14c are only in mechanical contact, there is a risk of poor contact.

したがって、樹脂モールド後、各ピン１４ａ。Therefore, after resin molding, each pin 14a.

１４ｂ、１４ｃはメッキもしくはハンダデツプ等の方法
により上下の各ピン１４　ａ　＋　１４　ｂ＋１４ｃを
それぞれ電気的に接続させる。14b and 14c electrically connect the upper and lower pins 14a+14b+14c by a method such as plating or soldering.

なお、上記実施例では、黒色モールドパッケージにおい
て、２つの異なるＩＣチップ１２ａ。In the above embodiment, two different IC chips 12a are used in the black molded package.

１２ｂを組み立てる場合について述べたが、透明モール
ドパッケージにおいて、ＩＣチップと光センサチップを
組み立てる場合についても同様である。Although the case of assembling 12b has been described, the same applies to the case of assembling an IC chip and a photosensor chip in a transparent mold package.

さらに、フレーム１３ａ、１３ｂへのマウントおよびワ
イヤボンドをバンプによって作成する場合も同様である
。Furthermore, the same applies when mounting to frames 13a, 13b and wire bonding are created by bumps.

〔発明の効果〕〔Effect of the invention〕

この発明は以上説明したとおり、２つのＩＣチップのマ
ウントされたフレームを背中合わせにはり合わせ、所要
のワイヤボンドを行った後、１つの樹脂モールドに封入
した後、背中合せにされた各ピンを電気的に接続したの
で、これら各ピンは上面、下面の共通のインタフェイス
となり、集積度が高まり、かつ小型化が図れるとともに
、外部配線でインタフェイスを行う必要がなくなり、そ
のため、余分な工程を省略できる等の効果がある。As explained above, in this invention, the frames on which two IC chips are mounted are pasted back to back, the necessary wire bonding is performed, and the frames are encapsulated in one resin mold. Since each pin is connected to the top and bottom surfaces, it becomes a common interface on the top and bottom surfaces, increasing the degree of integration and reducing the size.There is no need to interface with external wiring, so extra steps can be omitted. There are other effects.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明の一実施例を示す半導体集積回路装置
の側断面図、第２図および第３図は第１図の上面図およ
び下面図、第４図は従来の半導体集積回路装置の上面図
を示す。 図において、］１は樹脂モールドパッケージ、１２ａ、
１２ｂはＩＣチップ、１３ａ、１３ｂはフレーム、１４
ａ、１４ｂは入出カビ７．１４ｃはインタフェイスピン
、１５ａ、１５ｂはワイヤである。 なお、各図中の同一符号は同一または相当部分を示す。 代理人　大　岩　増　雄　　　（ほか２名）第１図 第２図 １４ａ　１４ａ　１４ａ　１４ｂ　１４ｂ　１４ｂ　１
４ｂ　１４ａ　１４ａ　１４ａデ　　　　　　　　　　
１ ３ａ １５ａ　　　　　　　　　　　　　　　　　　　　　　
　　　　　　　　　　　　　１２ａ１／−１／−１／−
１７−１／−１／−１／−１７−１７−１／、−第３図 第４図FIG. 1 is a side sectional view of a semiconductor integrated circuit device showing an embodiment of the present invention, FIGS. 2 and 3 are top and bottom views of FIG. 1, and FIG. 4 is a side sectional view of a conventional semiconductor integrated circuit device. A top view is shown. In the figure,] 1 is a resin mold package, 12a,
12b is an IC chip, 13a and 13b are frames, 14
14c is an interface pin, and 15a, 15b is a wire. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (and 2 others) Figure 1 Figure 2 14a 14a 14a 14b 14b 14b 1
4b 14a 14a 14a de
1 3a 15a
12a1/-1/-1/-
17-1/-1/-1/-17-17-1/, -Figure 3Figure 4

Claims (1)

【特許請求の範囲】[Claims] ２つ以上のＩＣチップを備えた半導体集積回路装置にお
いて、前記各チップをそれぞれフレームに独立にダイボ
ンドし、前記２つのフレームを背中合わせにはりつけ、
前記各ＩＣチップとこれらのＩＣチップに対応するピン
とのワイヤボンドを施した後、樹脂モールドを行い、さ
らに前記背中合わせにされたピン同士をそれぞれ電気的
に接続したことを特徴とする半導体集積回路装置。In a semiconductor integrated circuit device equipped with two or more IC chips, each of the chips is independently die-bonded to a frame, and the two frames are attached back to back,
A semiconductor integrated circuit device characterized in that each of the IC chips and the pins corresponding to the IC chips are wire-bonded, resin molding is performed, and the pins placed back to back are electrically connected to each other. .
JP61063475A 1986-03-19 1986-03-19 Semiconductor integrated circuit device Pending JPS62219531A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61063475A JPS62219531A (en) 1986-03-19 1986-03-19 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61063475A JPS62219531A (en) 1986-03-19 1986-03-19 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS62219531A true JPS62219531A (en) 1987-09-26

Family

ID=13230292

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61063475A Pending JPS62219531A (en) 1986-03-19 1986-03-19 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS62219531A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5034350A (en) * 1987-09-23 1991-07-23 Sgs Thomson Microelectronics S.R.L. Semiconductor device package with dies mounted on both sides of the central pad of a metal frame
US5273938A (en) * 1989-09-06 1993-12-28 Motorola, Inc. Method for attaching conductive traces to plural, stacked, encapsulated semiconductor die using a removable transfer film
US6423102B1 (en) 1994-11-30 2002-07-23 Sharp Kabushiki Kaisha Jig used for assembling semiconductor devices

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5034350A (en) * 1987-09-23 1991-07-23 Sgs Thomson Microelectronics S.R.L. Semiconductor device package with dies mounted on both sides of the central pad of a metal frame
US5273938A (en) * 1989-09-06 1993-12-28 Motorola, Inc. Method for attaching conductive traces to plural, stacked, encapsulated semiconductor die using a removable transfer film
US6423102B1 (en) 1994-11-30 2002-07-23 Sharp Kabushiki Kaisha Jig used for assembling semiconductor devices

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