JPS62216370A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62216370A JPS62216370A JP5983786A JP5983786A JPS62216370A JP S62216370 A JPS62216370 A JP S62216370A JP 5983786 A JP5983786 A JP 5983786A JP 5983786 A JP5983786 A JP 5983786A JP S62216370 A JPS62216370 A JP S62216370A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- chemical vapor
- film
- gate insulating
- temperature chemical
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000002131 composite material Substances 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims description 17
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 6
- 239000000126 substance Substances 0.000 abstract 3
- 230000003647 oxidation Effects 0.000 description 9
- 238000007254 oxidation reaction Methods 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 4
- 230000001186 cumulative effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、熱酸化法と高温化学気相成長法による複合酸
化膜をゲート絶縁膜に用いたＭＯＳ）ランジスタに関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MOS transistor using a composite oxide film formed by thermal oxidation and high temperature chemical vapor deposition as a gate insulating film.
本発明はＭＯＳ）ランジスタの絶縁膜の形成において、
熱酸化により形成される酸化膜と高温化学気相成長によ
る酸化膜を複合的に形成することにより、トランプの少
ない、絶縁耐圧特性の優れたゲート絶縁膜の形成を可能
とするものである。The present invention relates to the formation of an insulating film of a MOS transistor.
By compositely forming an oxide film formed by thermal oxidation and an oxide film formed by high-temperature chemical vapor deposition, it is possible to form a gate insulating film with fewer trumps and excellent dielectric strength characteristics.
従来、ＭＯＳトランジスタの絶縁酸化膜は熱酸化工程も
しくは化学気相成長による工程のいずれか一方のみを用
いて形成されていた。Conventionally, insulating oxide films of MOS transistors have been formed using only one of a thermal oxidation process and a chemical vapor deposition process.
しかしながら、熱酸化により形成された酸化膜は高温化
学気相成長法より形成される酸化膜よりトラップが少な
いという長所を持っているが、絶縁耐圧歩留は劣ってい
る。However, although oxide films formed by thermal oxidation have the advantage of fewer traps than oxide films formed by high-temperature chemical vapor deposition, they are inferior in dielectric strength yield.
一方、高温化学気相成長法により形成された酸化膜は熱
酸化により形成される酸化膜より絶縁耐圧歩留は高いが
、トラップが多いという欠点をもっている。On the other hand, an oxide film formed by high-temperature chemical vapor deposition has a higher dielectric strength yield than an oxide film formed by thermal oxidation, but has the disadvantage of having more traps.
このように前記２種類の工程から形成されるそれぞれの
酸化膜は一長一短があり、これをゲート絶縁膜として利
用しようとする時、さらに性能の良い酸化膜が期待され
ていた。As described above, each of the oxide films formed through the above two types of processes has advantages and disadvantages, and when attempting to use them as a gate insulating film, an oxide film with even better performance has been expected.
以」−に述べた問題点を解決するために、本発明ではゲ
ート絶縁膜を熱酸化により形成し、続いて７００℃以上
の高温化学気相成長法により複合的に酸化膜を成長させ
た。この複合酸化膜は、まず７００℃以上の高温化学気
相成長法を用いて酸化した後、続いて熱酸化を行なって
も同様な複合酸化膜が形成され、同様な成果が得られる
。In order to solve the problems described below, in the present invention, a gate insulating film is formed by thermal oxidation, and then a composite oxide film is grown by high temperature chemical vapor deposition at 700° C. or higher. Even if this composite oxide film is first oxidized using high-temperature chemical vapor deposition at 700° C. or higher and then thermally oxidized, a similar composite oxide film will be formed and similar results will be obtained.
上記のごとく形成された複合酸化膜は、高温化学気相成
長法により形成される絶縁耐圧歩留の高い酸化膜と熱酸
化により形成されるトラップの少ない酸化膜の両者の長
所を兼ね備えて持っている。The composite oxide film formed as described above has the advantages of both an oxide film with a high dielectric strength yield formed by high-temperature chemical vapor deposition and an oxide film with few traps formed by thermal oxidation. There is.
故にこの複合酸化膜はＭＯＳトランジスタのゲート絶縁
膜として理想的な性能を発揮することが可能となる。Therefore, this composite oxide film can exhibit ideal performance as a gate insulating film of a MOS transistor.
本発明の実施例を図面に基づいて詳細に説明する。第１
図は本発明による半導体装置の断面図である。 第１図
において１は半導体基板であり、その表面近傍にソース
領域２およびドレイン領域３が設けられており、これら
に挟まれた半導体基板ｌの表面上に熱酸化膜４が、その
上に高温化学気相成長法による酸化膜５が形成されてい
る。さらにその上に制御ゲート電極６が設けられている
。Embodiments of the present invention will be described in detail based on the drawings. 1st
The figure is a sectional view of a semiconductor device according to the present invention. In FIG. 1, reference numeral 1 denotes a semiconductor substrate, and a source region 2 and a drain region 3 are provided near the surface of the semiconductor substrate 1. On the surface of the semiconductor substrate 1 sandwiched between these, a thermal oxide film 4 is deposited at a high temperature. An oxide film 5 is formed by chemical vapor deposition. Furthermore, a control gate electrode 6 is provided thereon.
上記複合酸化膜４，５の構造は（１）熱酸化後、高温化
学気相成長、（２）高温化学気相成長後、熱酸化のいず
れの工程を用いても半導体基板１上に熱酸化膜４が接し
、その上に高温化学気相成長法による酸化膜５を積み重
ねる形に形成される。The structure of the composite oxide films 4 and 5 can be thermally oxidized on the semiconductor substrate 1 using any of the following steps: (1) thermal oxidation followed by high-temperature chemical vapor deposition, or (2) high-temperature chemical vapor deposition followed by thermal oxidation. The film 4 is in contact with the oxide film 5, and an oxide film 5 formed by high temperature chemical vapor deposition is stacked thereon.
酸化膜のトラップを測定する方法としてＭＯＳダイオー
ドを用いる方法が一般に知られており、その結果を第２
図に示す。第２図は１０００°Ｃの熱酸化膜、８５０°
Ｃ５ｉｆｔ□（Ｊｌ、 ＋ｌｌ、Ｑで形成した高温化学
気相成長法による酸化膜をそれぞれゲート絶縁膜として
用いたＭＯＳダイオードにおいてゲート・基板電極間に
一定電流を流すためのゲート電圧の経時変化図である。A method using MOS diodes is generally known as a method for measuring traps in oxide films, and the results are
As shown in the figure. Figure 2 shows thermal oxide film at 1000°C, 850°
C5ift□ (Jl, +ll, Q) is a diagram of the change in gate voltage over time to flow a constant current between the gate and substrate electrodes in a MOS diode using oxide films formed by high temperature chemical vapor deposition as gate insulating films. be.
この図におけるゲート電圧の上昇は酸化膜中あるいは酸
化膜−シリコン界面に存在するトランプによって電子が
捕獲されるためである。したがってこの結果は熱酸化膜
の方がトラップが少ないことを示している。The rise in gate voltage in this figure is due to electrons being captured by the cards present in the oxide film or at the oxide film-silicon interface. Therefore, this result shows that the thermal oxide film has fewer traps.
第３図は上記二種類の酸化膜を用いたＭｏ３）ランジス
タに一定電流密度を印加した時の誘電破壊時間に対する
累積破壊率を示す図である。横軸は、ストレス印加時間
を、縦軸は、累積破壊率を示す。この結果より明らかに
高温化学気相成長法による酸化膜の方が破壊しにくいこ
とがわかる。FIG. 3 is a graph showing the cumulative breakdown rate with respect to the dielectric breakdown time when a constant current density is applied to the Mo3) transistor using the above two types of oxide films. The horizontal axis shows the stress application time, and the vertical axis shows the cumulative failure rate. This result clearly shows that the oxide film formed by high temperature chemical vapor deposition is more difficult to destroy.
以上の二つの利点から、前記の構造をもつ複合酸化膜は
Ｍｏ３）ランジスタのゲート絶縁膜として優れた動作を
行うことが可能である。Because of the above two advantages, the composite oxide film having the above structure can perform excellently as a gate insulating film of a Mo3) transistor.
本発明による熱酸化膜と高温化学気相成長法による酸化
膜によって構成される複合酸化膜を利用することにより
トラップの少ない、絶縁耐圧特性の高いＭｏ３）ランジ
スタのゲート絶縁膜を得ることが可能となった。By using a composite oxide film composed of a thermal oxide film according to the present invention and an oxide film produced by high-temperature chemical vapor deposition, it is possible to obtain a gate insulating film for a Mo3) transistor with fewer traps and high dielectric strength characteristics. became.
第１図は、本発明による半導体装置の断面図である。第
２図は、ＭＯＳダイオードゲート電圧の経時変化図であ
り、第３図は、ＭｏＳトランジスタの誘電破壊時間に対
する累積破壊率を示す図である。
１・・・半導体基板
２・・・ソース領域
３・・・ドレイン領域
４・・・熱酸化膜
５・・・高温化学気相成長法による酸化膜６・・・制御
ゲート電極
以」二FIG. 1 is a sectional view of a semiconductor device according to the present invention. FIG. 2 is a graph showing the change in MOS diode gate voltage over time, and FIG. 3 is a graph showing the cumulative breakdown rate with respect to the dielectric breakdown time of the MoS transistor. 1...Semiconductor substrate 2...Source region 3...Drain region 4...Thermal oxide film 5...Oxide film formed by high temperature chemical vapor deposition 6...Control gate electrode and beyond
Claims (2)
レイン領域に挟まれた半導体基板表面上において、ゲー
ト絶縁膜が少なくとも２種類以上の酸化膜からなる複合
酸化膜であることを特徴とする半導体装置。(1) A semiconductor characterized in that the gate insulating film is a composite oxide film consisting of at least two or more types of oxide films on the surface of the semiconductor substrate sandwiched between a source region and a drain region provided near the surface of the semiconductor substrate. Device.
温度７００℃以上の高温化学気相成長法による酸化膜か
らなる２層以上の複合酸化膜であることを特徴とする特
許請求の範囲第１項記載の半導体装置。(2) The gate insulating film is a composite oxide film of two or more layers consisting of at least a thermal oxide film and an oxide film formed by high-temperature chemical vapor deposition at a formation temperature of 700° C. or higher. The semiconductor device according to item 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5983786A JPS62216370A (en) | 1986-03-18 | 1986-03-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5983786A JPS62216370A (en) | 1986-03-18 | 1986-03-18 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62216370A true JPS62216370A (en) | 1987-09-22 |
Family
ID=13124733
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5983786A Pending JPS62216370A (en) | 1986-03-18 | 1986-03-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62216370A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009004804A (en) * | 2008-09-01 | 2009-01-08 | Renesas Technology Corp | Semiconductor device |
| JP2013106019A (en) * | 2011-11-17 | 2013-05-30 | Toyota Central R&D Labs Inc | Semiconductor device, and method for manufacturing the same |
| US8748266B2 (en) | 1997-08-28 | 2014-06-10 | Renesas Electronics Corporation | Method of fabricating semiconductor device |
-
1986
- 1986-03-18 JP JP5983786A patent/JPS62216370A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8748266B2 (en) | 1997-08-28 | 2014-06-10 | Renesas Electronics Corporation | Method of fabricating semiconductor device |
| US9275863B2 (en) | 1997-08-28 | 2016-03-01 | Renesas Electronics Corporation | Method of fabricating semiconductor device |
| JP2009004804A (en) * | 2008-09-01 | 2009-01-08 | Renesas Technology Corp | Semiconductor device |
| JP2013106019A (en) * | 2011-11-17 | 2013-05-30 | Toyota Central R&D Labs Inc | Semiconductor device, and method for manufacturing the same |
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