JPS6221285B2 - - Google Patents
Info
- Publication number
- JPS6221285B2 JPS6221285B2 JP53128801A JP12880178A JPS6221285B2 JP S6221285 B2 JPS6221285 B2 JP S6221285B2 JP 53128801 A JP53128801 A JP 53128801A JP 12880178 A JP12880178 A JP 12880178A JP S6221285 B2 JPS6221285 B2 JP S6221285B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- agc
- circuit
- signal
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000003321 amplification Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3005—Automatic control in amplifiers having semiconductor devices in amplifiers suitable for low-frequencies, e.g. audio amplifiers
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Control Of Amplification And Gain Control (AREA)
Description
【発明の詳細な説明】
本発明は自動利得制御回路（以下AGC回路と
いう）に関するもので特にラジオ受信機等におけ
る高周波増幅段（以下RF段という）と中間周波
増幅段（以下IF段という）等の多段増幅回路の
利得制御に適したAGC回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to automatic gain control circuits (hereinafter referred to as AGC circuits), and in particular to radio frequency amplification stages (hereinafter referred to as RF stages) and intermediate frequency amplification stages (hereinafter referred to as IF stages) in radio receivers, etc. This invention relates to an AGC circuit suitable for controlling the gain of a multi-stage amplifier circuit.
従来、この種のAGC回路においては信号対雑
音比特性をよくする為に、RF段のAGC動作をIF
段より遅らせて行わしめているがこの様なAGC
回路でIF段の利得の圧縮が過度に行なわれると
IF段若しくは周波数変換回路等に歪みを生じる
事がある。 Conventionally, in this type of AGC circuit, in order to improve the signal-to-noise ratio characteristics, the AGC operation of the RF stage was changed to IF.
This kind of AGC is performed later than the previous step.
If the circuit compresses the gain of the IF stage too much,
Distortion may occur in the IF stage or frequency conversion circuit.
即ち、多段増幅回路にAGCの機能を有せしめ
た場合、その利得制御量は各段の利得配分に従い
更には前段の出力に歪みの生じる事のないように
設定される必要があるが、実際には上述のような
問題が生じる。 In other words, when a multi-stage amplifier circuit is equipped with an AGC function, the gain control amount needs to be set according to the gain distribution of each stage and also so as not to cause distortion in the output of the previous stage. The above-mentioned problem arises.
本発明の第１の目的は、上述の点にかんがみ、
過度の利得の圧縮を避けるため、一定の制御量を
有するAGC回路を提供せんとするものである。 In view of the above points, the first object of the present invention is to
In order to avoid excessive gain compression, an attempt is made to provide an AGC circuit with a constant control amount.
更に本発明の第２の目的は増幅回路に利得制御
を行なしめてもその直流出力電圧の変動しない
AGC回路を提供しようとするものである。 Furthermore, a second object of the present invention is to prevent the DC output voltage from changing even if gain control is performed on the amplifier circuit.
It attempts to provide an AGC circuit.
本発明によれば、それぞれの入力端子が同一信
号源に接続され、かつそれぞれの出力電流を同一
負荷に供給するようにした第１と第２の差動増幅
器と該第１と第２の差動増幅器のバイアス電流を
それぞれ供給する第１と第２のバイアス供給回路
手段と前記負荷の出力信号に応じた制御電圧を発
生する制御電圧発生手段と該制御電圧発生手段の
出力をうけて前記第１のバイアス供給回路のバイ
アス電流を変化させる回路手段とを備えたことを
特徴とする自動利得制御回路が得られる。 According to the present invention, first and second differential amplifiers each have their respective input terminals connected to the same signal source and supply their respective output currents to the same load; first and second bias supply circuit means for respectively supplying bias currents of the dynamic amplifier; control voltage generation means for generating a control voltage according to the output signal of the load; and circuit means for changing the bias current of one bias supply circuit.
次に本発明の実施例を図面を用いて説明する。 Next, embodiments of the present invention will be described using the drawings.
第１図は本発明の一実施例を示す回路接続図で
ある。 FIG. 1 is a circuit connection diagram showing one embodiment of the present invention.
第１図において信号源Ｓから発生した信号はコ
ンデンサC1を介してトランジスタQ1およびQ2に
よつて構成される第１の差動増幅器とトランジス
タQ3およびQ4とによつて構成される第２の差動
増幅にそれぞれ加えられ増幅されて前記第１と第
２の増幅器の負荷ＲLよりとり出される。回路手
段ｂは負荷ＲL中に生じた出力信号電圧に応じた
直流電圧を発生する手段である。 In FIG. 1, a signal generated from a signal source S is connected via a capacitor C 1 to a first differential amplifier formed by transistors Q 1 and Q 2 and formed by transistors Q 3 and Q 4 . They are respectively added to the second differential amplifier, amplified, and taken out from the loads R L of the first and second amplifiers. The circuit means b is a means for generating a DC voltage according to the output signal voltage generated in the load RL .
次にAGC動作について説明する。 Next, AGC operation will be explained.
今、信号源Ｓからの信号の増大に応じて負荷Ｒ
L中に生じる信号が増大すると端子ｃに生じる
AGC電圧も増大し、その電圧がトランジスタQ7
のベースエミツタ間のしきい値より高くなるとト
ランジスタQ7が動作しトランジスタQ5のベース
電位を降下させトランジスタQ5の電流を減少さ
せる。その為トランジスタQ1およびQ2によつて
構成される第１の差動増幅器の利得は減少し負荷
ＲLの信号レベルは一定におさえられる。さらに
信号が増大してゆくとやがてトランジスタQ5の
電流は０となる。この時第１の差動増幅器の利得
は０となり第２の増幅器のみによつて信号源Ｓの
信号は増幅されて負荷ＲLよりとり出される。こ
の時点で利得制御は行なわれなくなる。AGC回
路の動作しない時の利得をＡ〓1、AGC回路が十
分動作しこれ以上入力信号を増大してもAGC効
果のなくなつた状態での電圧利得をＡ〓2とする
と
Ａ〓1＝ＲＬ／ｒｅＱ１＋ｒｅＱ２
＋ＲＬ／ｒｅＱ３＋ｒｅＱ４＋Ｒ６＋Ｒ７
Ａ〓2＝ＲＬ／ｒｅＱ３＋ｒｅＱ４＋Ｒ６＋Ｒ７
で表わされる、
但しｒeQoはエミツタ接合抵抗でトランジスタ
Qnのエミツタ電流をＩEQo（mA）とすれば
ｒeQo＝２６／ＩＥＱｏ （Ω）
で与えられる。 Now, as the signal from the signal source S increases, the load R
When the signal generated during L increases, it is generated at terminal c.
The AGC voltage also increases and that voltage is connected to transistor Q 7
When the voltage becomes higher than the base-emitter threshold, transistor Q7 operates, lowering the base potential of transistor Q5 and reducing the current of transistor Q5 . Therefore, the gain of the first differential amplifier constituted by transistors Q 1 and Q 2 is reduced, and the signal level of the load R L is held constant. As the signal increases further, the current in transistor Q5 eventually becomes zero. At this time, the gain of the first differential amplifier becomes 0, and the signal from the signal source S is amplified only by the second amplifier and taken out from the load R L. At this point, gain control is no longer performed. If the gain when the AGC circuit is not operating is A〓 1 , and the voltage gain when the AGC circuit is fully operating and there is no AGC effect even if the input signal is increased is A〓 2 , then A〓 1 = R L / r eQ1 + r eQ2 + R L / r eQ3 + r eQ4 + R 6 + R 7 A〓 2 = R L / r eQ3 + r eQ4 + R 6 + R 7 , where r eQo is the emitter junction resistance of the transistor.
If the emitter current of Qn is I EQo (mA), it is given by r eQo =26/I EQo (Ω).
又、ＲLは負荷ＲLのインピーダンスを表わし
R6，R7はそれぞれ抵抗R6，R7の抵抗値である。 Also, R L represents the impedance of the load R L
R 6 and R 7 are the resistance values of resistors R 6 and R 7 , respectively.
従つて、利得制御量Ａ〓(AGO)は次式で与えら
れる。 Therefore, the gain control amount A〓 (AGO) is given by the following equation.
Ａ〓(AGC)＝Ａ〓１／Ａ〓２
上式より第１と第２の差動増幅器のバイアス電
流及び抵抗R6，R7の値を適切に選ぶ事によつて
利得制御量Ａ〓(AGC)を任意の一定値に設定でき
る。又、AGCが十分かかつた時、第２の差動増
幅器のエミツタに抵抗R6，R7が挿入されている
ので入力のダイナミツクレンジが広く歪み等に対
して有利である。 A〓 (AGC) = A〓 1 /A〓 2 From the above equation, by appropriately selecting the bias current of the first and second differential amplifiers and the values of the resistors R 6 and R 7 , the gain control amount A〓 (AGC) can be set to any constant value. Furthermore, when the AGC is sufficiently activated, the resistors R 6 and R 7 are inserted into the emitter of the second differential amplifier, so the dynamic range of the input is wide, which is advantageous against distortion and the like.
第１の増幅器を構成するトランジスタQ1とQ2
のエミツタは互いに結合されてトランジスタQ3
のコレクタに接続され、又第２の増幅器を構成す
るトランジスタQ3およびQ4のエミツタはそれぞ
れ抵抗R6およびR7を介してトランジスタQ9のコ
レクタに接続されている。さらにトランジスタ
Q8およびQ9のエミツタはそれぞれ抵抗R10及び
R11を介してトランジスタQ10のコレクタに接続さ
れている。トランジスタQ10は定電流回路を形成
している。信号源Ｓからの信号が小さく端子ｃに
発生するAGC電圧が小さい時はトランジスタQ8
のベース電圧はダイオードD6の電源から抵抗
R4を介して与えられ、一方トランジスタQ9のベ
ース電圧はダイオードD6の電極から与えられ
ているのでトランジスタQ10の電流はすべてトラ
ンジスタQ8に流れている。従つてトランジスタ
Q3およびQ4で構成される第２の差動増幅器のバ
イアス電流は０であり電圧増幅度は０である。従
つて信号源Ｓの信号はトランジスタQ1及びQ2に
よつて構成される第１の差動増幅器によつて増幅
されてトランジスタQ1のコレクタに接続された
抵抗R13よりとり出され、さらにトランジスタQ11
によつて増幅され、トランジスタQ12のエミツタ
ホロワ回路より出力信号がとり出される。 Transistors Q 1 and Q 2 forming the first amplifier
The emitters of transistor Q 3 are coupled together
The emitters of transistors Q 3 and Q 4 constituting the second amplifier are connected to the collector of transistor Q 9 via resistors R 6 and R 7 , respectively. More transistors
The emitters of Q 8 and Q 9 are resistors R 10 and
Connected to the collector of transistor Q 10 via R 11 . Transistor Q10 forms a constant current circuit. When the signal from signal source S is small and the AGC voltage generated at terminal c is small, transistor Q 8
The base voltage of the diode D is from the power supply of the resistor
Since the base voltage of transistor Q 9 is applied from the electrode of diode D 6 , all the current of transistor Q 10 flows to transistor Q 8 . Therefore the transistor
The bias current of the second differential amplifier composed of Q 3 and Q 4 is 0, and the voltage amplification degree is 0. Therefore, the signal from the signal source S is amplified by the first differential amplifier constituted by the transistors Q 1 and Q 2 and taken out from the resistor R 13 connected to the collector of the transistor Q 1 . Transistor Q 11
The output signal is amplified by the emitter follower circuit of transistor Q12 .
信号源Ｓからの信号が増大すると上記出力信号
も増大し平滑回路手段ｂより端子ｃに供給される
AGC電圧も増大する。端子ｃのAGC電圧がトラ
ンジスタQ7のベースエミツタ間電圧のしきい値
をこえるとトランジスタQ7が動作しコレクタに
接続されている抵抗R4の電圧降下が生じトラン
ジスタQ8のベース電位を下げる。トランジスタ
Q8のベース電位が下がるとやがてトランジスタ
Q8に流れていた電流の一部がトランジスタQ9に
流れるようになる。トランジスタQ9の電流は第
２の差動増幅器に供給される。第２の差動増幅器
のトランジスタQ3およびQ4のエミツタはそれぞ
れ抵抗R6およびR7が挿入されているので第１の
差動増幅器より利得が低い。従つてトランジスタ
Q9に電流が分流されるようになるとトランジス
タQ1のベース端子から負荷抵抗R13をみた電圧利
得は低下し出力信号は一定におさえられる。 When the signal from the signal source S increases, the output signal also increases and is supplied to the terminal c from the smoothing circuit means b.
AGC voltage also increases. When the AGC voltage at terminal c exceeds the base-emitter voltage threshold of transistor Q7 , transistor Q7 operates, causing a voltage drop across resistor R4 connected to its collector, lowering the base potential of transistor Q8 . transistor
When the base potential of Q 8 decreases, the transistor eventually
Part of the current that was flowing through Q8 now flows through transistor Q9 . The current of transistor Q9 is supplied to the second differential amplifier. The emitters of the transistors Q 3 and Q 4 of the second differential amplifier have lower gain than the first differential amplifier because the resistors R 6 and R 7 are inserted, respectively. Therefore the transistor
When current is shunted to Q9 , the voltage gain seen from the base terminal of transistor Q1 to load resistor R13 decreases, and the output signal is held constant.
さらに入力信号が増大して、トランジスタQ8
の電流が減少しトランジスタQ8の電流が０にな
るとAGC動作は停止し、この時点より入力信号
の増大と共に出力信号を増大していくことにな
る。又、第２図の利得制御においてトランジスタ
Q11の動作点はAGC動作の行なわれていない時で
もAGC動作の行なわれている時でも常に同じで
ある。 As the input signal increases further, transistor Q 8
When the current in transistor Q8 decreases and the current in transistor Q8 becomes 0, the AGC operation stops, and from this point on, the output signal increases as the input signal increases. Also, in the gain control shown in Fig. 2, the transistor
The operating point of Q 11 is always the same even when AGC operation is not performed and when AGC operation is performed.
つまりAGC動作が行なわれないような入力信
号レベルの小さい時にはトランジスタQ10の電流
はすべてトランジスタQ8に流れるので、トラン
ジスタQ1とQ2には動作点という観点からいうと
トランジスタQ10の電流が半分ずつ流れるとみて
差支えない。以下、特に断わらないがいずれもこ
の観点からいう。 In other words, when the input signal level is low and the AGC operation is not performed, all the current of transistor Q10 flows to transistor Q8 , so from the point of view of the operating point, the current of transistor Q10 flows to transistors Q1 and Q2 . It is safe to assume that it will flow in half. Everything below is referred to from this perspective, although it is not specified otherwise.
従つて抵抗R13に流れる電流はトランジスタQ10
の半分に等しい。同様にAGC動作が十分行なわ
れトランジスタQ8の電流が０になつた時も抵抗
R6とR7を等しい値に設定しておけば抵抗R13に流
れる電流はトランジスタQ10の半分である。AGC
動作時、トランジスタQ1およびQ2の電流は等し
く、又トランジスタQ2およびQ3の電流値も等し
いので抵抗R13に流れる電流はトランジスタQ10の
半分の電流が流れる。従つてトランジスタQ11の
初期のバイアスを適切に設定しておけばトランジ
スタQ11の動作点はAGC回路の動作に関係なく常
に一定なので第１と第２の差動増幅器とトランジ
スタQ7，Q8，Q9，Q10によつて構成される利得制
御回路の後に直結の増幅器トランジスタQ11を設
けても信号が歪む等の不都合は生じない。従つて
外付端子に制限をうける集積回路化にはきわめて
好都合である。又集積回路においては差動トラン
ジスタのベア性が非常にすぐれているので本発明
のAGC回路は集積回路化に適している。 Therefore, the current flowing through the resistor R 13 is the transistor Q 10
equal to half of Similarly, when the AGC operation is sufficiently performed and the current of transistor Q8 becomes 0, the resistance
If R 6 and R 7 are set to the same value, the current flowing through resistor R 13 is half that of transistor Q 10 . AGC
During operation, the currents of transistors Q 1 and Q 2 are equal, and the current values of transistors Q 2 and Q 3 are also equal, so that the current flowing through resistor R 13 is half that of transistor Q 10 . Therefore, if the initial bias of transistor Q 11 is set appropriately, the operating point of transistor Q 11 will always be constant regardless of the operation of the AGC circuit, so the first and second differential amplifiers and transistors Q 7 and Q 8 , Q 9 , and Q 10 , even if the directly connected amplifier transistor Q 11 is provided after the gain control circuit, problems such as signal distortion will not occur. Therefore, it is extremely convenient for integrated circuits where external terminals are limited. Furthermore, in an integrated circuit, the AGC circuit of the present invention is suitable for integration as the differential transistor has very good bareness.
以上本発明によれば自動利得制御回路の利得制
御量を容易に一定にでき、特に直結増幅器を後段
に持つ高利得増幅回路の半導体集積回路化に大き
な効果がある。 As described above, according to the present invention, it is possible to easily keep the gain control amount of the automatic gain control circuit constant, and it is particularly effective in integrating a high gain amplifier circuit having a direct-coupled amplifier in the subsequent stage into a semiconductor integrated circuit.
第１図は本発明一実施例を示す回路接続図であ
る。
図面において、D5，D6…，D8，D9はダイオー
ド、R1，R2，…，R15，R16は抵抗、Q1，Q2…，
Q12，Q13はトランジスタ、C1はコンデンサ、Ｓ
は信号源、ａは電源端子、ｄは接地端子、ｂは信
号に応じたAGC電圧を発生する回路手段、ｃは
AGC電圧供給端子をそれぞれ示す。
FIG. 1 is a circuit connection diagram showing one embodiment of the present invention. In the drawing, D 5 , D 6 ..., D 8 , D 9 are diodes, R 1 , R 2 , ..., R 15 , R 16 are resistors, Q 1 , Q 2 ...,
Q 12 , Q 13 are transistors, C 1 is a capacitor, S
is a signal source, a is a power supply terminal, d is a ground terminal, b is a circuit means for generating an AGC voltage according to the signal, and c is a
The AGC voltage supply terminals are shown respectively.
Claims (1)
れ、かつそれぞれの出力電流を同一負荷に供給す
るようにした第１と第２の差動増幅器と、前記第
１と第２の差動増幅器のバイアス電流を供給する
バイアス供給回路手段と、前記バイアス供給回路
手段に互に結合されたエミツタが接続され、コレ
クタが前記第１と第２の差動増幅器にそれぞれ接
続され、一方のベースに定電圧が供給され、他方
のベースには前記負荷の出力信号に応じた制御電
圧を発生する制御電圧発生手段の出力が接続され
た１対の差動トランジスタを備えたことを特徴と
する自動利得制御回路。1 first and second differential amplifiers whose respective input terminals are connected to the same signal source and whose respective output currents are supplied to the same load; Bias supply circuit means for supplying a bias current, emitters coupled to each other are connected to the bias supply circuit means, collectors are respectively connected to the first and second differential amplifiers, and one base is connected to a constant voltage. an automatic gain control circuit, characterized in that it is provided with a pair of differential transistors, the other base of which is connected to the output of a control voltage generating means that generates a control voltage according to the output signal of the load. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12880178A JPS5555608A (en) | 1978-10-19 | 1978-10-19 | Automatic gain control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12880178A JPS5555608A (en) | 1978-10-19 | 1978-10-19 | Automatic gain control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5555608A JPS5555608A (en) | 1980-04-23 |
| JPS6221285B2 true JPS6221285B2 (en) | 1987-05-12 |
Family
ID=14993760
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12880178A Granted JPS5555608A (en) | 1978-10-19 | 1978-10-19 | Automatic gain control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5555608A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11419216B2 (en) | 2020-03-30 | 2022-08-16 | Samsung Display Co., Ltd. | Display device and method of manufacturing the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS537139B2 (en) * | 1974-04-08 | 1978-03-15 | ||
| JPS5334446A (en) * | 1976-09-10 | 1978-03-31 | Matsushita Electric Ind Co Ltd | Automatic gain control circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5721378Y2 (en) * | 1976-07-02 | 1982-05-10 |
-
1978
- 1978-10-19 JP JP12880178A patent/JPS5555608A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS537139B2 (en) * | 1974-04-08 | 1978-03-15 | ||
| JPS5334446A (en) * | 1976-09-10 | 1978-03-31 | Matsushita Electric Ind Co Ltd | Automatic gain control circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11419216B2 (en) | 2020-03-30 | 2022-08-16 | Samsung Display Co., Ltd. | Display device and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5555608A (en) | 1980-04-23 |
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