JPS6221269B2 - - Google Patents
Info
- Publication number
- JPS6221269B2 JPS6221269B2 JP55159003A JP15900380A JPS6221269B2 JP S6221269 B2 JPS6221269 B2 JP S6221269B2 JP 55159003 A JP55159003 A JP 55159003A JP 15900380 A JP15900380 A JP 15900380A JP S6221269 B2 JPS6221269 B2 JP S6221269B2
- Authority
- JP
- Japan
- Prior art keywords
- single crystal
- substrate
- semiconductor
- forming
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000013078 crystal Substances 0.000 claims description 34
- 239000000758 substrate Substances 0.000 claims description 34
- 239000004065 semiconductor Substances 0.000 claims description 31
- 238000005530 etching Methods 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 230000007704 transition Effects 0.000 claims description 7
- 238000000034 method Methods 0.000 description 20
- 239000010408 film Substances 0.000 description 18
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 17
- 230000015556 catabolic process Effects 0.000 description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000010409 thin film Substances 0.000 description 4
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
- Weting (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造法に係り、特に共通
の結晶基板上に電気的に絶縁された半導体装置を
作るための方法例えば絶縁物により絶縁され、結
晶基板に埋設された半導体単結晶島の作成（誘電
体分離半導体基板）に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device that is electrically insulated on a common crystal substrate. The present invention relates to the creation of semiconductor single crystal islands (dielectrically isolated semiconductor substrates).
従来この種の基板は、主として使用上基板の電
位を一定に固定することのできない回路、放射線
等の影響による誤動作をきらう応用や絶縁を行な
うために逆バイアス接合を用いた通常の接合分離
法では実現できない高耐圧を必要とされる半導体
装置への応用等に用いられてきた。半導体として
シリコンをまた絶縁物としてSiO2を例にとると
この種の基板は通常第１図ａ乃至第１図ｅに示す
ような方法で製造される。すなわち、まず、第１
図ａにおいて、１１は半導体装置を構成しようと
するＰまたはｎ型導電性を有するシリコン基板で
基板表面の結晶軸は（100）面となつている。１
２は通常のフオトレジスト工程で選択的にエツチ
ングされた酸化膜である。この基板をヒドラジ
ン、水酸化カリウム等のエツチング速度に結晶面
に対する異方性をもつエツチヤントで異方性エツ
チングを行なうと、第１図ｂに示した様な側面を
（111）面とするＶ溝が得られる。次にこのＶ溝部
分を全面的に酸化し（第１図ｃ）、この上部に第
１図ｄに示した様に多結晶シリコン１３を成長さ
せる。しかるのち、この基板を単結晶シリコン面
側よりエツチングないし研磨を行ない第１図ｅの
様な構造を得る。ここで１４は互いに酸化膜１５
で絶縁分離された単結晶シリコン島でありこの中
に通常の拡散プロセスにより個々のトランジス
タ、ダイオード等が作成される。 Conventionally, this type of substrate is mainly used for circuits where the potential of the substrate cannot be fixed at a constant level, for applications where malfunctions due to the effects of radiation etc. are to be avoided, and for insulation using the normal junction separation method using reverse bias junctions. It has been used in applications such as semiconductor devices that require high breakdown voltages that cannot be realized. Taking silicon as the semiconductor and SiO 2 as the insulator, this type of substrate is usually manufactured by the method shown in FIGS. 1a to 1e. That is, first, the first
In FIG. 1A, reference numeral 11 denotes a silicon substrate having P or n type conductivity, which is used to form a semiconductor device, and the crystal axis of the substrate surface is the (100) plane. 1
2 is an oxide film selectively etched by a normal photoresist process. When this substrate is anisotropically etched with an etchant such as hydrazine or potassium hydroxide whose etching rate has anisotropy with respect to the crystal plane, a V-groove with a (111) side surface as shown in Figure 1b is formed. is obtained. Next, this V-groove portion is entirely oxidized (FIG. 1c), and polycrystalline silicon 13 is grown on top of it as shown in FIG. 1d. Thereafter, this substrate is etched or polished from the single crystal silicon side to obtain a structure as shown in FIG. 1e. Here, 14 are mutually oxide films 15
It is a single-crystal silicon island insulated and isolated within which individual transistors, diodes, etc. are created by a normal diffusion process.
以上のプロセスでＶ溝の側面と単結晶表面のな
す角はシリコン単結晶の（111）面と（100）面の
なす角であるから結晶の性質上一意に決定され約
54.7゜となる。また第１図から明白であるよう
に、多結晶シリコン中に絶縁分離された単結晶シ
リコン島の深さはすべて同一となる。 In the above process, the angle between the side surface of the V-groove and the single crystal surface is the angle between the (111) plane and the (100) plane of the silicon single crystal, so it is uniquely determined by the crystal properties and is approximately
It becomes 54.7°. Further, as is clear from FIG. 1, the depths of the single-crystal silicon islands isolated in the polycrystalline silicon are all the same.
本発明の目的は、選択的エピタキシヤル成長法
を用いることにより低耐圧部分と高耐圧部分それ
ぞれが独立に必要十分な深さを有する単結晶島を
形成し、上記欠点を解決した誘電体分離半導体基
板を作成する方法を提供することにある。 An object of the present invention is to provide a dielectrically isolated semiconductor which solves the above-mentioned drawbacks by forming a single crystal island having a necessary and sufficient depth in each of a low breakdown voltage part and a high breakdown voltage part independently by using a selective epitaxial growth method. The object of the present invention is to provide a method for creating a substrate.
本発明は、例えば半導体基板上の電気的絶縁が
望まれる所に選択的に異方性エツチングによる溝
を形成する方法と、前記溝に囲まれた特定表面に
のみ選択的に基板と同一の導電型を有する半導体
単結晶を成長させる方法と、前記半導体結晶の成
長層の表面およびその側面、前記溝の表面を含む
半導体基板表面に絶縁材料の薄膜を被覆する方法
と、溝の中を含む前記絶縁薄膜上に実質的に半導
体基板と等しい熱膨張係数を有する支持体を沈積
する方法と溝内にある支持体が露出するまで半導
体基板の半導体露出面を均一に除去する方法より
なる。 The present invention relates to a method of selectively forming grooves by anisotropic etching, for example, in locations where electrical insulation is desired on a semiconductor substrate, and a method of selectively forming grooves using anisotropic etching in locations where electrical insulation is desired, and selectively forming the same conductivity as that of the substrate only on a specific surface surrounded by the grooves. a method of growing a semiconductor single crystal having a mold, a method of coating a semiconductor substrate surface including the surface of the growth layer of the semiconductor crystal, the side surfaces thereof, and the surface of the groove with a thin film of an insulating material; The method includes depositing a support having a coefficient of thermal expansion substantially equal to that of the semiconductor substrate on the insulating thin film, and uniformly removing the exposed semiconductor surface of the semiconductor substrate until the support in the groove is exposed.
次に本発明の実施例について図面を参照して説
明する。まず第２図ａの様に（100）面を有する
単結晶シリコン基板２１上にフオトレジスト工程
により選択エツチングされた酸化膜２２，２３を
作成する。ここで２２は高耐圧部分を作成する単
結晶島の底面に相当し２３は低耐圧部分の底面に
相当する。 Next, embodiments of the present invention will be described with reference to the drawings. First, as shown in FIG. 2A, selectively etched oxide films 22 and 23 are formed on a single crystal silicon substrate 21 having a (100) plane by a photoresist process. Here, 22 corresponds to the bottom surface of the single crystal island forming the high breakdown voltage section, and 23 corresponds to the bottom surface of the low breakdown voltage section.
次に第２図ｂに示すように異方性エツチングを
行ないＶ溝を作成する。続いてフオトレジスト工
程により、全面に作成した酸化膜のうち高耐圧部
分の底面に相当する部分を選択エツチングして第
２図ｃの状態を得る。ここで２４は酸化膜であ
る。次にこの基板に単結晶部分と同一の導電型を
有する単結晶シリコンをエピタキシヤル成長させ
ると、第２図ｃの酸化膜上には多結晶シリコンが
成長し同図の高耐圧部分底面に相当する酸化膜が
除去された部分には単結晶シリコンが選択的に成
長する（選択エピタキシヤル成長）。また上述２
つの領域の境界には多結晶シリコンと単結晶シリ
コンの遷移領域が形成される。ここで成長した単
結晶シリコンのエピタキシヤル層上にフオトレジ
スト工程を用いて酸化膜を残し第２図ｄの構造を
得る。ここで２５は単結晶シリコン基板２６は単
結晶シリコン基板上に選択的にエピタキシヤル成
長した単結晶層、２７は酸化膜上に成長した多結
晶シリコン層、２８は遷移領域、２９はエピタキ
シヤル成長した単結晶層上にフオトレジスト工程
の選択エツチングにより残された酸化膜である。
次に第２図ｄの構造に対し再び異方性エツチング
を行なう。多結晶層２７および遷移領域２８は結
晶に特定の方向性がないため異方性エツチングに
より除去される。一方エピタキシヤル成長による
単結晶層３０は単結晶基板３２と同一の結晶軸を
有しているため異方性エツチングにより（111）
面３１が表われてエツチング速度がきわめて遅く
なる。この状態でエツチングを停止し第２図ｆに
示した様に全面に分離を行なうための酸化膜３３
を作成し、続いて第２図ｇの様に多結晶シリコン
３４を成長させる。これの単結晶面を研磨ないし
エツチングすることにより、第２図ｈに示した最
終形状が得られる。ここで低耐圧部分を作成する
単結晶島３５の深さは第２図ｂで作成するＶ溝の
深さすなわち第２図ａにおける酸化膜２３と２２
の間隔により決定され、高耐圧部分を作成する単
結晶島３６の深さは第２図ｄにより成長させるエ
ピタキシヤル層の厚さによつて決定され、それぞ
れ独立に最適値とすることが可能である。 Next, as shown in FIG. 2b, anisotropic etching is performed to create a V-groove. Subsequently, by a photoresist process, a portion of the oxide film formed over the entire surface, which corresponds to the bottom surface of the high breakdown voltage portion, is selectively etched to obtain the state shown in FIG. 2c. Here, 24 is an oxide film. Next, when single-crystal silicon having the same conductivity type as the single-crystal part is epitaxially grown on this substrate, polycrystalline silicon grows on the oxide film shown in Figure 2c, which corresponds to the bottom of the high-voltage part in the same figure. Single crystal silicon selectively grows in the areas where the oxide film has been removed (selective epitaxial growth). Also, the above 2
A transition region between polycrystalline silicon and single crystal silicon is formed at the boundary between the two regions. A photoresist process is used to leave an oxide film on the single-crystal silicon epitaxial layer grown here to obtain the structure shown in FIG. 2d. Here, 25 is a single crystal silicon substrate 26 which is a single crystal layer selectively grown epitaxially on the single crystal silicon substrate, 27 is a polycrystalline silicon layer grown on an oxide film, 28 is a transition region, and 29 is a single crystal layer grown epitaxially on the single crystal silicon substrate. This is an oxide film left on the single crystal layer by selective etching in the photoresist process.
Next, the structure of FIG. 2d is again subjected to anisotropic etching. Polycrystalline layer 27 and transition region 28 are removed by anisotropic etching since the crystals have no specific orientation. On the other hand, since the epitaxially grown single crystal layer 30 has the same crystal axis as the single crystal substrate 32, it is etched by anisotropic etching (111).
Surface 31 appears and the etching rate becomes extremely slow. In this state, the etching is stopped and an oxide film 33 is formed on the entire surface for separation as shown in FIG.
Then, as shown in FIG. 2g, polycrystalline silicon 34 is grown. By polishing or etching the single crystal surface, the final shape shown in FIG. 2h is obtained. Here, the depth of the single-crystal island 35 forming the low breakdown voltage portion is the depth of the V-groove formed in FIG. 2b, that is, the depth of the oxide films 23 and 22 in FIG. 2a.
The depth of the single-crystal islands 36 forming the high breakdown voltage portion is determined by the thickness of the epitaxial layer grown as shown in FIG. be.
以上の実施例では半導体基板としてシリコンを
考えたが特にシリコンに限定されるものではな
い。また絶縁分離に用いられる絶縁薄膜もSiO2
に限定されずSi3N4その他とすることも可能であ
る。またこの実施例では支持体として多結晶シリ
コンを用いたが半導体素子製造時の高温に耐えか
つ半導体基板と実質的に熱膨張係数の等しい材料
であればいずれでもよい。 Although silicon was considered as the semiconductor substrate in the above embodiments, it is not particularly limited to silicon. Insulating thin films used for insulation isolation are also SiO 2
The material is not limited to Si 3 N 4 and others. Furthermore, although polycrystalline silicon is used as the support in this embodiment, any material may be used as long as it can withstand high temperatures during semiconductor device manufacturing and has a coefficient of thermal expansion substantially equal to that of the semiconductor substrate.
本発明によれば低耐圧部分を構成する単結晶島
と高耐圧部分を構成する単結晶島の深さをそれぞ
れ独立に最適値に定めることができ同一規模の半
導体装置を作成するために必要な誘電体分離半導
体基板の大きさを従来技術に比し小さくする効果
がある。 According to the present invention, the depths of the single crystal islands constituting the low breakdown voltage part and the single crystal islands constituting the high breakdown voltage part can be determined independently to the optimum values, which are necessary to create a semiconductor device of the same size. This has the effect of reducing the size of the dielectrically isolated semiconductor substrate compared to the prior art.
第１図ａ乃至第１図ｅは従来技術による半導体
装置用基板製造法を工程順に示す断面図で、この
うち第１図ａはフオトレジスト工程後の半導体基
板の断面図、第１図ｂは異方性エツチング工程後
の断面図、第１図ｃは絶縁分離酸化膜被覆後の断
面図、第１図ｄは多結晶シリコン成長後の断面
図、第１図ｅは研磨後の断面図である。第２図ａ
乃至第２図ｈは本発明の実施例を工程順に示す断
面図で、このうち第２図ａは、フオトレジスト工
程後の断面図、第２図ｂは異方性エツチング後の
断面図、第２図ｃは選択エピタキシヤル成長のた
めのフオトレジスト工程の断面図、第２図ｄは選
択エピタキシヤル成長後の断面図、第２図ｅは異
方性エツチングによる多結晶シリコンおよび遷移
領域除去後の断面図、第２図ｆは絶縁材料薄膜被
覆後の断面図、第２図ｇは支持体沈積後の断面
図、第２図ｈは研磨後の断面図である。
尚図において、１１…（100）面を表面とする
単結晶シリコン基板、１２…選択エツチングされ
た酸化膜、１３…多結晶シリコン、１４…単結晶
シリコン島、１５…絶縁分離酸化膜、２１…
（100）面を表面とする単結晶シリコン基板、２２
…高耐圧素子作成部分、２３…低耐圧素子作成部
分、２４…酸化膜、２５…単結晶シリコン基板、
２６…単結晶シリコン基板と同一の導電型をもつ
単結晶層、２７…多結晶シリコン、２８…遷移領
域、２９…異方性エツチングのための酸化膜、３
０…エピタキシヤル成長による単結晶層、３１…
（111）面、３２…単結晶シリコン基板、３３…酸
化膜、３４…多結晶シリコン、３５…低耐圧素子
用単結晶島、３６…高耐圧素子用単結晶島。
1a to 1e are cross-sectional views showing a conventional method for manufacturing a substrate for a semiconductor device in the order of steps, of which FIG. 1a is a cross-sectional view of the semiconductor substrate after the photoresist process, and FIG. 1b is Figure 1c is a cross-sectional view after the anisotropic etching process, Figure 1c is a cross-sectional view after coating with an insulating isolation oxide film, Figure 1d is a cross-sectional view after polycrystalline silicon growth, and Figure 1e is a cross-sectional view after polishing. be. Figure 2a
2h to 2h are cross-sectional views showing an embodiment of the present invention in the order of steps, of which FIG. 2a is a cross-sectional view after the photoresist process, FIG. 2b is a cross-sectional view after anisotropic etching, and FIG. Figure 2c is a cross-sectional view of the photoresist process for selective epitaxial growth, Figure 2d is a cross-sectional view after selective epitaxial growth, and Figure 2e is after polycrystalline silicon and transition region removal by anisotropic etching. 2(f) is a sectional view after coating with a thin film of insulating material, FIG. 2(g) is a sectional view after support is deposited, and FIG. 2(h) is a sectional view after polishing. In the figure, 11...single crystal silicon substrate with (100) plane as the surface, 12... selectively etched oxide film, 13... polycrystalline silicon, 14... single crystal silicon island, 15... insulating isolation oxide film, 21...
Single crystal silicon substrate with (100) plane as the surface, 22
...High voltage resistance element production part, 23...Low breakdown voltage element production part, 24...Oxide film, 25...Single crystal silicon substrate,
26... Single crystal layer having the same conductivity type as the single crystal silicon substrate, 27... Polycrystalline silicon, 28... Transition region, 29... Oxide film for anisotropic etching, 3
0...Single crystal layer by epitaxial growth, 31...
(111) plane, 32... Single crystal silicon substrate, 33... Oxide film, 34... Polycrystalline silicon, 35... Single crystal island for low breakdown voltage elements, 36... Single crystal island for high breakdown voltage elements.
Claims (1)
程と、前記基板の平担面の一部を除いた面および
前記溝の表面を第１の絶縁膜で覆う工程と、半導
体をエピタキシヤル成長させて前記基板の露出し
た平担面上に単結晶半導体層を、前記第１の絶縁
膜上に多結晶半導体層を、およびこれら単結晶お
よび多結晶半導体層を連結する遷移領域をそれぞ
れ形成する工程と、結晶異方性を利用した異方性
エツチングにより前記多結晶半導体層および前記
遷移領域を除去し、前記単結晶半導体層の表面を
前記第１の絶縁膜と連続する第２の絶縁膜で覆う
工程と、前記第１および第２の絶縁膜上に支持体
層を形成する工程と、前記単結晶半導体基板を前
記溝が形成された面とは反対の面から前記支持体
層の一部が露出するまで除去する工程とを有し、
互いに深さが異なりかつそれぞれが絶縁膜を介し
て前記支持体層に支持された複数の単結晶半導体
島領域を有する構造を得ることを特徴とする半導
体装置の製造法。1. A step of selectively forming a groove in a single crystal semiconductor substrate, a step of covering a surface of the substrate excluding a part of the flat surface and the surface of the groove with a first insulating film, and a step of epitaxially growing the semiconductor. forming a single crystal semiconductor layer on the exposed flat surface of the substrate, a polycrystalline semiconductor layer on the first insulating film, and a transition region connecting these single crystal and polycrystalline semiconductor layers. and removing the polycrystalline semiconductor layer and the transition region by anisotropic etching using crystal anisotropy, and forming a second insulating film continuous with the first insulating film on the surface of the single crystal semiconductor layer. a step of forming a support layer on the first and second insulating films; and a step of forming a support layer on the first and second insulating films; removing the part until the part is exposed,
1. A method of manufacturing a semiconductor device, comprising obtaining a structure having a plurality of single-crystal semiconductor island regions having mutually different depths and each supported by the support layer via an insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15900380A JPS5783042A (en) | 1980-11-12 | 1980-11-12 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15900380A JPS5783042A (en) | 1980-11-12 | 1980-11-12 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5783042A JPS5783042A (en) | 1982-05-24 |
| JPS6221269B2 true JPS6221269B2 (en) | 1987-05-12 |
Family
ID=15684101
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15900380A Granted JPS5783042A (en) | 1980-11-12 | 1980-11-12 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5783042A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7061375B2 (en) | 2003-03-12 | 2006-06-13 | Honda Motor Co., Ltd. | System for warning a failure to wear a seat belt |
| JP4725282B2 (en) * | 2005-10-17 | 2011-07-13 | トヨタ自動車株式会社 | Vehicle control device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5247686A (en) * | 1975-10-15 | 1977-04-15 | Toshiba Corp | Semiconductor device and process for production of same |
| JPS5563840A (en) * | 1978-11-08 | 1980-05-14 | Hitachi Ltd | Semiconductor integrated device |
-
1980
- 1980-11-12 JP JP15900380A patent/JPS5783042A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5247686A (en) * | 1975-10-15 | 1977-04-15 | Toshiba Corp | Semiconductor device and process for production of same |
| JPS5563840A (en) * | 1978-11-08 | 1980-05-14 | Hitachi Ltd | Semiconductor integrated device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5783042A (en) | 1982-05-24 |
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