JPS62200764A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS62200764A JPS62200764A JP4191286A JP4191286A JPS62200764A JP S62200764 A JPS62200764 A JP S62200764A JP 4191286 A JP4191286 A JP 4191286A JP 4191286 A JP4191286 A JP 4191286A JP S62200764 A JPS62200764 A JP S62200764A
- Authority
- JP
- Japan
- Prior art keywords
- opening
- insulating film
- region
- element region
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052710 silicon Inorganic materials 0.000 abstract description 10
- 239000010703 silicon Substances 0.000 abstract description 10
- 238000000034 method Methods 0.000 abstract description 8
- VLJQDHDVZJXNQL-UHFFFAOYSA-N 4-methyl-n-(oxomethylidene)benzenesulfonamide Chemical compound CC1=CC=C(S(=O)(=O)N=C=O)C=C1 VLJQDHDVZJXNQL-UHFFFAOYSA-N 0.000 abstract description 2
- 229910021340 platinum monosilicide Inorganic materials 0.000 abstract description 2
- 230000002265 prevention Effects 0.000 abstract 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 20
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 239000000463 material Substances 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000000992 sputter etching Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- -1 7IJ nitride Chemical class 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 150000003839 salts Chemical class 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は半導体装置及びその製造方法に係り、特にシリ
コンバイボー２トランジスタ等のエミッタ電極用コンタ
クトの構造とその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a structure of a contact for an emitter electrode of a silicon bibor 2 transistor, etc., and a method of manufacturing the same.
（従来の技術）
近年高周波半導体装置の高性能化は目覚ましくクリコン
バイポーラトランジスタ（以下トランジスタと称す）は
ベース幅の減少や浅い能動領域の形成及びパターンの微
細化等により、高性能化が図られている０そしてトラン
ジスタのエミッタ箪糧゛取り出し用コンタクトの構造は
パターンの微細化やエミッタ・ベース間の短絡による不
良原因に深く関わり、トランジスタの性能向上や製造少
留向上の重要な要素となっている○
そこで以下に従来のトランジスタのエミッタ電極取り出
し用コンタクトの構造及びその製造方法について第３図
を用いて説明する０第３図形成したシリコン基板２０表
面に二酸化シリコン膜３．窒化ンリコン膜９を順次堆積
する０次に窒化／リコン膜９上に所定のパターンを有す
るレジスト（図示せずンを形成し、このレジストをマス
クに９化ンリコン膜９をエツチングして第２の開口部］
２を形成する。次に窒化シリコン膜９をマスクにして第
２の開口部１２を通して二酸化シリコン膜３をフッ酸系
エツチング液を用いオーバーエツチングして二酸化シリ
コン膜３に第１の開口部１】を形成する０さらにイオン
圧入法を用いて第１の開口部１】内のシリコン基板２上
にエミッタ領域４を形成する。なおエミッタ領域４の周
辺部は浅く形成される。(Prior art) In recent years, the performance of high-frequency semiconductor devices has improved dramatically, and the performance of cryocon bipolar transistors (hereinafter referred to as transistors) has been improved by reducing the base width, forming a shallow active region, and miniaturizing the pattern. The structure of the contact for taking out the emitter of a transistor is closely related to the miniaturization of patterns and the causes of defects due to short circuits between the emitter and base, and is an important element for improving transistor performance and reducing manufacturing costs. ○ Therefore, the structure of a conventional contact for taking out an emitter electrode of a transistor and its manufacturing method will be explained below with reference to FIG. Next, a resist (not shown) having a predetermined pattern is formed on the nitride/recon film 9, and the silicon nitride film 9 is etched using this resist as a mask to form a second silicon nitride film 9. Aperture]
form 2. Next, using the silicon nitride film 9 as a mask, the silicon dioxide film 3 is over-etched through the second opening 12 using a hydrofluoric acid-based etching solution to form a first opening 1 in the silicon dioxide film 3. An emitter region 4 is formed on the silicon substrate 2 within the first opening 1 using ion implantation. Note that the peripheral portion of the emitter region 4 is formed shallowly.
次に第３図［ｂｌに示すように接触抵抗の低減のために
、熱処理によりｐｔ８ｉ／会５を形成する０その後エミ
ッタ篭也部１５を構成するＴ ｉ 頷６ 。Next, as shown in FIG. 3 [bl], in order to reduce the contact resistance, a heat treatment is performed to form a pt8i/contact 5, and then an emitter basket 15 is formed.
ｐｔ層７．ＡｕＩｖ８を順次形成しエミッタ電極を形成
する。pt layer7. AuIv8 is sequentially formed to form an emitter electrode.
ところがこの構造では、窒化シリコン、膜９が１ひさし
伏″′となり、第１の開口部１］が形成されているため
、エミッタ電極部１５を構成するＴｉ層６が段切れを起
こし、この段切れ部を通して、次に積層されるＰｔ層７
がエミッタ領域４０周辺部（第３図ｆｂ）のＡの部分）
の浅い部分に直接付着する。さらにその後の熱処理によ
ってエミッタ領域４の浅い部分からベース領域１へ拡散
し、エミッタ領域４とベース領域１との竹絡が起こり、
特性の低下が生じる。However, in this structure, the silicon nitride film 9 is overhanging by 1 inch and the first opening 1] is formed, so the Ti layer 6 constituting the emitter electrode section 15 is broken and this step is removed. Through the cut part, the Pt layer 7 to be laminated next
is the peripheral part of the emitter region 40 (portion A in FIG. 3 fb))
directly adheres to the shallow part of the surface. Further, due to the subsequent heat treatment, diffusion occurs from the shallow part of the emitter region 4 to the base region 1, causing entanglement between the emitter region 4 and the base region 1.
Deterioration of properties occurs.
父、第４図に示すようにエミッタ領域４のストライブ幅
を小すくシて、エミッタ・ベース間の寄生容量を低減し
、トランジスタの周波数特性の改善を目的としたエミッ
タコンタクト部の千Ｎ造を示した。この構造ではエミッ
タ領域４の端部（第４図のＢの部分）にＰｔ層が付着し
やすくなるので、エミッタ領域４とベースｌとの短絡は
さらに顕著となる。As shown in Figure 4, the emitter contact section is designed with a 1,000-N structure with the aim of reducing the stripe width of the emitter region 4, reducing the parasitic capacitance between the emitter and the base, and improving the frequency characteristics of the transistor. showed that. In this structure, the Pt layer tends to adhere to the end portion of the emitter region 4 (portion B in FIG. 4), so that the short circuit between the emitter region 4 and the base l becomes more pronounced.
（発明が解決しようとする問題点）
以上述べたように従来の半導体装置及びその製造方法で
は、半導体基板上の所定の素子領域上に形成された電極
を構成する物質が、電極形成工程において段切れを起こ
し、所定の素子領域に付着し、その後の熱処理により他
の素子領域に拡散していた。その結果素子領域間の短絡
が生じ、半導体装置の特性の低下が起った。そこで本発
明では上記の欠点を除去するもので各素子領域の短絡を
排除した半導体装置及びその製造方法を提供することを
目的とする。(Problems to be Solved by the Invention) As described above, in the conventional semiconductor device and its manufacturing method, the material constituting the electrode formed on a predetermined element region on the semiconductor substrate is It caused breakage, adhered to a predetermined device region, and spread to other device regions during subsequent heat treatment. As a result, short circuits occurred between element regions, resulting in deterioration of the characteristics of the semiconductor device. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which eliminates the above-mentioned drawbacks and eliminates short circuits in each element region.
（問題点を解決するための手段）
上記目的を達成するために本発明の半導体装置では、半
導体基板の素子領域上に第】の開口部を有した第１の絶
縁膜を設ける。父、この第１の絶縁膜の表面に第１の開
口部より小さな第２の開口部を有した第２の絶縁膜を設
ける。又第１の開口部の中に第３の開口部を有した第３
の絶縁膜を設ける。なお第３の開口部は第２の開口部と
一体化している。さらに第２及び第３の開口部を通して
半導体基板の素子領域上に電極部を接続することにより
構成される。(Means for Solving the Problems) In order to achieve the above object, in the semiconductor device of the present invention, a first insulating film having an opening of ] is provided over an element region of a semiconductor substrate. A second insulating film having a second opening smaller than the first opening is provided on the surface of the first insulating film. and a third opening having a third opening within the first opening.
An insulating film is provided. Note that the third opening is integrated with the second opening. Furthermore, it is constructed by connecting an electrode portion onto the element region of the semiconductor substrate through the second and third openings.
父上記目的を達成するために本発明の半導体装置の製造
方法では、素子領域が形成された半導体基板上に＠】の
絶縁膜を形成する。次にこの第１の絶縁膜上にエツチン
グ選択比が第１の絶縁膜より大きい第２の絶縁膜を形成
する。次に第２の開口部を第２の絶縁膜に形成する。次
に第２の絶ｈ１膜をマスクにして第１の絶縁膜をエツチ
ングすることにより、第２の開口部を含むような第１の
開口部を第１の絶縁膜に形成する。次に第１の開口部内
の半導体基板上に素子領域を形成する。次に第１の開口
部内に第３の絶縁膜を充填する。次に第２の開口部を心
して第３の絶縁膜を選択除去することにより、第３の絶
縁膜に第３の開口部を形成する０なお第３の開口部は第
２の開口部と一体化するように形成する。さらに第２及
び第３の開口部を通して半導体基板の素子領域上に一極
部を形成す為ことにより半導体装置が製造される０
（作用）
本発明の半導体装置及びその製造方法では、第】の開口
部内のＤ［定の素子領域上に形成され、第１の開口部と
一体化された第３の開口部を遇して電極が形成されるの
で、電極を構成する物質が負極形成工程において段切れ
を起こしにくくなる０又たとえ電極を構成する物質が段
切れを起こしても、所定の素子領域の端部に第３の絶縁
膜が形成されているので、段切れ部を通して！極を構成
する物質が所定の素子領域の端部に付着することはない
。したがって所定の素子領域と他の素子領域との短絡の
防止を行うことができる。In order to achieve the above object, in the method of manufacturing a semiconductor device of the present invention, an insulating film of @ is formed on a semiconductor substrate on which an element region is formed. Next, a second insulating film having a higher etching selectivity than the first insulating film is formed on the first insulating film. Next, a second opening is formed in the second insulating film. Next, by etching the first insulating film using the second insulating film as a mask, a first opening including the second opening is formed in the first insulating film. Next, an element region is formed on the semiconductor substrate within the first opening. Next, the first opening is filled with a third insulating film. Next, by selectively removing the third insulating film with the second opening in mind, a third opening is formed in the third insulating film.Note that the third opening is integral with the second opening. form so as to become Furthermore, a single pole portion is formed on the element region of the semiconductor substrate through the second and third openings, thereby manufacturing the semiconductor device. Since the electrode is formed with the third opening formed on the device region D in the opening and integrated with the first opening, the material constituting the electrode is Even if the material constituting the electrode causes a break, the third insulating film is formed at the end of the predetermined element area, so it can be easily passed through the break! The material constituting the poles does not adhere to the edges of a given device region. Therefore, it is possible to prevent a short circuit between a predetermined element region and another element region.
（実施例） 以下本発明の一つの実施例を図面を参照して説明する。(Example) An embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明を適用したシリコンバイボー２トランジ
スタのエミッタ電極の構造について述べた断面図の一部
である０第１図に示すように素子分離領域、エミッタ抵
抗部等（以上図示せず）やベース領域１及びエミッタ領
域４などの素子領域を形成したシリコン基板２などの半
導体基板上の所定の素子領域であるエミッタ領域４に第
１の開口部】１を有した二酸化シリコン膜３などの第１
の絶縁膜を設ける。又この二酸化シリコ：／膜３０表面
に第１の開口部１１より小さな第２の開口部を有した窒
化７リコン膜９などの第２の絶縁膜を設ける。又第１の
開口部１１の内部に第３の開口部を有した窒化シリコン
膜２０などの第３の絶縁膜を設ける。なお、第３の開口
部は第２の開口部と一体化している。Figure 1 is a part of a cross-sectional view showing the structure of the emitter electrode of a silicon bibor 2 transistor to which the present invention is applied.0 As shown in Figure 1, element isolation regions, emitter resistors, etc. (not shown above) A silicon dioxide film 3 or the like having a first opening 1 in an emitter region 4 which is a predetermined element region on a semiconductor substrate such as a silicon substrate 2 on which element regions such as a base region 1 and an emitter region 4 are formed. 1st
An insulating film is provided. Further, a second insulating film such as a silicon nitride film 9 having a second opening smaller than the first opening 11 is provided on the surface of the silicon dioxide film 30. Further, a third insulating film such as a silicon nitride film 20 having a third opening is provided inside the first opening 11. Note that the third opening is integrated with the second opening.
ざらに第２及び第３の開口部を通してンリコン基叡２上
のエミッタ領域４にエミッタ電極部１５を接続すること
でエミッタ電極が構成される。An emitter electrode is formed by connecting the emitter electrode portion 15 to the emitter region 4 on the silicon substrate 2 through the second and third openings.
なおエミッタを極部１５はＴｉｔ葡６．Ｐｔｌ曽７゜吠
Ａｕ層８が１１１１１槓層し、エミッタ領域４とエミッ
タ電極部１５との接続には、接触抵抗低減のためにＰ
ｔ Ｓ ｉ ＠ ５を介している。In addition, the emitter pole part 15 is Tit 6. There are 11,111 layers of Ptl 7° Au layer 8, and P is used to connect the emitter region 4 and emitter electrode part 15 to reduce contact resistance.
via tS i @5.
次に第１図に示したンリコンバイボーラトランジスタの
エミッタ電極の製造方法について述べる。第２図ｆａ）
〜Ｉｆ）はその製造方法を説明した断面図の一部であり
、第２図ｔａ＋に示すように従来技術を用いて素子分離
領域、エミッタ抵抗部寺（以上図示せず）及びペース領
域】を形成したンリコン基板２上に熱酸化法により二酸
化シリコン膜３などの第１の絶縁膜を１５００Ａ程度形
成する。さらにＬＰＣＶＤ法（Ｌｏｗ Ｐｒｅｓｓｕｒ
ｅＣｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉ ｔｉ
ｏｎ ）を用いて、二酸化７リコンＢ！Ｘ３よりエツチ
ング選択比の大きい窒化７リコン膜９などの第２の絶縁
膜を５００Ａ程度形成する。Next, a method for manufacturing the emitter electrode of the nonreconverter bipolar transistor shown in FIG. 1 will be described. Figure 2 fa)
~If) is a part of a cross-sectional view explaining the manufacturing method, and as shown in FIG. A first insulating film such as a silicon dioxide film 3 having a thickness of about 1500 Å is formed on the silicon substrate 2 thus formed by thermal oxidation. Furthermore, LPCVD method (Low Pressure
eChemical Vapor Depositi
on ) to convert 7-licon dioxide B! A second insulating film such as a silicon nitride film 9 having an etching selectivity larger than that of X3 is formed at a thickness of about 500 Å.
次に第２図（ｂ）に示すようにレジスト１０によって窒
化シリコン膜９上に所定のパターンを形成した後、レジ
スト】０をマスクにプラズマエツチング装置等を用いて
窒化ンリコン膜９をエツチングし第２の開口部１２を設
ける。Next, as shown in FIG. 2(b), after forming a predetermined pattern on the silicon nitride film 9 using a resist 10, the silicon nitride film 9 is etched using a plasma etching device or the like using the resist 10 as a mask. 2 openings 12 are provided.
次に第２図ｆｃ）に示すように窒化シリコン膜９をマス
クにして、二酸化シリコン膜２をフッ叡系エツチング液
例えばフッ化アンモニウムを用いて第２の開口部】２よ
り大きな第１の開口部１１を形成するようにオーバーエ
ツチングを行うことにより１ひさし伏″の窒化シリコン
膜が形成できる。さらにイオン注入法を用いて、第１の
開口部１１内の半導体基板上にエミッタ領域４を形成す
る。イオン注入は例えば砒素（Ａｓ）をイオン用ソース
に用い、注入エネルギーを］００ＫｅＶ、注入量を３．
５Ｘ１０ とし、アニールは例えば１０００℃、１５
分間程度行う０なおイオン注入法により形成されたエミ
ッタ領域４はその周辺部が浅くなる０
次に第２図ｔｄ）に示すように、窒化ンリコン膜９をマ
スクにして電子ビーム蒸着装置等を用いて、７リコン基
板２上のエミッタ領域１及び窒化７リコン膜９の表面上
にＴ ｉなどの金Ｍ膜を５００ Ａ ８ ［堆ｆＲＬ
テＴ ｉ＊ １６ヲ形成ｆ ル。Next, using the silicon nitride film 9 as a mask, as shown in FIG. By performing over-etching to form the first opening 11, a silicon nitride film having a height of 1" can be formed. Furthermore, an emitter region 4 is formed on the semiconductor substrate within the first opening 11 using an ion implantation method. For ion implantation, for example, arsenic (As) is used as an ion source, the implantation energy is ]00 KeV, and the implantation amount is 3.
5×10, and annealing is performed at 1000℃, 15
The emitter region 4 formed by the ion implantation method, which is carried out for about a minute, becomes shallow at its periphery.Next, as shown in FIG. Then, a gold M film such as Ti is deposited on the surface of the emitter region 1 on the silicon substrate 2 and the surface of the silicon nitride film 9 at a thickness of 500 A 8 [deposited].
TE T i * 16 formation f le.
さらにプラズマＣＶＤ装置等を用いて第１の開口部１１
の甲に窒化シ！ルコン膜を満たす０次にイオンミｌ）ン
グ装置等を用いて第２の開口部】２を通して第１の開口
部１１の中の窒化シリコン膜を選択的にエツチングする
０このようＫすることで第２図（ｅ）に示すように、第
２の開口部１２と同じ大きさで、一体化した第３の開口
部１４を有した窒化７ＩＪコン膜２０（第３の絶縁膜）
を形成する。Furthermore, the first opening 11 is formed using a plasma CVD device or the like.
Nitride on the instep! The silicon nitride film in the first opening 11 is selectively etched through the second opening 2 using an ion milling device or the like to fill the silicon film. As shown in FIG. 2(e), a 7IJ nitride film 20 (third insulating film) has an integrated third opening 14 that is the same size as the second opening 12.
form.
次に第２図（ｆ）に示すように保護膜として用いたＴ
ｉ層】６を塩醒等でエツチングを行い、エミッタ領域４
を霧出する０さらＫこのエミッタ領域４上に電子ビーム
蒸着装置等を用いて、Ｐｔ層を３００Ａ程度形成し、５
００ ’Ｏで熱処理し。Next, as shown in Fig. 2(f), T was used as a protective film.
I-layer] 6 is etched with salt etching, etc., and the emitter region 4 is etched.
A Pt layer of about 300 A is formed on this emitter region 4 using an electron beam evaporator or the like, and
Heat treated at 00'O.
てＰｔＳｉ層７を形成する。Then, a PtSi layer 7 is formed.
次に第１図に示すようにスパッタ蒸庸装置等を用いて、
電極部を構成するＩｌｌ ｉ層６．Ｐｔ層７゜Ａｕ層８
をｊ幀次槓鳩し、その後イオンミリング装置責等により
バターニングしてエミッタを極を形成する。Next, as shown in Fig. 1, using a sputter evaporation device or the like,
Ill i layer constituting the electrode part 6. Pt layer 7゜Au layer 8
The emitter is milled and then patterned using an ion milling device or the like to form an emitter pole.
以上の構成及び製造方法によれば、エミッタ領域４の端
部に窒化７す、コン［２０が形成されているので、エミ
ッタ電極部１５を構成するＴ１Ｎｌ６が電極形成時に段
切れを起しても、Ｐｔ層７がエミッタ領域の浅い部分及
び端部に付着することかなく、熱処理によるエミッタ・
ベース間の短絡が発生しない。According to the above configuration and manufacturing method, since the nitrided capacitor 20 is formed at the end of the emitter region 4, even if the T1N16 constituting the emitter electrode section 15 is broken during electrode formation, , without the Pt layer 7 adhering to the shallow parts and edges of the emitter region, the emitter layer 7 can be removed by heat treatment.
No short circuit between bases.
父、窒化ンリコン膜２０がエミッタ領域］へのＰｔｒｆ
４７の付着を防止するので、ストライプ幅の小さなエミ
ッタ領域４を形成し、エミッタ領域４とベース領域１と
の間の寄生容量を低減し、トランジスタの周波数特性を
向上させることができる０
なお、上記実施例では第３図の絶縁膜である窒化シリコ
ン膜２０をエミッタ領域４や窒化シリコン膜９上に堆積
する工程の前にそれらの表面に゛１゛ｉ層１６を形成し
ている。これはイオンミリング装置等を用いて窒化シリ
コン膜２０をエツチングする際、反応ガスとして、アル
ゴン（Ａ「）と酸素（０２）との混合気体を用いると、
１゛ｉ層１６の表面が酸化して、エツチング速度が極め
て遅くなり、イオンビームによるエツチングやダメージ
からエミッタ領域４を防ぐ保＃ｉＩｍとなる。又、保睡
膜としてのＴｉＮ４１６の酸化物は、窒化シリコン膜２
０よりエツチング選択比が極めて大きいから、薄い層で
よい。したがってＴｉ層１６が厚いために第１の開口部
１１のエミッタ領域４の端部への窒化シリコン膜の充填
が不十分になることはない０又、保護膜はＴｉ層】６以
外に、酸化性の大きい全極、たとえばｋｌ、Ｎｉ等でも
同様な効果が得られる０以上本発明の一実施例としてシ
リコンバイポーラトランジスタのエミッタ電碓取り出Ｌ
［コンタクトの構造及び製造方法について説明したが、
これに限定されるものではなく、集積回路においても本
発明の示す構造、製造方法が適用でき、同様の効果が期
待できるのは明らかである０
〔発明の効果〕
以上述べたように本発明によれば、第１の開口部内の半
導体基板上に形成された所定の素子領域の端部に第３の
絶縁膜が形成されている。father, silicon nitride film 20 is the emitter region]
47, it is possible to form the emitter region 4 with a small stripe width, reduce the parasitic capacitance between the emitter region 4 and the base region 1, and improve the frequency characteristics of the transistor. In the embodiment, before the process of depositing the silicon nitride film 20, which is an insulating film, on the emitter region 4 and the silicon nitride film 9 shown in FIG. 3, the 1i layer 16 is formed on the surfaces thereof. This is because when etching the silicon nitride film 20 using an ion milling device or the like, if a mixed gas of argon (A') and oxygen (02) is used as the reactive gas,
The surface of the 1.i layer 16 is oxidized, the etching rate becomes extremely slow, and the emitter region 4 is protected from etching and damage by the ion beam. In addition, the oxide of TiN416 as a sleep retention film is the silicon nitride film 2.
Since the etching selectivity is much higher than that of 0, a thin layer is sufficient. Therefore, since the Ti layer 16 is thick, the filling of the silicon nitride film to the end of the emitter region 4 of the first opening 11 will not be insufficient. A similar effect can be obtained even with all poles having a large polarity, such as kl, Ni, etc. 0 or more As an embodiment of the present invention, the emitter electrode L of a silicon bipolar transistor is used.
[The structure and manufacturing method of the contact was explained, but
It is clear that the structure and manufacturing method of the present invention can be applied to integrated circuits, and similar effects can be expected.0 [Effects of the Invention] As described above, the present invention According to this method, a third insulating film is formed at an end of a predetermined element region formed on a semiconductor substrate within a first opening.
したがって所定の素子領域に接続した’を極部を形成す
る物質が段切れにより所定の素子阻域へ付層することが
ないので、素子領域間の短絡が起らず特性の低下が生じ
ない。Therefore, the material forming the pole portion connected to a predetermined element region is not deposited in the predetermined device blocking region due to step breakage, so that short circuits between the device regions do not occur and the characteristics do not deteriorate.
第１図は本発明による半導体装置の構造断面図、第２図
ｆａ）〜げ）は本発明による半導体装１ｔの各工程にお
ける構造断面図、第３図１ａ）、 （ｂ）及び第４図は
従来の半導体装置の各工程における構造断面図である。
】・・・ペース領域、２・・・半導体基板、３・・・二
酸化ンリコン膜、４・・・エミッタ領域、９・・・窒化
７リコン膜、１１・・・第１の開口部、１２・・・＄２
の開口部、】４・・・第３の開口部、１５・・・エミッ
タ電極部、１６・・・Ｔｉｌ、２０・・窒化シリコン膜
。
代理人 づｆ理士 則 近 憲 右
同 竹 花 喜久男
第１図
１２図FIG. 1 is a structural cross-sectional view of a semiconductor device according to the present invention, FIG. 1A and 1B are structural cross-sectional views at each step of a conventional semiconductor device. ]...Pace region, 2...Semiconductor substrate, 3...Licon dioxide film, 4...Emitter region, 9...Licon nitride film, 11...First opening, 12.・・・$2
4. Third opening, 15. Emitter electrode portion, 16. Til, 20. Silicon nitride film. Agent Zuf Physician Nori Chika Kikuo Takehana Figure 1 Figure 12
Claims (3)
前記素子領域の中の所定の領域に第１の開口部を有する
第１の絶縁膜と、この第１の絶縁膜の表面に設けられ、
前記第１の開口部より小さな第２の開口部を前記第１の
開口部上に有した第２の絶縁膜と、前記第１の開口部内
に設けられ、前記第２の開口部と一体化した第３の開口
部を有した第３の絶縁膜と、前記第２及び第３の開口部
を通して前記所定の素子領域に接続した電極部とを具備
することを特徴とする半導体装置。(1) Provided on a semiconductor substrate on which an element region is formed,
a first insulating film having a first opening in a predetermined region in the element region; provided on a surface of the first insulating film;
a second insulating film having a second opening smaller than the first opening above the first opening; and a second insulating film provided within the first opening and integrated with the second opening. A semiconductor device comprising: a third insulating film having a third opening; and an electrode portion connected to the predetermined element region through the second and third openings.
膜を形成する工程と、この第１の絶縁膜上にエッチング
選択比が前記第１の絶縁膜より大きい第２の絶縁膜を形
成する工程と、この第２の絶縁膜に所望の第２の開口部
を形成する工程と、前記第１の絶縁膜に前記第２の絶縁
膜をマスクにして前記第１の絶縁膜をエッチングするこ
とにより前記第２の開口部を含むような第１の開口部を
形成する工程と、この第１の開口部内の前記半導体基板
上に所定の素子領域を形成する工程と、前記第１の開口
部に第３の絶縁膜を充填する工程と、前記第２の開口部
を通して前記第３の絶縁膜を選択除去することにより、
前記第３の絶縁膜に前記第２の開口部と一体化した第３
の開口部を形成する工程と、前記第２及び第３の開口部
を通して前記所定の素子領域上に電極部を形成する工程
とを含むことを特徴とする半導体装置の製造方法。(2) forming a first insulating film on the semiconductor substrate on which the element region is formed; and forming a second insulating film with a higher etching selectivity than the first insulating film on the first insulating film; forming a desired second opening in the second insulating film; and etching the first insulating film using the second insulating film as a mask. forming a first opening including the second opening, forming a predetermined element region on the semiconductor substrate within the first opening; By filling the opening with a third insulating film and selectively removing the third insulating film through the second opening,
a third insulating film integrated with the second opening;
A method of manufacturing a semiconductor device, comprising: forming an opening; and forming an electrode portion on the predetermined element region through the second and third openings.
工程前に前記第２の開口部を通して前記所定の素子領域
上に金属膜を堆積する工程と、前記電極部を形成する前
に前記金属膜を除去する工程とを含むことを特徴とする
特許請求の範囲第（２）項記載の半導体装置の製造方法
。(3) Depositing a metal film on the predetermined element region through the second opening before filling the first opening with the third insulating film, and forming the electrode portion. The method of manufacturing a semiconductor device according to claim 2, further comprising the step of removing the metal film before the step of removing the metal film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4191286A JPS62200764A (en) | 1986-02-28 | 1986-02-28 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4191286A JPS62200764A (en) | 1986-02-28 | 1986-02-28 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62200764A true JPS62200764A (en) | 1987-09-04 |
Family
ID=12621475
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4191286A Pending JPS62200764A (en) | 1986-02-28 | 1986-02-28 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62200764A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5679982A (en) * | 1993-02-24 | 1997-10-21 | Intel Corporation | Barrier against metal diffusion |
-
1986
- 1986-02-28 JP JP4191286A patent/JPS62200764A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5679982A (en) * | 1993-02-24 | 1997-10-21 | Intel Corporation | Barrier against metal diffusion |
| US5783483A (en) * | 1993-02-24 | 1998-07-21 | Intel Corporation | Method of fabricating a barrier against metal diffusion |
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