JPS62199119A - Phase locked loop circuit - Google Patents
Phase locked loop circuitInfo
- Publication number
- JPS62199119A JPS62199119A JP61040413A JP4041386A JPS62199119A JP S62199119 A JPS62199119 A JP S62199119A JP 61040413 A JP61040413 A JP 61040413A JP 4041386 A JP4041386 A JP 4041386A JP S62199119 A JPS62199119 A JP S62199119A
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- JP
- Japan
- Prior art keywords
- signal
- phase
- output
- pull
- phase difference
- Prior art date
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- 238000001514 detection method Methods 0.000 claims abstract description 27
- 230000003247 decreasing effect Effects 0.000 claims abstract 2
- 230000001360 synchronised effect Effects 0.000 claims description 11
- 230000001629 suppression Effects 0.000 abstract description 16
- 238000000034 method Methods 0.000 abstract description 15
- 238000006243 chemical reaction Methods 0.000 abstract description 6
- 230000007423 decrease Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 101100464782 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) CMP2 gene Proteins 0.000 description 1
- 101100464779 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) CNA1 gene Proteins 0.000 description 1
- 230000035559 beat frequency Effects 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
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- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は位相同期回路に係り、特にＰＣＭ通信のタイミ
ング抽出等に好適な位相同期回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase synchronized circuit, and particularly to a phase synchronized circuit suitable for timing extraction of PCM communications.
ＰＣＭ通信のタイミング抽出等に適用する位相同期回路
（以下、ＰＬＬと記述する）は、信号入力時には応答を
速くして高速に入力信号を引込み。A phase-locked circuit (hereinafter referred to as PLL), which is applied to timing extraction in PCM communication, responds quickly when a signal is input and pulls in the input signal at high speed.
引込後は雑音帯域を小さくして入カシツタを抑圧するこ
とが必要である。しかし、一般にＰＬＬの引込み特性と
ジッタ抑圧特性は相反する性質をもっている。すなわち
、高速引込みのためにループフィルタの時定数を小さく
すると、雑音帯域は大きくなりジッタ抑圧特性が劣化す
る。After pulling in, it is necessary to reduce the noise band to suppress input ivy. However, the pull-in characteristic and jitter suppression characteristic of a PLL generally have contradictory properties. That is, if the time constant of the loop filter is made small for high-speed pull-in, the noise band becomes large and the jitter suppression characteristics deteriorate.
この問題に対処するための従来のＰＬＬとしては、特公
昭５９−１２０４９号に記載のように、２つの時定数回
路を設け、２つの入力信号と電圧制御発掘器（以下ｖＣ
Ｏと略す）の周波数の差が一定値以上の場合にフィルタ
の時定数を短縮するように切り換えるものがあった。ま
た、特開昭５９−２０２７３６号に記載のものでは、Ｐ
ＬＬが同期しているか否かを検出する検出器を位相比較
器の出力側に設け、非同期状態である時にはループフィ
ルタの時定数を小さくするようにしている。As described in Japanese Patent Publication No. 59-12049, a conventional PLL to deal with this problem has two time constant circuits, two input signals and a voltage control excavator (hereinafter referred to as vC).
Some filters switch to shorten the time constant of the filter when the difference in frequency between the filters (abbreviated as O) is equal to or greater than a certain value. Moreover, in the one described in JP-A No. 59-202736, P
A detector for detecting whether LL is synchronized is provided on the output side of the phase comparator, and when it is in an asynchronous state, the time constant of the loop filter is made small.
〔発明が解決しようとしている問題点〕前述した特公昭
５９−１２０４９号に記載のものでは、入力信号の周波
数とｖＣＯの自走周波数（入力制御電圧０のときの発振
周波数）とが大幅に異なっているときに始めてループフ
ィルタの時定数を切換えるものであり、一方、特開昭５
９−２０２７３６に記載のものでは、ＶＣＯが入力信号
に同期していないときにループフィルタの時定数を切換
えている。[Problems to be solved by the invention] In the device described in the aforementioned Japanese Patent Publication No. 59-12049, the frequency of the input signal and the free-running frequency of the vCO (oscillation frequency when the input control voltage is 0) are significantly different. The time constant of the loop filter is switched only when the
In the method described in No. 9-202736, the time constant of the loop filter is switched when the VCO is not synchronized with the input signal.
これらのいずれによっても、同期はずれ状態に於る引込
み時間は短縮されるが、ＰＬＬの引込み過程は、ＰＬＬ
が入力信号に同期した後の、入力信号とｖＣｏ出力信号
の位相差が所定値以下に減少する迄の過程も含んでいて
、このための所要時間も短いことが望まれる。しかし、
上記従来技術によると、前者では入力とｖＣＯの周波数
差が所定値以下となったときより後の、後者ではＰＬＬ
が入力と同期状態となったときより後の引込み過程では
、ジッタ抑圧に適した狭いループ帯域幅に切換えられて
いてこのための引込み時間を十分小さくできないという
欠点があった。Both of these methods shorten the pull-in time in the out-of-synchronization state, but the PLL pull-in process
It also includes a process in which the phase difference between the input signal and the vCo output signal is reduced to a predetermined value or less after it is synchronized with the input signal, and it is desirable that the time required for this process be short. but,
According to the above conventional technology, in the former case, after the frequency difference between the input and vCO becomes equal to or less than a predetermined value, in the latter case, the PLL
In the pull-in process after the input becomes synchronized with the input, the loop bandwidth is switched to a narrow loop bandwidth suitable for jitter suppression, and the pull-in time for this purpose cannot be made sufficiently small.
本発明の目的は、ＰＬＬが入力信号に同期しかつ位相差
がある一定値以下になるまで高速に引込みを行うように
することによって引込み時間を大幅に短縮でき、かつジ
ッタ抑圧特性のよい位相同期回路を提供するにある。An object of the present invention is to provide phase synchronization with good jitter suppression characteristics, which can significantly shorten the pull-in time by synchronizing the PLL with the input signal and performing pull-in at high speed until the phase difference becomes less than a certain value. To provide the circuit.
上記目的は、周波数引込みが終ったか否かを検出する周
波数引込み検出回路と、位相差が所定値以下か否かを検
出する位相差検出器と、これらによってＰＬＬが入力信
号に同期していてかつ位相差が所定値以下になっている
ことが検出された時にループフィルタの時定数の切り換
え信号を出力するモード制御回路を設けることにより達
せられる。The above purpose is to provide a frequency pull-in detection circuit that detects whether frequency pull-in is completed, a phase difference detector that detects whether the phase difference is less than or equal to a predetermined value, and a phase difference detector that detects whether the PLL is synchronized with the input signal. This can be achieved by providing a mode control circuit that outputs a switching signal for the time constant of the loop filter when it is detected that the phase difference is less than or equal to a predetermined value.
上記の手段によると、モード制御回路は、ＰＬＬが同期
する迄の周波数引込み過程を終り、更に位相差が所定値
以下となる位相同期過程のほぼ終了時点までは高速引込
み状態となるようにループフィルタの時定数を小さい値
とするので、ジッタ抑圧状態に切り換わる時点の位相差
は十分小さく１、引込みに要する時間を非常に短くでき
る。しかも引込後はループフィルタの時定数を大きくし
高ジッタ抑圧が可能なのは従来と同じである。According to the above means, the mode control circuit controls the loop filter so that the frequency pull-in process is completed until the PLL is synchronized, and the loop filter is kept in a high-speed pull-in state until the phase difference becomes equal to or less than a predetermined value and almost the end of the phase lock process. Since the time constant of is set to a small value, the phase difference at the time of switching to the jitter suppression state is sufficiently small 1, and the time required for pull-in can be extremely shortened. Moreover, after the pull-in, the time constant of the loop filter is increased to suppress high jitter, as in the conventional case.
以下１本発明の一実施例を第１図により説明する。第１
図において、位相比較器１００は入力信号ｆｉ と出力
信号ｆｏを入力とし、位相差信号１０１．１０２を出力
する６位相差信号１０１は変換利得Ｇｘｔ Ｇｘ （
Ｇｘ＞Ｇｚ）を持ち動作モード信号６０１によって制御
できる。即ち、引き込み時はＧ１を選択し、引き込み完
了後のジッタ抑制時にはＧ２を選択する１位相差信号１
０１は抵抗Ｒ８を介してループフィルタ２００へ入力さ
れる。ループフィルタ２００はコンデンサＣと抵抗Ｒｚ
、Ｒｚで構成され、抵抗Ｒ２は動作モード信号６０１
で制御されるスイッチＳＷ１でショートできる。ＶＣＯ
３００はループフィルタの出力信号２０１に応じた周波
数信号ｆＯを出力する。An embodiment of the present invention will be described below with reference to FIG. 1st
In the figure, a phase comparator 100 receives an input signal fi and an output signal fo, and six phase difference signals 101 outputting phase difference signals 101 and 102 have a conversion gain Gxt Gx (
Gx>Gz) and can be controlled by the operation mode signal 601. That is, 1 phase difference signal 1 selects G1 when pulling in, and selects G2 when suppressing jitter after completing pulling.
01 is input to the loop filter 200 via the resistor R8. The loop filter 200 includes a capacitor C and a resistor Rz
, Rz, and the resistor R2 receives the operation mode signal 601.
It can be short-circuited with switch SW1 controlled by . VCO
300 outputs a frequency signal fO according to the output signal 201 of the loop filter.
周波数引込み検出回路４００は位相差信号１０２がある
一定値以下となる状態がある一定期間経続したときに周
波数を引込んだと判定し、周波数引込み信号４０１を１
にする。フィルタ電流検出回路５００は抵抗Ｒ８の両端
電圧を入力として位相差を検出するもので、この両端電
圧の絶対値がある一定値以下になったときにフィルタ電
流検出信号５０１を１にする。モード制御回路６００は
周波数引込み信号４０１とフィルタ電流検出信号５０１
の論理積をアンドゲート６１０でとり、モード切換信号
６０１を出力する。The frequency pull-in detection circuit 400 determines that the frequency has been pulled in when the phase difference signal 102 remains below a certain value for a certain period of time, and sets the frequency pull-in signal 401 to 1.
Make it. The filter current detection circuit 500 detects a phase difference by inputting the voltage across the resistor R8, and sets the filter current detection signal 501 to 1 when the absolute value of the voltage across the resistor R8 becomes equal to or less than a certain value. The mode control circuit 600 includes a frequency pull-in signal 401 and a filter current detection signal 501.
An AND gate 610 performs a logical AND operation, and outputs a mode switching signal 601.
以上の各構成要素の詳細を次に説明する。第２図は位相
比較器１００の実施例を示すもので、第３図はその動作
のタイミングチャートである。これらの図に於て、ＶＣ
Ｏの出力信号ｆｏは連続したクロック信号であり（デユ
ーティ５０％）、入力信号ｆ１の基本周波数の２倍の周
波数である。Details of each of the above components will be explained next. FIG. 2 shows an embodiment of the phase comparator 100, and FIG. 3 is a timing chart of its operation. In these figures, VC
The output signal fo of O is a continuous clock signal (duty: 50%) and has a frequency twice the fundamental frequency of the input signal f1.
まずフリップフロップＦＦＩのＱ出力は入力信号！、の
立上りのタイミングでＦＦＩのＤ入力データをセットす
るが、Ｄ入力は常に１なのでこのとき必ず１となる。フ
リップフロップＦＦ２のＱ出力は出力信号ｆｏの立下り
のタイミングでＤ入力、即ちフリップフロップＦＦＩの
Ｑ出力１をセットするのでこのとき１となる。フリップ
フロップＦＦ２のＱ出力が１にセットされるとフリップ
フロップＦＦ２のＱ出力はＯとなり、これによってフリ
ップフロップＦＦＩはリセットされる。したがってフリ
ップフロップＦＦＩのＱ出力、つまり。First, the Q output of flip-flop FFI is an input signal! The D input data of the FFI is set at the rising edge of , but since the D input is always 1, it is always 1 at this time. The Q output of the flip-flop FF2 becomes 1 at this time because the D input, ie, the Q output 1 of the flip-flop FFI, is set at the falling timing of the output signal fo. When the Q output of the flip-flop FF2 is set to 1, the Q output of the flip-flop FF2 becomes O, thereby resetting the flip-flop FFI. Therefore, the Q output of flip-flop FFI, ie.
パルス信号Ｔ１のパルス幅は信号ｆ１と信号ｆ。The pulse width of the pulse signal T1 is the signal f1 and the signal f.
の立上りタイミング差ΔＴに信号ｆｏの周期の１７２に
相当するτを加えた値ｔ１となる。また。The value t1 is obtained by adding τ corresponding to 172 of the period of the signal fo to the rise timing difference ΔT of the signal fo. Also.
パルス信号ＴｘはブリップフロップＦＦ２のＱ出力と信
号ｆｏを反転した信号との論理積（アンドゲートＡＮＤ
１出力）であるので、このパルス幅は信号ｆｏの１／２
周期τとなる。したがって、入力信号ｆ、と出力信号ｆ
ｏの立上りタイミングの差Δｒは、パルス信号Ｔｔ 、
Ｔｚのパルス幅の差（ΔＴ＋で）−τ＝ΔＴで与えられ
る。サンプルパルスＴｇは、フリップフロップＦＦ２の
Ｑ出力と信号ｆｏとの論理積（アンドゲートＡＮＤ２出
力）で与えられ、パルス信号Ｔｒ 、Ｔｚにオーバーラ
ツプしない波形が得られる。The pulse signal Tx is a logical product (AND gate AND) of the Q output of the flip-flop FF2 and a signal obtained by inverting the signal fo.
1 output), this pulse width is 1/2 of the signal fo.
The period is τ. Therefore, the input signal f, and the output signal f
The difference Δr in the rising timing of o is the pulse signal Tt,
The difference in pulse width of Tz (in ΔT+) is given by −τ=ΔT. The sample pulse Tg is given by the AND (AND gate AND2 output) of the Q output of the flip-flop FF2 and the signal fo, and a waveform that does not overlap with the pulse signals Tr and Tz is obtained.
次に、上記のパルス信号Ｔｚ 、Ｔｔのパルス幅の差を
電流に変換する部分について述べる。カレントミラーを
構成するトランジスタＱ１０１〜Ｑ１０５のゲート面積
は、トランジスタＱ１’０３が他のに倍で、他は全て等
しくし、一方カレントミラーを構成するトランジスタＱ
１１１〜Ｑ１１５のゲート面積は、トランジスタＱ１１
４が他のに倍で、他は全て等しいとする。ここで、パル
スＴ１が１のときはアナログスイッチ５１０１が閉じら
れ、積分器を構成している反転アンプＡＭＰの出力ｖ１
は上昇し、パルスＴ１が１のときはスイッチ３１０２が
閉じるので出力ｖ１は下がる。この結果、反転アンプＡ
ＭＰの出力ｖ１の変化分ΔＶｌは次式となる。Next, a section for converting the difference in pulse width between the pulse signals Tz and Tt into a current will be described. The gate area of the transistors Q101 to Q105 forming the current mirror is that transistor Q1'03 is twice as large as the other transistors, all other things being equal, and transistor Q1'03 forming the current mirror is
The gate area of 111 to Q115 is the same as that of transistor Q11.
Assume that 4 is twice as much as the other, and all else is equal. Here, when the pulse T1 is 1, the analog switch 5101 is closed, and the output v1 of the inverting amplifier AMP constituting the integrator
increases, and when pulse T1 is 1, switch 3102 closes, so output v1 decreases. As a result, the inverting amplifier A
The variation ΔVl in the MP output v1 is expressed by the following equation.
ｌｏｔ
ここで、τ＋ΔＴ、τは前述したパルス信号Ｔｚ 、Ｔ
ｚのパルス幅であり、Ｉｔ、ｔＩｚは各カレントミラー
回路の電流、Ｃ１０１はコンデンサＣ１０１の容量であ
る。このΔｖ１はスイッチ８１０３とコンデンサＣｌＯ
２で構成されるサンプルホールド回路に於て、サンプル
パルスＴｓでサンプリングされホールドされる。この結
果、第３図Ｖｚに示すようにリップルが除去される。サ
ンプルホールド回路の出力ｖ２は、トランジスタＱ１０
６と抵抗Ｒ１０１で構成されるＶ／Ｉ変換回路で電流工
２に変換される。この結果、Δｖ１が増加するとＶｚ、
従ってＩ２が増加し、Ｉｚが増加すると（１）式からΔ
ＶＺは減少する。この結果、パルス信号Ｔ１ｅ Ｔｚに
よる積分動作が繰り返されると（１）式のΔｖ１が零に
なるよう動作し、平衡条件は次式となる。lot Here, τ+ΔT, τ are the aforementioned pulse signals Tz, T
It is the pulse width of z, It and tIz are the currents of each current mirror circuit, and C101 is the capacitance of the capacitor C101. This Δv1 is the difference between the switch 8103 and the capacitor ClO.
2, the sample pulse Ts is used to sample and hold the sample pulse Ts. As a result, ripples are removed as shown in FIG. 3 Vz. The output v2 of the sample and hold circuit is the transistor Q10.
6 and a resistor R101, it is converted into a current generator 2. As a result, when Δv1 increases, Vz,
Therefore, when I2 increases and Iz increases, Δ
VZ decreases. As a result, when the integral operation by the pulse signals T1e Tz is repeated, the operation is performed so that Δv1 in equation (1) becomes zero, and the equilibrium condition becomes the following equation.
Ｔｌ ｅ、Ｉｘ ＝Ｔｚ ｗ Ｉｚ −（
２）これより、スイッチ５１０４が開いているときの位
相差信号１０１の電流及び位相差信号１０２の電流ｌ５
（ＯＦＦ）は次式で示される。Tl e, Ix = Tz w Iz −(
2) From this, the current of the phase difference signal 101 and the current l5 of the phase difference signal 102 when the switch 5104 is open
(OFF) is expressed by the following equation.
Ｔ ｚ Ｔ ｘ
・・・・・・ （３）
又、スイッチ５１０４が閉じた時の位相差信号１０１の
電流Ｉｚ （ＯＮ）は次式となる。T z T x (3) Further, the current Iz (ON) of the phase difference signal 101 when the switch 5104 is closed is expressed by the following equation.
（３）、（４）式より明らかなように９位相差信号１０
１，１０２はパルス信号Ｔ１ 、’ｒｚのパルス幅の差
Δψに比例した電流となって信号ｆ。As is clear from equations (3) and (4), 9 phase difference signals 10
1, 102 is a current proportional to the difference Δψ between the pulse widths of the pulse signals T1 and 'rz, resulting in a signal f.
とｆｏの位相を検出できる。更に、動作モード信号６０
１によるスイッチ５１０４のオンオフによって信号１０
１のレベル、すなわちこの信号の変換利得が変化する。The phase of and fo can be detected. Furthermore, the operation mode signal 60
The signal 10 is turned on and off by turning on and off the switch 5104 by
1 level, that is, the conversion gain of this signal changes.
第４図は周波数引込み検出回路４００の実施例を示すも
ので、第５図はその動作タイミングチャートである。こ
れらの図に於て、位相信号１０２（電流）は信号ｆｉ
とｆｏの位相差ΔＴに比例するので、抵抗４２１と４２
２の接続点の電圧Ｖφもこの位相差に比例する。コンパ
レータ４３０の出力ＣＭＰ１はＶφが基準電圧Ｖ ｒ
ｘよりも大きい時に１となり、コンパレータ４４０の出
力ＣＭＰ２はＶφが基準電圧ＶｒＬよりも小さい時に１
となる。FIG. 4 shows an embodiment of the frequency pull-in detection circuit 400, and FIG. 5 is an operation timing chart thereof. In these figures, the phase signal 102 (current) is the signal fi
Since it is proportional to the phase difference ΔT between and fo, the resistors 421 and 42
The voltage Vφ at the connection point between the two is also proportional to this phase difference. The output CMP1 of the comparator 430 has Vφ as the reference voltage V r
It becomes 1 when it is larger than x, and the output CMP2 of the comparator 440 becomes 1 when Vφ is smaller than the reference voltage VrL.
becomes.
ノアゲート４５０の出力ττはＣＭＰＩ又はＣＭＰ ２
が１のときＯとなり、カウンタ４７０をリセットする。The output ττ of the NOR gate 450 is CMPI or CMP 2
When is 1, it becomes O, and the counter 470 is reset.
カウンタ４７０はＣＬが１でｎビットの出力Ｑ、がＯの
とき、出力信号ｆｏのパルスをカウントし、Ｑ、が１に
なるとカウントを停止する。The counter 470 counts the pulses of the output signal fo when CL is 1 and the n-bit output Q is O, and stops counting when Q becomes 1.
したがって、カウンタ４７０の計数値Ｎは３でか１のと
き時間とともに増加し、ＣＬが０になると０となる。Ｃ
Ｌが１となる期間がカウンタの計数値が２ｎになるまで
継続するとＱ、は１となり。Therefore, the count value N of the counter 470 increases with time when it is 3 or 1, and becomes 0 when CL becomes 0. C
If the period in which L is 1 continues until the count value of the counter reaches 2n, Q becomes 1.
カウンタの計数を停止する。ところで１周波数引込み過
程ではＣＬが１となる期間が短く、引込み後は１を継続
する。したがって、カウンタ４７０の計数値が２″にな
るまでの期間を、周波数引込み過程でＣＬが１となる期
間以上に選べば、カウンタ４７０の出力Ｑ、で周波数引
込みを検出できる。Stops counter counting. By the way, in the 1-frequency pull-in process, the period during which CL is 1 is short, and it continues to be 1 after the pull-in. Therefore, if the period until the count value of the counter 470 reaches 2'' is selected to be longer than the period during which CL becomes 1 in the frequency pulling process, frequency pulling can be detected by the output Q of the counter 470.
以上の様に構成した第１図の実施例の動作を第６図に示
す動作波形により説明する。同図は引き込み同期過程に
おける信号ｆ、と信号ｆｏの位相差Δでの変化及びこの
時の各信号を示したものである。ＰＬＬは位相差が一π
〜＋πの間を繰り返し変化する周波数駆込み過程と、位
相差が−πからぼぼ０に整定する位相同期過程を経過し
て入力信号を引込む、この同期過程における周波数引込
み信号４０１は、位相差・ΔＴか周波数引込検出位置以
下になった状態が時間μの間経続した時刻ｔ２に１にな
る。ここで、時間μは入出力信号のビート周波数の周期
以上の値で第４図で説明したものである。The operation of the embodiment of FIG. 1 constructed as above will be explained with reference to the operation waveforms shown in FIG. 6. This figure shows changes in the phase difference Δ between the signal f and the signal fo during the pull-in synchronization process, and each signal at this time. PLL has a phase difference of 1π
The frequency pull-in signal 401 in this synchronization process, in which the input signal is pulled through a frequency pull-in process that repeatedly changes between ~+π and a phase lock process in which the phase difference settles from -π to approximately 0, is generated by the phase difference ΔT. It becomes 1 at time t2 when the state in which the frequency is lower than the frequency pull-in detection position continues for a time μ. Here, the time μ is a value greater than or equal to the period of the beat frequency of the input/output signal, and is the value explained in FIG. 4.
フィルタ電流検出信号５０１は、第６図の位相差ΔＴ（
相当の電流）が同図のフィルタ電流検出等価位相以下と
なったとき１となる。ここで検出するフィルタ電流の値
は安定に検出できる範囲で小さいほどよい。The filter current detection signal 501 has a phase difference ΔT (
It becomes 1 when the corresponding current) becomes equal to or less than the filter current detection equivalent phase in the same figure. The value of the filter current detected here is preferably as small as possible within a stable detection range.
モード制御信号６０１は、周波数引込信号４０１とフィ
ルタ電流検出信号５０１の論理積であり周波数を引込み
、かつフィルタ電流が十分小さい値になった時点で１と
なる。このモード制御信号６０１が１になると１位相比
較器１００の位相信号出力１０１の変換利得を下げると
ともに、ループフィルタ２００のスイッチＳＷＩを閉じ
、高速引込状態から高ジッタ抑圧状態に切り換える。The mode control signal 601 is the AND of the frequency pull-in signal 401 and the filter current detection signal 501, and becomes 1 when the frequency is pulled in and the filter current reaches a sufficiently small value. When this mode control signal 601 becomes 1, the conversion gain of the phase signal output 101 of the 1-phase comparator 100 is lowered, the switch SWI of the loop filter 200 is closed, and the high-speed pull-in state is switched to the high-jitter suppression state.
以上のように、動作モードはフィルタ電流が微小値の点
で切り換えられるので、位相比較器１００の変換利得や
ループフィルタの抵抗値を切り換えてもＶＣＯ３００の
入力信号の変化がなく、これに大きな外乱を与えること
がないから、引込状態を継続できる。As described above, since the operation mode is switched at a point where the filter current is a minute value, there is no change in the input signal of the VCO 300 even if the conversion gain of the phase comparator 100 or the resistance value of the loop filter is switched. Since it does not give any negative feedback, it is possible to maintain a withdrawn state.
以上の一実施例によれば、周波数を引込みかつフィルタ
の電流値が十分小さくなったときに、ＰＬＬの動作を高
速引込み状態から高ジッタ抑圧状態に切り換えるので、
引込み時間が高速引込み状態の特性のみで決定でき、高
速引込み特性を確保したまま、ジッダ抑圧特性を更に向
上できる。According to the above embodiment, when the frequency is pulled in and the filter current value becomes sufficiently small, the operation of the PLL is switched from the high-speed pulling state to the high jitter suppression state.
The pull-in time can be determined only by the characteristics of the high-speed pull-in state, and the jitter suppression characteristics can be further improved while maintaining the high-speed pull-in characteristics.
なお、第１図の実施例ではモード制御信号６０１で位相
比較器１００の変換利得とループフィルタ２００の抵抗
値の双方を制御しているが、これは。In the embodiment shown in FIG. 1, the mode control signal 601 controls both the conversion gain of the phase comparator 100 and the resistance value of the loop filter 200;
いずれか一方の制御であっても本発明の効果を発揮でき
る。また、第１図の実施例では、モード制御回路６００
はアンドゲート１個のみとしたが、第７図はこの回路の
別の実施例を示すものである。The effects of the present invention can be exerted even if only one of them is controlled. Further, in the embodiment of FIG. 1, the mode control circuit 600
Although only one AND gate was used in FIG. 7, another embodiment of this circuit is shown.
本実施例はＲＳフリップフロップを構成するナントゲー
ト６３１，６３２に周波数引込み信号４０１と、フィル
タ電流検出信号５０１をインバータ６２１で反転した信
号を入力し、インバータ６２２でフリップフロップの出
力を反転してモード制御信号６０１を出力するように構
成している。第８図はこのモード制御回路６００の動作
を示す真理値表であって、この真理値表から分かるよう
に、周波数引込み信号４０１がＯのときはフィルタ電流
検出信号５０１に関係なく高速引込み状態となり、周波
数引込み信号４０１．フィルタ電流検出信号５０１が共
に１のときは高ジッタ抑圧状態となる。In this embodiment, a frequency pull-in signal 401 and a signal obtained by inverting the filter current detection signal 501 by an inverter 621 are input to the Nant gates 631 and 632 constituting the RS flip-flop, and the output of the flip-flop is inverted by the inverter 622 to set the mode. It is configured to output a control signal 601. FIG. 8 is a truth table showing the operation of this mode control circuit 600. As can be seen from this truth table, when the frequency pull-in signal 401 is O, the high-speed pull-in state occurs regardless of the filter current detection signal 501. , frequency pull-in signal 401. When both filter current detection signals 501 are 1, a high jitter suppression state is entered.
更に、周波数引込み信号４０１が１でフィルタ電流検出
信号５０１がＯのときは前の状態を保持するので、−た
ん高ジッタ抑圧状態になるとフィルタ電流検出信号５０
１に関係なく高ジッタ抑圧状態を保持できる。従って、
このモード制御回路によれば−たん高ジッタ抑圧状態に
なるとフィルタ電流検出信号５０１にかかわらず高ジッ
タ抑圧状態を保持できるので、入力信号ｆ、のジッタ等
によるフィルタ電流の変動に対しても安定な位相同期回
路を提供できる効果がある。Furthermore, when the frequency pull-in signal 401 is 1 and the filter current detection signal 501 is O, the previous state is maintained, so when the high jitter suppression state is reached, the filter current detection signal 50
1, a high jitter suppression state can be maintained. Therefore,
According to this mode control circuit, once the high jitter suppression state is reached, the high jitter suppression state can be maintained regardless of the filter current detection signal 501, so that the high jitter suppression state can be maintained even when the filter current fluctuates due to jitter of the input signal f, etc. This has the effect of providing a phase-locked circuit.
また以上では電流検出は抵抗Ｒ３の両端電圧で行うとし
たが、フィルタ２００に流れる電流の検出が目的である
故に、抵抗Ｒ１等に流れる電流を検出してもよい。Further, in the above description, current detection is performed using the voltage across the resistor R3, but since the purpose is to detect the current flowing through the filter 200, the current flowing through the resistor R1 or the like may also be detected.
本発明によれば、引込み時間を高速引込み状態のみの特
性で決定できるので、高速引込み特性を確保し、更に引
込んだ後に十分なジッタ抑圧特性を実現できるという効
果がある。According to the present invention, since the pull-in time can be determined based on the characteristics of only the high-speed pull-in state, it is possible to ensure the high-speed pull-in characteristic and further achieve sufficient jitter suppression characteristics after the pull-in.
第１図は本発明の一実施例を示す図、第２図及び第３図
は第１図中の位相比較器の実施例を示す図及びその動作
タイムチャート、第４図及び第５図は第１図中の周波数
引込み検出回路の実施例を示す図及びその動作タイムチ
ャート、第６図は第１図の実施例の動作タイムチャート
、第７図及び第８図はモード制御回路の別の実施例を示
す図及びその動作説明図である。
１００・・・位相比較器、２００・・・ループフィルタ
、３００・・・電圧制御発掘器、４００・・・周波数引
込み検出回路、５００・・・フィルタ電流検出回路、６
００・・・モード制御回路。FIG. 1 is a diagram showing an embodiment of the present invention, FIGS. 2 and 3 are diagrams showing an embodiment of the phase comparator in FIG. 1 and its operation time chart, and FIGS. A diagram showing an embodiment of the frequency pull-in detection circuit in FIG. 1 and its operation time chart, FIG. 6 is an operation time chart of the embodiment of FIG. 1, and FIGS. 7 and 8 show another example of the mode control circuit. FIG. 2 is a diagram showing an embodiment and an explanatory diagram of its operation. 100... Phase comparator, 200... Loop filter, 300... Voltage control excavator, 400... Frequency pull-in detection circuit, 500... Filter current detection circuit, 6
00...Mode control circuit.
Claims (1)
の入力信号との位相差を検出する位相比較器と、該位相
比較器出力の低周波成分のみを通過させて上記電圧制御
発掘器の制御電圧を出力するループフィルタとから成る
位相同期回路に於て、上記位相比較器出力が所定の第１
位相差対応値よりも小さい値を所定の時間をこえて出力
した時に周波数引込信号を出力する引込み検出回路と、
上記位相比較器出力が上記第１位相差対応値よりも小さ
い第２位相差対応値より小さくなつた時に位相同期信号
を出力する位相差検出回路と、上記周波数引込信号及び
位相同期信号がともに出力された時に上記ループフィル
タの時定数を増大させる制御及び上記位相比較器の利得
を低下させる制御の一方又は双方を行うための制御信号
を出力するモード制御回路とを設けたことを特徴とする
位相同期回路。 ２、前記位相差検出回路は、前記ループフィルタへの流
入電流を検出することにより前記位相比較器出力の大き
さを検出する構成としたことを特徴とする特許請求の範
囲第１項記載の位相同期回路。 ３、前記モード制御回路は、前記周波数引込信号と前記
位相同期信号とのアンドをとるアンド回路としたことを
特徴とする特許請求の範囲第１項記載の位相同期回路。 ４、前記モード制御回路は、前記周波数引込信号が出力
されていない状態の時は常に前記制御信号を出力せず、
上記周波数引込信号が出力されておりかつ前記位相同期
信号が出力されていない状態の時は該状態になる直前の
状態での上記制御信号の有無をそのまま保持するような
論理回路で構成したことを特徴とする特許請求の範囲第
１項記載の位相同期回路。[Claims] 1. A voltage controlled oscillator, a phase comparator that detects a phase difference between an output signal of the oscillator and an external input signal, and a phase comparator that allows only low frequency components of the output of the phase comparator to pass through. In a phase synchronized circuit consisting of a loop filter that outputs the control voltage of the voltage control excavator, the output of the phase comparator is connected to a predetermined first
a pull-in detection circuit that outputs a frequency pull-in signal when a value smaller than a corresponding phase difference value is output for a predetermined time;
A phase difference detection circuit that outputs a phase synchronization signal when the output of the phase comparator becomes smaller than a second phase difference corresponding value that is smaller than the first phase difference corresponding value, and outputs both the frequency pull-in signal and the phase synchronization signal. a mode control circuit that outputs a control signal for performing one or both of control for increasing the time constant of the loop filter and control for decreasing the gain of the phase comparator when synchronous circuit. 2. The phase difference detection circuit according to claim 1, wherein the phase difference detection circuit is configured to detect the magnitude of the output of the phase comparator by detecting the current flowing into the loop filter. synchronous circuit. 3. The phase synchronization circuit according to claim 1, wherein the mode control circuit is an AND circuit that performs an AND between the frequency pull-in signal and the phase synchronization signal. 4. The mode control circuit does not always output the control signal when the frequency pull-in signal is not output;
When the frequency pull-in signal is output and the phase synchronization signal is not output, the logic circuit maintains the presence or absence of the control signal as it was in the state immediately before the state. A phase-locked circuit according to claim 1, characterized in that:
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61040413A JPS62199119A (en) | 1986-02-27 | 1986-02-27 | Phase locked loop circuit |
| CA000530439A CA1282465C (en) | 1986-02-27 | 1987-02-24 | Phase-locked loop |
| US07/019,113 US4774480A (en) | 1986-02-27 | 1987-02-26 | Phase-locked loop having separate smoothing and loop filters |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61040413A JPS62199119A (en) | 1986-02-27 | 1986-02-27 | Phase locked loop circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62199119A true JPS62199119A (en) | 1987-09-02 |
| JPH0558292B2 JPH0558292B2 (en) | 1993-08-26 |
Family
ID=12579976
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61040413A Granted JPS62199119A (en) | 1986-02-27 | 1986-02-27 | Phase locked loop circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62199119A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63217719A (en) * | 1987-03-06 | 1988-09-09 | Hitachi Ltd | Phase locked loop circuit |
| JPH01119128A (en) * | 1987-10-31 | 1989-05-11 | Nec Corp | Destack system jitter suppressing circuit |
| JPH02211736A (en) * | 1989-02-10 | 1990-08-23 | Nec Corp | Clock synchronizing circuit |
| JPH02290331A (en) * | 1989-04-27 | 1990-11-30 | Nec Ic Microcomput Syst Ltd | Pll oscillator |
| JPH03143116A (en) * | 1989-10-30 | 1991-06-18 | Hitachi Ltd | Phase locked loop circuit and digital signal processor |
| JPH04271636A (en) * | 1991-02-27 | 1992-09-28 | Sanyo Electric Co Ltd | Interface circuit and phase locked loop used therefor |
| US5347233A (en) * | 1992-04-02 | 1994-09-13 | Mitsubishi Denki Kabushiki Kaisha | PLL circuit apparatus and phase difference detecting circuit apparatus |
| JPH098653A (en) * | 1995-06-16 | 1997-01-10 | Sony Corp | Device and method for detecting phase |
| JP2008219799A (en) * | 2007-03-07 | 2008-09-18 | Thine Electronics Inc | Pll frequency synthesizer |
| CN108075773A (en) * | 2016-11-14 | 2018-05-25 | 中芯国际集成电路制造(上海)有限公司 | For the start-up circuit and phaselocked loop of phaselocked loop |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101507853B1 (en) * | 2013-04-04 | 2015-04-07 | 엘지전자 주식회사 | vacuum cleaner and a manufacturion method of the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5472454U (en) * | 1977-10-31 | 1979-05-23 | ||
| JPS5917727A (en) * | 1982-06-28 | 1984-01-30 | エリクソン ジーイー モービル コミュニケーションズ インコーポレーテッド | Bandwidth control circuit of phase locked loop |
-
1986
- 1986-02-27 JP JP61040413A patent/JPS62199119A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5472454U (en) * | 1977-10-31 | 1979-05-23 | ||
| JPS5917727A (en) * | 1982-06-28 | 1984-01-30 | エリクソン ジーイー モービル コミュニケーションズ インコーポレーテッド | Bandwidth control circuit of phase locked loop |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63217719A (en) * | 1987-03-06 | 1988-09-09 | Hitachi Ltd | Phase locked loop circuit |
| JPH01119128A (en) * | 1987-10-31 | 1989-05-11 | Nec Corp | Destack system jitter suppressing circuit |
| JPH02211736A (en) * | 1989-02-10 | 1990-08-23 | Nec Corp | Clock synchronizing circuit |
| JPH02290331A (en) * | 1989-04-27 | 1990-11-30 | Nec Ic Microcomput Syst Ltd | Pll oscillator |
| JPH03143116A (en) * | 1989-10-30 | 1991-06-18 | Hitachi Ltd | Phase locked loop circuit and digital signal processor |
| JPH04271636A (en) * | 1991-02-27 | 1992-09-28 | Sanyo Electric Co Ltd | Interface circuit and phase locked loop used therefor |
| US5347233A (en) * | 1992-04-02 | 1994-09-13 | Mitsubishi Denki Kabushiki Kaisha | PLL circuit apparatus and phase difference detecting circuit apparatus |
| JPH098653A (en) * | 1995-06-16 | 1997-01-10 | Sony Corp | Device and method for detecting phase |
| JP2008219799A (en) * | 2007-03-07 | 2008-09-18 | Thine Electronics Inc | Pll frequency synthesizer |
| CN108075773A (en) * | 2016-11-14 | 2018-05-25 | 中芯国际集成电路制造(上海)有限公司 | For the start-up circuit and phaselocked loop of phaselocked loop |
| CN108075773B (en) * | 2016-11-14 | 2021-04-02 | 中芯国际集成电路制造(上海)有限公司 | Starting circuit for phase-locked loop and phase-locked loop |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0558292B2 (en) | 1993-08-26 |
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