JPS62193241A - Crystal substrate for semiconductor device - Google Patents
Crystal substrate for semiconductor deviceInfo
- Publication number
- JPS62193241A JPS62193241A JP3377586A JP3377586A JPS62193241A JP S62193241 A JPS62193241 A JP S62193241A JP 3377586 A JP3377586 A JP 3377586A JP 3377586 A JP3377586 A JP 3377586A JP S62193241 A JPS62193241 A JP S62193241A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- wafer
- substrate
- semiconductor device
- alignment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 33
- 239000013078 crystal Substances 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 5
- 230000003287 optical effect Effects 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 25
- 230000000694 effects Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000003550 marker Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000010297 mechanical methods and process Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000011282 treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54406—Marks applied to semiconductor devices or parts comprising alphanumeric information
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54493—Peripheral marks on wafers, e.g. orientation flats, notches, lot number
Landscapes
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置用の結晶基板に関し、特に該基板に
ついての情報を表示してなる結晶基板に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a crystal substrate for a semiconductor device, and more particularly to a crystal substrate displaying information about the substrate.
半導体装置は結晶基板に対し各種の処理を施して製造さ
れるのであるが、結晶基板からは一般に多数の半導体装
置が形成される。Semiconductor devices are manufactured by subjecting a crystal substrate to various treatments, and a large number of semiconductor devices are generally formed from a crystal substrate.
この様な多数個どり用の結晶基板（ウェハ）としては、
従来、第３図に示す様な、直径数インチ、厚さ数百ミク
ロンの円板上のものが使用されている。該基板１の周辺
部の一部には切欠２が形成されている。該切欠２は直線
状であり、ファセットもしくはオリエンテーションフラ
ットと呼ばれるものであり、基板１の結晶方位を表して
いる。また、このファセット２は、ウェハ１の加工時の
位置合せ（アライメント）にも使用される。即ち、通常
は、機械式合せ機構により、ファセット及びそれと平行
な方向の直径と外周との交点のうちの一点を治具に押付
けることによって、機械的な位置出を行なっている。基
板１の結晶方位を知ることと、ウェハの位置出を行なう
ことは、半導体装置の製造工程には不可欠である。As a crystal substrate (wafer) for such a large number of crystals,
Conventionally, a disc-shaped device having a diameter of several inches and a thickness of several hundred microns, as shown in FIG. 3, has been used. A notch 2 is formed in a part of the periphery of the substrate 1. The notch 2 is linear and is called a facet or orientation flat, and represents the crystal orientation of the substrate 1. The facets 2 are also used for alignment during processing of the wafer 1. That is, normally, mechanical positioning is performed by pressing one point of the intersection of the facet, the diameter in a direction parallel to the facet, and the outer periphery to a jig using a mechanical alignment mechanism. Knowing the crystal orientation of the substrate 1 and locating the wafer are essential to the manufacturing process of semiconductor devices.
しかして、近年において半導体装置の微細化が進むにつ
れて、この切欠の存在が問題となってきている。即ち、
まずウェハの面積が減少し、半導体装置のとれ数が減少
する。例えば、ＳＥＭＩ規格の１００鶴ウエハではファ
セットの存在によって約１．５％の面積減少が生じてい
るが、実際は、ウェハの周辺部では、収率が低下する領
域が生じるために、実質的には半径が減少したような状
態となり、前記ファセットによる面積減少効果は数％に
も上ることになる。このファセットによる面積減少は半
導体装置のコストアップをもたらし、デメリットは大き
い。However, as semiconductor devices have become increasingly finer in recent years, the presence of these notches has become a problem. That is,
First, the area of the wafer is reduced, and the number of semiconductor devices to be removed is reduced. For example, in the SEMI standard 100 Tsuru wafer, the area is reduced by about 1.5% due to the presence of facets, but in reality, there is an area where the yield decreases at the periphery of the wafer, so the area is reduced by approximately 1.5%. The radius appears to be reduced, and the area reduction effect due to the facets reaches several percent. This reduction in area due to facets increases the cost of the semiconductor device, which is a big disadvantage.
また、ファセットは、基板加工時即ち半導体装置製造時
にも悪影響を生じる。まずファセットのコーナ一部は、
搬送容器や搬送装置との衝突により、チッピングを生じ
やすい。また、熱処理工程の通過の際に、熱伝導状態に
不均一性を生じるために、ウェハのそり、欠陥発生等の
悪影響を及ぼす。この際、ウェハのファセット形成時の
履歴カ問題となってくることは言うまでもない。また、
スピンオンの場合、ファセットから塗布材が流れ出し、
しばしばウェハ裏面を汚す結果となる。Furthermore, facets also have an adverse effect during substrate processing, that is, during semiconductor device manufacturing. First, some of the corners of the facets are
Chipping is likely to occur due to collision with the transport container or transport device. Further, when the wafer passes through a heat treatment process, non-uniformity occurs in the heat conduction state, which causes adverse effects such as warping of the wafer and generation of defects. Needless to say, in this case, the problem of history during the formation of facets on the wafer becomes a problem. Also,
In the case of spin-on, the coating material flows out from the facets,
This often results in contamination of the backside of the wafer.
この様に、ファセットの存在にはかなりの問題点がある
。As described above, the existence of facets has considerable problems.
また、従来、第４図に示される様に、円板状基板１の周
辺部の一部にノツチ３を付することにより結晶方位を表
示することも提案されているが、これによっても上記の
問題点は根本的には解決されない。Furthermore, as shown in FIG. 4, it has been proposed to indicate the crystal orientation by attaching a notch 3 to a part of the peripheral part of the disc-shaped substrate 1, but this also allows the above-mentioned The problem is not fundamentally resolved.
一方において、工程の管理化、自動化が進んだ現在では
、ウェハに表示されるべき情報も、結晶方位の他に多数
存在する。On the other hand, now that process management and automation have advanced, there is a large amount of information that should be displayed on wafers in addition to crystal orientation.
これらの品質情報表示についても、上記第３図及び第４
図に記載の様な切欠を付することにより行なえば、同様
の問題が生ずる。These quality information displays are also shown in Figures 3 and 4 above.
If this is done by providing a notch as shown in the figure, a similar problem will occur.
本発明によれば、上記の如き従来技術の問題点を解決す
るものとして、表面に結晶方位に関連する加工時位置合
せ用パターンと当該基板に関する情報表示用パターンと
が形成されていることを特徴とする、半導体装置用結晶
基板が提供される。According to the present invention, in order to solve the problems of the prior art as described above, a pattern for positioning during processing related to the crystal orientation and a pattern for displaying information regarding the substrate are formed on the surface. A crystal substrate for a semiconductor device is provided.
以下、図面を参照しながら本発明の具体的実施例を説明
する。Hereinafter, specific embodiments of the present invention will be described with reference to the drawings.
第１図は本発明による基板の第１の実施例を示す平面図
である。FIG. 1 is a plan view showing a first embodiment of a substrate according to the present invention.
第１図において、１は半導体結晶基板（ウェハ）であり
、たとえばシリコンからなる。４は位置合せ用パターン
、５はウェハの品質を表示するパターン（文字）である
。４のパターンは、上記第３図のファセットと同様に、
結晶方位を表わしている。５のウェハの品質を表示する
パターンは前記パターン４の外方、即ち、ウェハ外周に
近い方にある。５に表示されたウェハの品質は、引上方
法、導電タイプ、面方位、抵抗率であるが、別にこれら
に限る必要はなく、ウェハに関する所望の情報を表示す
ることができる。In FIG. 1, reference numeral 1 denotes a semiconductor crystal substrate (wafer), which is made of silicon, for example. 4 is an alignment pattern, and 5 is a pattern (characters) indicating the quality of the wafer. Pattern 4 is similar to the facet in Figure 3 above,
It represents the crystal orientation. The pattern No. 5 indicating the quality of the wafer is located outside of the pattern No. 4, that is, near the outer circumference of the wafer. The quality of the wafer displayed in 5 includes the pulling method, conductivity type, surface orientation, and resistivity, but is not limited to these, and any desired information regarding the wafer can be displayed.
本実施例の基板は次の様にして形成される。即ち、まず
、半導体装置のりソゲラフイエ程と同様にしてレジスト
塗布した後、例えばＬＥＤによるキャラクタ−転写装置
（ウェハマーカ）あるいはＥＢ描面装置等により、４と
５のパターンを焼付は現像する。次いで、例えばＲＩＥ
等により、基板１の上記パターン部分を深さ数μｍエツ
チングする。The substrate of this example is formed as follows. That is, first, a resist is applied in the same manner as in the semiconductor device adhesive process, and then patterns 4 and 5 are printed and developed using, for example, an LED character transfer device (wafer marker) or an EB drawing device. Then, for example, RIE
The above-mentioned pattern portion of the substrate 1 is etched to a depth of several μm by etching.
本実施例の基板の加工時において、ウェハの位置合せは
、前述したような機械式では無理であるものの、例えば
イメージセンサを利用した電気式合せ機構、あるいはレ
ーザースキャンを利用した光学式合せ機構等により、ア
ライメントが可能である。４の位置合せ用パターンは、
従来のファセットと同一場所、同一寸法に形成すること
により、同−合せ機構により位置合せが可能である。Although it is impossible to align the wafers mechanically during processing of the substrate in this embodiment, it is impossible to align the wafers using the mechanical method described above, but for example, an electrical alignment mechanism using an image sensor, an optical alignment mechanism using laser scanning, etc. alignment is possible. The alignment pattern of 4 is
By forming the facets at the same location and with the same dimensions as conventional facets, alignment can be performed using a matching mechanism.
尚、上記パターン４，５０部分は半導体装置の製造時に
おいて、該パターン形成面を裏面とすることにより、半
導体装置形成に十分に利用できる。Incidentally, the above-mentioned patterns 4 and 50 can be fully utilized for forming a semiconductor device by setting the pattern forming surface as the back surface during the manufacture of the semiconductor device.
以上の様に、本実施例の基板は従来の基板の様に切欠を
有しないので該切欠の存在にともなう上記の如き問題は
全く存在しない。As described above, unlike the conventional substrate, the substrate of this embodiment does not have a notch, so the above-mentioned problems associated with the presence of the notch do not exist at all.
第２図は本発明による基板の第２の実施例を示す平面図
である。FIG. 2 is a plan view showing a second embodiment of the substrate according to the present invention.
第２図において、第１図におけると同様に、１はウェハ
であり、５は該ウェハの品質を表示するパターンである
。６は位置合せ用パターンであり、該パターンは上記第
１の実施例の場合と異なる。In FIG. 2, as in FIG. 1, 1 is a wafer, and 5 is a pattern indicating the quality of the wafer. Reference numeral 6 denotes an alignment pattern, which is different from that of the first embodiment.
即ち、本実施例の位置合せ用パターン６はファセ７・ト
状ではなくＶ字形であり、これにより図における」１下
方向のアライメントのみならず図における左右方向のア
ライメントをも高い精度で行なうことができる。また、
回転方向のアライメント精度を向上させたい場合には、
このようなパターンを、ウェハ１の２カ所に配置すれば
良い。That is, the alignment pattern 6 of this embodiment has a V-shape rather than a facet 7-shape, so that not only the downward alignment in the figure 1 but also the horizontal alignment in the figure can be performed with high precision. I can do it. Also,
If you want to improve alignment accuracy in the rotational direction,
Such a pattern may be placed at two locations on the wafer 1.
本発明においては、上記第４図の従来の基板の様にノツ
チに基づくウェハのチッピング、割れの対策を考慮する
必要はないために、位置合せ用パターンとして任意のパ
ターンが可能である。In the present invention, unlike the conventional substrate shown in FIG. 4, there is no need to consider countermeasures against chipping and cracking of the wafer based on notches, so any pattern can be used as the alignment pattern.
また、本発明においては、形成される情報表示用パター
ンは、人間の目に判別できる記号及び大きさである必要
はなく、読取機械等に認識できる、例えば、バーコード
等であってもかまわない。また、ウェハの両面に差があ
る場合には、どちらの面、あるいは必要に応じて両面に
各パターンを形成してもかまわない。Furthermore, in the present invention, the formed information display pattern does not have to be a symbol and size that can be discerned by the human eye, and may be a bar code that can be recognized by a reading machine, etc. . Furthermore, if there is a difference between both surfaces of the wafer, each pattern may be formed on either surface or both surfaces as necessary.
以上の様な本発明によれば、切欠を設けることなしに基
板表面に位置合せ用パターン及び情報表示用パターンを
形成しているので、基板の有効利用が可能になり、また
、加工時における１員傷や変形等が著しく少なく、加工
性が容易である。また、本発明によれば基板に関する品
質等の情報をも表示しであるので、管理が容易且つ正確
となる。従って、本発明によれば高品質な半導体装置を
低コストにて製造することが可能となる。According to the present invention as described above, since the alignment pattern and the information display pattern are formed on the surface of the substrate without providing a notch, the substrate can be used effectively, and There are very few scratches or deformations, and the workability is easy. Furthermore, according to the present invention, information such as quality regarding the substrate is also displayed, making management easy and accurate. Therefore, according to the present invention, a high quality semiconductor device can be manufactured at low cost.
第１図及び第２図は本発明による結晶基板の平面図であ
る。
第３図及び第４図は従来の結晶基板の平面図である。
に基板、４，６：位置合せ用パターン、５：品質表示用
パターン
代理人 弁理士 山 下 壌 子
弟１図
第２図
ｂ づ
第３図
第４図1 and 2 are plan views of a crystal substrate according to the present invention. 3 and 4 are plan views of conventional crystal substrates. Board, 4, 6: Alignment pattern, 5: Quality display pattern Agent Patent attorney Yo Yamashita Child 1 Figure 2 b Zu Figure 3 Figure 4
Claims (2)
に関連する加工時位置合せ用パターンと当該基板に関す
る情報表示用パターンとが形成されていることを特徴と
する、半導体装置用結晶基板。(1) A crystal substrate for a semiconductor device, characterized in that a pattern for alignment during processing related to crystal orientation and a pattern for displaying information regarding the substrate are formed on the surface thereof.
表示用パターンが位置合せパターンの外方に位置してい
る、特許請求の範囲第１項の半導体装置用結晶基板。(2) The crystal substrate for a semiconductor device according to claim 1, wherein two patterns are formed in the peripheral portion, and the information display pattern is located outside the alignment pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3377586A JPS62193241A (en) | 1986-02-20 | 1986-02-20 | Crystal substrate for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3377586A JPS62193241A (en) | 1986-02-20 | 1986-02-20 | Crystal substrate for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62193241A true JPS62193241A (en) | 1987-08-25 |
Family
ID=12395823
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3377586A Pending JPS62193241A (en) | 1986-02-20 | 1986-02-20 | Crystal substrate for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62193241A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8849155B2 (en) | 2010-07-23 | 2014-09-30 | Brother Kogyo Kabushiki Kaisha | Image forming device |
| US12011784B2 (en) | 2020-08-03 | 2024-06-18 | Disco Corporation | Wafer, wafer manufacturing method, device chip manufacturing method, and resistivity markings |
-
1986
- 1986-02-20 JP JP3377586A patent/JPS62193241A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8849155B2 (en) | 2010-07-23 | 2014-09-30 | Brother Kogyo Kabushiki Kaisha | Image forming device |
| US12011784B2 (en) | 2020-08-03 | 2024-06-18 | Disco Corporation | Wafer, wafer manufacturing method, device chip manufacturing method, and resistivity markings |
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