JPS62192086A - Semiconductor storage device - Google Patents
Semiconductor storage deviceInfo
- Publication number
- JPS62192086A JPS62192086A JP61034679A JP3467986A JPS62192086A JP S62192086 A JPS62192086 A JP S62192086A JP 61034679 A JP61034679 A JP 61034679A JP 3467986 A JP3467986 A JP 3467986A JP S62192086 A JPS62192086 A JP S62192086A
- Authority
- JP
- Japan
- Prior art keywords
- shift register
- control signal
- memory
- decoders
- lines
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 19
- 239000003990 capacitor Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 7
- 230000008878 coupling Effects 0.000 description 5
- 238000010168 coupling process Methods 0.000 description 5
- 238000005859 coupling reaction Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 206010028980 Neoplasm Diseases 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 201000011510 cancer Diseases 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
- Static Random-Access Memory (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体メモリ装置、詳しくは、半導体メモリ装
置内の回路ブロック構成に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to circuit block configurations within semiconductor memory devices.
従来の技術
半導体メモリ装置は大容量化が進む一方ビット構成や機
能面において多岐にわたる製品が生み出されている。そ
の中にはシフトレジスタを有した半導体メモリ装置も発
表されている。2. Description of the Related Art As the capacity of semiconductor memory devices continues to increase, products with a wide variety of bit configurations and functions are being produced. Among them, semiconductor memory devices having shift registers have also been announced.
第３図及び第４図はシフトレジスタを有する従来の半導
体メモリ装置の内部ブロック構成の例である。同図にお
いて２はメモリセルアレー、４はシフトレジスタ、５２
は制御信号線、６２はシフトレジスタ制御信号発生回路
ブロック、６４は入出力回路ブロック、６５はデータ線
である。FIGS. 3 and 4 are examples of internal block configurations of conventional semiconductor memory devices having shift registers. In the figure, 2 is a memory cell array, 4 is a shift register, 52
62 is a shift register control signal generation circuit block, 64 is an input/output circuit block, and 65 is a data line.
第３図の従来例は、シフトレジスタをメモリアレ一部の
両側に隣接した配置をとる例であり、第４図のそれは、
シフトレジスタを周辺回路部に配置する例である。The conventional example shown in FIG. 3 is an example in which shift registers are arranged adjacent to both sides of a part of the memory array, and the conventional example shown in FIG.
This is an example in which a shift register is placed in a peripheral circuit section.
上記構成の半導体メモリ装置の動作を簡単に説明する。The operation of the semiconductor memory device having the above configuration will be briefly described.
メモリセルアレー２より複数ビットの情報を読み出し、
上記読み出し情報をシフトレジスタ４に転送し、制御信
号により入出力回路６４を介して装置外にシリアルデー
タ出力を行なう。この読み出し動作に対し、書き込み動
作は、入出力回路６４を介して書き込み情報をシフトレ
ジスタ４に取り込み、その情報をメモリセルアレー２に
書き込むことにより行なわれる。Read multiple bits of information from memory cell array 2,
The read information is transferred to the shift register 4, and serial data is output to the outside of the device via the input/output circuit 64 in response to a control signal. In contrast to this read operation, a write operation is performed by taking write information into the shift register 4 via the input/output circuit 64 and writing the information into the memory cell array 2.
発明が解決しようとする問題点
上記従来例のブロック配置を採った場合１半導体メモリ
装置のシリアル入出力動作及びシフトレジスタのデータ
転送動作の高速化において以下の問題が発生する。Problems to be Solved by the Invention When the above conventional block arrangement is adopted, the following problems occur in increasing the speed of the serial input/output operation of the semiconductor memory device and the data transfer operation of the shift register.
第３図の構成において、制御信号線６２の配線長が長く
なる（特に、メモリ容置が大容量になると、半導体メモ
リ装置の大型化に伴って配線長も長くなる）故、配線の
浮遊容量が増大し、信号遅延も大きくなる。従って、シ
フトレジスタのデータ転送動作及び入出力動作速度が遅
くなり、高速化を阻むことになる。In the configuration shown in FIG. 3, the wiring length of the control signal line 62 becomes long (particularly when the memory capacity becomes large, the wiring length also becomes long as the semiconductor memory device becomes larger), so the stray capacitance of the wiring increases. increases, and signal delay also increases. Therefore, the data transfer operation and input/output operation speed of the shift register becomes slow, which prevents speeding up.
まだ１第４図の構成をとった場合、シフトレジスタの動
作に関しては、制御信号線を短くする事ができるので、
転送動作を遅くする要因は少ないが、メモリセルアレー
２とシフトレジスタ４とを結ぶデータ線６６が長くなり
データ線容量が増加し高速動作における問題点となり、
更に、いくつかのデータ線が近接して長距離を配線され
る事から、データ線相互間の容量結合によるデータ線の
雑音が安定動作上無視できないものとなる。However, if the configuration shown in Figure 4 is adopted, the control signal line can be shortened for the operation of the shift register, so
Although there are few factors that slow down the transfer operation, the length of the data line 66 connecting the memory cell array 2 and the shift register 4 increases the data line capacity, which becomes a problem in high-speed operation.
Furthermore, since several data lines are wired close to each other over long distances, noise on the data lines due to capacitive coupling between the data lines cannot be ignored for stable operation.
すなわち、 （１）制御信号線の長大化による浮遊容量の増大化。That is, (1) Increase in stray capacitance due to longer control signal lines.
＠）データ線の容量増加と、容量結合による雑音。@) Noise due to increased data line capacity and capacitive coupling.
の２点が大きな問題点である。These two points are major problems.
問題点を解決するだめの手段
本発明は、これらの問題点を解消するもので、複数ビッ
ト構成の半導体メモリ装置において多ビットシフトレジ
スタを配置する場合、メモリセルアレーを分割し１その
間にシフトレジスタをメモリセルアレーに隣接して配置
したブロック構成としたものである。Means for Solving the Problems The present invention solves these problems. When arranging a multi-bit shift register in a semiconductor memory device with a multi-bit configuration, the memory cell array is divided and one shift register is placed between the two. The block configuration is such that the memory cell array is arranged adjacent to the memory cell array.
作用
本発明によると５分割されたメモリセルアレー間にシフ
トレジスタをまとめる事により、シフトレジスタの制御
信号を一本化することができ、制御信号配線の浮遊容量
の低減を実現できる。更に、メモリセルアレーと隣接し
てシフトレジスタを配置することにより、データ線の配
線長を短くでき、且つ、近接するデータ線間の結合容量
を低減する事ができる。According to the present invention, by grouping the shift registers between the five divided memory cell arrays, the control signals for the shift registers can be unified, and the stray capacitance of the control signal wiring can be reduced. Furthermore, by arranging the shift register adjacent to the memory cell array, the wiring length of the data lines can be shortened, and the coupling capacitance between adjacent data lines can be reduced.
すなわち、浮遊容量低減効果による高速動作化と結合容
量低減による雑音低減化による安定動作を実現すること
ができる。That is, it is possible to realize high-speed operation due to the effect of reducing stray capacitance and stable operation due to noise reduction due to the reduction of coupling capacitance.
実施例
第１図は本発明の一実施例要部構成である。メモリセル
アレー２は複数のビットライン８及び１ピツトラインに
直交する複数のワードライン７を含んでいる。半導体メ
モリ装置１において、メモリセルアレー２は２つのメモ
リブロックを構成している。デコーダ３により、特定の
ビットラインが選択され、シフトレジスタ４との間でデ
ータ転送が行なわれる。メモリセルへのデータの書き込
みと、メモリセルからのデータの読み出し動作及びシフ
トレジスタのデータ転送は制御信号配線部６から制御信
号を受けて制御される。６は制御信号発生回路や入出力
回路を含む周辺回路部である。Embodiment FIG. 1 shows the main structure of an embodiment of the present invention. The memory cell array 2 includes a plurality of bit lines 8 and a plurality of word lines 7 perpendicular to one pit line. In the semiconductor memory device 1, the memory cell array 2 constitutes two memory blocks. A specific bit line is selected by the decoder 3 and data is transferred to and from the shift register 4. Writing of data to the memory cells, reading of data from the memory cells, and data transfer of the shift register are controlled by receiving control signals from the control signal wiring section 6. 6 is a peripheral circuit section including a control signal generation circuit and an input/output circuit.
第２図は、８ビツト構成のシフトレジスタを４系統有し
た４ビツト入出力構成の半導体メモリ装置における本発
明の他の実施例である。第１図に比べると、シフトレジ
スタ、制御信号配線部１周辺回路部を詳しくした実施例
である。すなわち、シフトレジスタは、１１〜１８．２
１〜２８゜３１〜３８．４１〜４８のレジスタ部よシ構
成され、それぞれのレジスタ１１〜４８に接続されたデ
ータ線はデコーダ３を介して対応するビットラインに接
続される。制御信号線５１，５２．５３の各信号は、読
み出し制御信号発生回路ブロック６１、シフトレジスタ
制御信号発生回路ブロック６２および書き込み制御信号
発生回路ブロック６３において発生される。９はワード
ラインデコ−ダである。６４は入出力回路ブロックであ
り、これを通して、シフトレジスタ部と１装置外部との
データの授受が行なわれる。FIG. 2 shows another embodiment of the present invention in a semiconductor memory device with a 4-bit input/output configuration having four systems of 8-bit configuration shift registers. Compared to FIG. 1, this is an embodiment in which the shift register and the peripheral circuit section of the control signal wiring section 1 are detailed. That is, the shift register is 11 to 18.2
The data line connected to each register 11-48 is connected to a corresponding bit line via a decoder 3. Each signal on the control signal lines 51, 52, and 53 is generated in a read control signal generation circuit block 61, a shift register control signal generation circuit block 62, and a write control signal generation circuit block 63. 9 is a word line decoder. Reference numeral 64 denotes an input/output circuit block through which data is exchanged between the shift register section and the outside of the device.
上記のブロック構成を採ると、シフトレジスタ１１〜１
８．２１〜２８．３１〜３８．４１〜４８が１つにまと
まっているのでシフトレジスタの制御線は６２の１系統
を共通に使用することができる。すなわち、第３図のよ
うに２系統以上の制御信号線が必要にならないので、配
線の浮遊容量は犬きく低減できることになり、更に、同
一系統の信号で制御されるので、それぞれのシフトレジ
スタの同期性も良くなるという副次的な効果もある。ま
た、シフトレジスタ部とデコーダ部を隣接させることに
より、データ線の長さを最短にすることも可能になり、
第２図の実施例に示すように、近接するデータ線相合容
量を最小にすることができる。If the above block configuration is adopted, shift registers 11 to 1
Since 8.21 to 28.31 to 38.41 to 48 are combined into one, one system of 62 shift register control lines can be used in common. In other words, as there is no need for two or more systems of control signal lines as shown in Figure 3, the stray capacitance of wiring can be significantly reduced.Furthermore, since they are controlled by the same system of signals, each shift register's There is also the side effect of improving synchronization. Also, by placing the shift register section and decoder section adjacent to each other, it is possible to minimize the length of the data line.
As shown in the embodiment of FIG. 2, adjacent data line coupling capacitance can be minimized.
なお、半導体メモリ装置のビット構成として、４ビツト
、シフトレジスタのビット構成として、８ビツトの実施
例を示したが、他のビット構成の半導体メモリ装置にお
いても同様のブロック配置構成を採用することにより、
配線浮遊容量の低減とデータ線相互の干渉の低減を実現
し、高速動作化を容易にする事は言うまでもない。Although an example has been shown in which the bit configuration of the semiconductor memory device is 4 bits and the bit configuration of the shift register is 8 bits, semiconductor memory devices with other bit configurations can also be configured by adopting a similar block arrangement configuration. ,
Needless to say, this reduces wiring stray capacitance and reduces interference between data lines, making it easier to operate at higher speeds.
発明の効果
以上のように本発明は、シフトレジスタを有する半導体
メモリ装置において、メモリセルアレーを分割し、それ
ぞれのメモリブロックの間にデコーダを配置し、更にそ
の間にシフトレジスタ、そして１ シフトレジスタ部の
間に制御信号を配置したブロック構成を採ることにより
、信号配線の浮遊容量とデータ線相互の干渉を低減し、
高速動作実現を図ることができ、その実用的効果は犬な
るものがある。Effects of the Invention As described above, the present invention provides a semiconductor memory device having a shift register, in which a memory cell array is divided, a decoder is arranged between each memory block, a shift register is provided between each memory block, and a shift register section is provided. By adopting a block configuration in which control signals are placed between the
It is possible to achieve high-speed operation, and its practical effects are significant.
第１図は本発明の一実施例要部構成ブロック図１第２図
は本発明の具体的な他の実施例を示すブロック図１第３
図及び第４図は従来各側のブロック図である。
１・・・・・・半導体メモリ装置、２・・・・・・メモ
リセルアレー、３・・・・・・デコーダ、４・・・・・
シフトレジスタ、６・・・・・・制御信号配線部、６・
・・・・・周辺回路部、７・・・・・・ワードライン、
８・・・・・・ピットライン、９・・・・・・ワードラ
インデコーダ、１１〜１８．２１〜２８゜３１〜３８．
４１〜４８・・・・・・シフトレジスタを構成するレジ
スタ、５１〜５３・・・・・・制御信号線、８１．６３
・・・・・・読み出し、書き込み制御信号発生回路ブロ
ック、６２・・・・・・シフトレジスタ制御信号発生回
路ブロック１６４・・・・・・入出力回路ブロック、６
５・・・・・・データ線。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名１−
一一半尊（６７１表ｊ
２−一一声乞り已ルアυ−
３−−−デコーダ
第 １ 図
斗−ｍ−シフにレジスタ５−−向（確号幅耐灸
舌や
［１’−７’ＪＬヨンシ・癌や
７−−−ワーにう肖ン
δ−−−ビッ【う６ソ
第 ２ 図 プー一−＋
可！′ト弓〜己すマ辷１」２−−−７石’Ｉ ｅ）レア
、−
３−−・テ゛、−ジ′
？−−−、−、−ラｊンテコーヂ
１１〜ｌｊ ２１−２８． ｊｌ・３Ｂ、４ｊ−４８−
−−７７トしジ又ｑ５ｆ−５３−−−′Ｇ！−べ）ル
ｃ＋、０−−− ｇＰｓ−ｈ＝ｔ、曇Ｆ： ｑ剥＃ｌｆ
ｆ ：科！：□フ’ｏ−／７ｆｆ？−−ン・ｋじｚ９早
；１２７４詩文ミョエ釦ひｌフ′４−−−＼洲？ｙ器ブ
ロブフ
ノーｍ１４シミブー゛、１多シシ、ユｉ−第３図
２−７Ｅ、）３Ｉｔア、−４−−ラフにじスタ
ｓ２°−１ｊ？ごｐ、ｔテ喝
σ４−八田刀ロエシプＤノ２
２−一メモリこノしアし−
４−一シ７！−レジ入ヲ
５２− 引刑詩１（
Ｃ２−一一シフトレジ又ヲ弔υン巧＋ｔ５Ｎ７Ｂｇ、７
つ／り０４−ｍ−へたｎｏ工各７０ツフ
「５−−テーク様
手続補正書（自発）FIG. 1 is a block diagram showing the main part configuration of one embodiment of the present invention. FIG. 2 is a block diagram showing another specific embodiment of the present invention.
4 and 4 are block diagrams of each side of the prior art. 1...Semiconductor memory device, 2...Memory cell array, 3...Decoder, 4...
Shift register, 6... Control signal wiring section, 6.
...Peripheral circuit section, 7...Word line,
8...Pit line, 9...Word line decoder, 11-18.21-28°31-38.
41-48...Registers forming the shift register, 51-53...Control signal lines, 81.63
... Read and write control signal generation circuit block 62 ... Shift register control signal generation circuit block 164 ... Input/output circuit block 6
5...Data line. Name of agent: Patent attorney Toshio Nakao and 1 other person1-
11 and a Half Sons (671 table j 2-11-voice begging Rua υ- 3----Decoder 1st figure
Dou-m-shifu to register 5--direction (accurate sign width moxibustion resistance tongue and [1'-7' JL Yongshi cancer and 7----wa-ni-u-port δ--bit [U6 so No. 2 Figure Pooichi-+
Possible! ``Tokyo ~ own length 1'' 2--7 stones' I e) Rare, - 3--・te゛, -ji'? ---, -, -Launtekoji 11-lj 21-28. jl・3B, 4j-48-
--77 Toshijimata q5f-53---'G! -Bel) c+, 0--- gPs-h=t, cloudy F: q strip #lf
f: Department! :□F'o-/7ff? --n・kjiz9 early; 1274 poem myoe button hilf'4 ---＼洲? y-equipment blobufno m14 simibuh, 1 multi-shishi, yui-Figure 3
2-7E,) 3It a, -4--rough rainbow star s2°-1j? Gop, Tteki σ4-Hatta sword loesip Dno 2 2-1 memory konoshia-4-1 7! -Register entry 52- Closing poem 1 (C2-11 Shift cash register again ヲ弔υn takumi+t5N7Bg, 7
Tsu/ri04-m-heta-no-work 70 tufu each "5--take-like procedural amendment (voluntary)
Claims (1)
ビットラインに直交する複数のワードラインと、容量素
子及びスイッチ素子から構成されたメモリセルアレーと
、前記複数のビットラインから特定ビットラインを選択
するデコーダと、並列の多ビットシフトレジスタと、メ
モリデータの読み出し及び書き込み制御回路と、シフト
レジスタ制御回路とを有し、前記メモリセルアレーは複
数のメモリブロックを構成し、前記ビットラインは前記
メモリブロックの分割軸に直交した方向を向き、前記デ
コーダは上記複数のメモリブロックの間にそれぞれのメ
モリブロックに対応して配置され且つそれぞれは各メモ
リブロックに隣接し、前記シフトレジスタは制御信号配
線を挾んで前記デコーダの間に配置され且つ前記デコー
ダを介したメモリデータの転送を行なうことを特徴とし
た半導体記憶装置。A plurality of bit lines formed on a semiconductor substrate, a plurality of word lines perpendicular to the bit lines, a memory cell array composed of a capacitor element and a switch element, and selecting a specific bit line from the plurality of bit lines. a decoder, a parallel multi-bit shift register, a memory data read/write control circuit, and a shift register control circuit, the memory cell array constitutes a plurality of memory blocks, and the bit line is connected to the memory block. The decoders are arranged between the plurality of memory blocks corresponding to the respective memory blocks, and are adjacent to each memory block, and the shift registers sandwich the control signal wiring. A semiconductor memory device, wherein the semiconductor memory device is arranged between the decoders and transfers memory data via the decoders.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61034679A JPS62192086A (en) | 1986-02-18 | 1986-02-18 | Semiconductor storage device |
| US07/015,349 US4796224A (en) | 1986-02-18 | 1987-02-17 | Layout for stable high speed semiconductor memory device |
| KR1019870001317A KR910009122B1 (en) | 1986-02-18 | 1987-02-18 | Layout for stable high speed semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61034679A JPS62192086A (en) | 1986-02-18 | 1986-02-18 | Semiconductor storage device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62192086A true JPS62192086A (en) | 1987-08-22 |
Family
ID=12421102
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61034679A Pending JPS62192086A (en) | 1986-02-18 | 1986-02-18 | Semiconductor storage device |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US4796224A (en) |
| JP (1) | JPS62192086A (en) |
| KR (1) | KR910009122B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0365876A2 (en) * | 1988-10-28 | 1990-05-02 | Texas Instruments Incorporated | Decoding global drive/boot signals using local predecoders |
| WO1996024136A1 (en) * | 1995-01-30 | 1996-08-08 | Hitachi, Ltd. | Semiconductor memory |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5265045A (en) * | 1986-10-31 | 1993-11-23 | Hitachi, Ltd. | Semiconductor integrated circuit device with built-in memory circuit group |
| JPS6468851A (en) * | 1987-09-09 | 1989-03-14 | Nippon Electric Ic Microcomput | Semiconductor integrated circuit |
| US5014242A (en) * | 1987-12-10 | 1991-05-07 | Hitachi, Ltd. | Semiconductor device for a ram disposed on chip so as to minimize distances of signal paths between the logic circuits and memory circuit |
| US5093807A (en) * | 1987-12-23 | 1992-03-03 | Texas Instruments Incorporated | Video frame storage system |
| US5587962A (en) * | 1987-12-23 | 1996-12-24 | Texas Instruments Incorporated | Memory circuit accommodating both serial and random access including an alternate address buffer register |
| US5278802A (en) * | 1988-10-28 | 1994-01-11 | Texas Instruments Incorporated | Decoding global drive/boot signals using local predecoders |
| US5408673A (en) * | 1989-10-13 | 1995-04-18 | Texas Instruments Incorporated | Circuit for continuous processing of video signals in a synchronous vector processor and method of operating same |
| EP0428785B1 (en) * | 1989-11-24 | 1994-02-16 | Siemens Aktiengesellschaft | Semiconductor memory |
| US5150279A (en) * | 1991-03-18 | 1992-09-22 | International Business Machines Corporation | High performance computer system with platters and unidirectional storage modules therebetween |
| US5384745A (en) * | 1992-04-27 | 1995-01-24 | Mitsubishi Denki Kabushiki Kaisha | Synchronous semiconductor memory device |
| US5594704A (en) * | 1992-04-27 | 1997-01-14 | Mitsubishi Denki Kabushiki Kaisha | Synchronous semiconductor memory device |
| US5270964A (en) * | 1992-05-19 | 1993-12-14 | Sun Microsystems, Inc. | Single in-line memory module |
| US5517442A (en) * | 1995-03-13 | 1996-05-14 | International Business Machines Corporation | Random access memory and an improved bus arrangement therefor |
| US5734582A (en) * | 1995-12-12 | 1998-03-31 | International Business Machines Corporation | Method and system for layout and schematic generation for heterogeneous arrays |
| US6141286A (en) * | 1998-08-21 | 2000-10-31 | Micron Technology, Inc. | Embedded DRAM architecture with local data drivers and programmable number of data read and data write lines |
| JP2006123493A (en) * | 2004-09-30 | 2006-05-18 | Seiko Epson Corp | Line head and image forming apparatus |
| US8901747B2 (en) | 2010-07-29 | 2014-12-02 | Mosys, Inc. | Semiconductor chip layout |
| JP2022095327A (en) * | 2020-12-16 | 2022-06-28 | キオクシア株式会社 | Semiconductor storage device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5698785A (en) * | 1979-11-23 | 1981-08-08 | Texas Instruments Inc | Semiconductor memory device |
| JPS59198593A (en) * | 1983-04-27 | 1984-11-10 | Hitachi Ltd | Semiconductor storage device |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5332635A (en) * | 1976-09-07 | 1978-03-28 | Fujitsu Ltd | Memory unit in common use of write data line |
| JPS5339022A (en) * | 1976-09-22 | 1978-04-10 | Hitachi Ltd | Information process unit |
| JPS57208691A (en) * | 1981-06-15 | 1982-12-21 | Mitsubishi Electric Corp | Semiconductor memory |
| JPS609152A (en) * | 1983-06-29 | 1985-01-18 | Fujitsu Ltd | Semiconductor device |
| US4701885A (en) * | 1984-07-26 | 1987-10-20 | Texas Instruments Incorporated | Dynamic memory array with quasi-folded bit lines |
| KR900006221B1 (en) * | 1984-11-15 | 1990-08-25 | 후지쓰 가부시끼가이샤 | Semiconductor memory device |
| US4648077A (en) * | 1985-01-22 | 1987-03-03 | Texas Instruments Incorporated | Video serial accessed memory with midline load |
| US4700328A (en) * | 1985-07-11 | 1987-10-13 | Intel Corporation | High speed and high efficiency layout for dram circuits |
| KR900002664B1 (en) * | 1985-08-16 | 1990-04-21 | 가부시끼가이샤 히다찌세이사꾸쇼 | The semiconductor memory having serial data |
-
1986
- 1986-02-18 JP JP61034679A patent/JPS62192086A/en active Pending
-
1987
- 1987-02-17 US US07/015,349 patent/US4796224A/en not_active Expired - Lifetime
- 1987-02-18 KR KR1019870001317A patent/KR910009122B1/en not_active IP Right Cessation
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5698785A (en) * | 1979-11-23 | 1981-08-08 | Texas Instruments Inc | Semiconductor memory device |
| JPS59198593A (en) * | 1983-04-27 | 1984-11-10 | Hitachi Ltd | Semiconductor storage device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0365876A2 (en) * | 1988-10-28 | 1990-05-02 | Texas Instruments Incorporated | Decoding global drive/boot signals using local predecoders |
| EP0632461A2 (en) * | 1988-10-28 | 1995-01-04 | Texas Instruments Incorporated | Memory device |
| EP0632461A3 (en) * | 1988-10-28 | 1995-02-15 | Texas Instruments Inc | Memory device. |
| WO1996024136A1 (en) * | 1995-01-30 | 1996-08-08 | Hitachi, Ltd. | Semiconductor memory |
Also Published As
| Publication number | Publication date |
|---|---|
| KR870008316A (en) | 1987-09-25 |
| US4796224A (en) | 1989-01-03 |
| KR910009122B1 (en) | 1991-10-31 |
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