JPS62180456A - Signal bypass system for parallel computer - Google Patents
Signal bypass system for parallel computerInfo
- Publication number
- JPS62180456A JPS62180456A JP2183186A JP2183186A JPS62180456A JP S62180456 A JPS62180456 A JP S62180456A JP 2183186 A JP2183186 A JP 2183186A JP 2183186 A JP2183186 A JP 2183186A JP S62180456 A JPS62180456 A JP S62180456A
- Authority
- JP
- Japan
- Prior art keywords
- computer
- bypass
- circuit
- communication
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims description 5
- 238000004891 communication Methods 0.000 abstract description 28
- 230000005540 biological transmission Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- Multi Processors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕 ゛
本発明は、同一構成の計算機が複数個互いに接続される
並列計算機において、計算機間の信号をバイパスする方
式に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for bypassing signals between computers in a parallel computer in which a plurality of computers having the same configuration are connected to each other.
同一構成の複数の計算機をメツシュ状等に接続し、処理
を各計算機で分散して並列に実行する並列計算機が知ら
れている。2. Description of the Related Art Parallel computers are known in which a plurality of computers having the same configuration are connected in a mesh pattern or the like, and processing is distributed among the computers and executed in parallel.
従来、このような並列計算機において、計算機間の通信
を行う場合、送信側と受信側の計算機が直接に接続され
ていない場合には次のような方式が一般に採られている
。即ち、送受計算機間に存在する計算機を仲介計算機と
し、該仲介計算機に送信先の計算機のアドレスおよび送
信データを送出する。仲介計算機は、送られて来たデー
タを一旦蓄積し、さらに該仲介計算機が送信元となって
、送信先計算機の方向ヘアドレス、データを送出する。Conventionally, when communicating between computers in such parallel computers, the following method has generally been adopted when the sending and receiving computers are not directly connected. That is, a computer existing between the sending and receiving computers is used as an intermediary computer, and the address of the destination computer and transmission data are sent to the intermediary computer. The intermediary computer temporarily stores the sent data, and furthermore, the intermediary computer becomes the transmission source and sends the address and data in the direction of the destination computer.
これを繰り返し、送信先計算機にデータが到着すれば通
信を終了する。This is repeated, and when the data reaches the destination computer, the communication ends.
上記従来方式では、通信の経路となった各々の計算機に
おいて、受信および送信の時間遅延が生ずるため、高速
性を要求される並列計算機においては重大な欠点になっ
ていた。In the above-mentioned conventional method, a time delay occurs between reception and transmission in each computer along the communication path, which is a serious drawback in parallel computers that require high speed.
本発明の目的は、並列計算機を構成する計算機間の通信
において、上述した時間遅延をなくし、計算機間通信の
高速化を図ることにある。An object of the present invention is to eliminate the above-mentioned time delay in communication between computers forming a parallel computer, and to speed up communication between the computers.
［問題点を解決するための手段及び作用〕本発明は、並
列計算機を構成する各計算機にデータ処理部とは別に、
当該計算機と接続する計算機からの入力を選択する回路
、出力の送出先計算機を選択する回路、これらの両者を
直接バイパスする回路およびバイパス状態保持回路を設
け、バイパス状態保持回路に入力計算機、出力計算機お
よびバイパス状態の３種のフラグをセットすることによ
り、入力と出力の任意の計算機の組合せがバイパス回路
を経て直接に接続できるようにしたことである。[Means and effects for solving the problems] The present invention provides that each computer constituting a parallel computer has a data processing unit that
A circuit that selects input from a computer connected to the computer, a circuit that selects a destination computer for output, a circuit that directly bypasses both, and a bypass state holding circuit are provided, and the bypass state holding circuit is connected to the input computer and the output computer. By setting three types of bypass state flags, any combination of input and output computers can be directly connected via the bypass circuit.
以下、本発明の一実施例について図面により説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第２図は本発明で対象とする並列計算機における計算機
間の接続構成例を示したもので、計算機１が各々通信路
２を介して、他の計算機と４方向において接続されてい
る例である。以下、計算機１が他の計算機と接続される
方向をそれぞれＦ方向、Ｒ方向、Ｂ方向、Ｌ方向とする
。FIG. 2 shows an example of a connection configuration between computers in a parallel computer targeted by the present invention, and is an example in which computer 1 is connected to other computers in four directions via communication paths 2. . Hereinafter, the directions in which the computer 1 is connected to other computers will be referred to as the F direction, the R direction, the B direction, and the L direction, respectively.
第２図の並列計算機における一つの計算機の構成例を第
１図に示す。第１図において、１１は入力選択回路、１
２はバイパス回路、１３は出力選択回路、１４はバイパ
ス状態保持回路、１５は当該計算機のデータ処理部、１
６と１７は通信データ信号路である。また、２１は入力
選択回路切替信号線、２２はバイパス回路切替信号線、
２３は出力選択切替信号線、２４は通信要求信号線であ
る。バイパス状態保持回路１４は入力方向、出力方向お
よびそれがバイパスか否かを示すフラグをセットするラ
ッチである。通信要求信号線２４は当該計算機と接続さ
れるＦ、Ｒ，Ｂ、Ｌ方向の各計算機とそれぞれ個別に接
続されている。以下。An example of the configuration of one computer in the parallel computer shown in FIG. 2 is shown in FIG. In FIG. 1, 11 is an input selection circuit;
2 is a bypass circuit, 13 is an output selection circuit, 14 is a bypass state holding circuit, 15 is a data processing section of the computer, 1
6 and 17 are communication data signal paths. Further, 21 is an input selection circuit switching signal line, 22 is a bypass circuit switching signal line,
23 is an output selection switching signal line, and 24 is a communication request signal line. The bypass state holding circuit 14 is a latch that sets a flag indicating the input direction, the output direction, and whether or not it is a bypass. The communication request signal line 24 is individually connected to each computer in the F, R, B, and L directions connected to the computer in question. below.
Ｆ方向からＢ方向への通信を例に第１図の動作を説明す
る。The operation of FIG. 1 will be explained using communication from direction F to direction B as an example.
いま、バイパス回路１２はオフ（非バイパス状態）であ
るとする。通信要求信号線２４によりＦ方向に接続され
た計算機からの通信要求を受は取ると、データ処理部１
５はバイパス状態保持回路１４に入力方向としてＦ方向
をセットする。これにより、バイパス状態保持回路１４
はＦ方向を選択する切替信号を信号線２１に出力するた
め、入力選択回路１１はＦ方向を選択する。この結果。Assume that the bypass circuit 12 is now off (non-bypass state). When receiving a communication request from a computer connected in the F direction via the communication request signal line 24, the data processing unit 1
5 sets the F direction as the input direction to the bypass state holding circuit 14. As a result, the bypass state holding circuit 14
outputs a switching signal for selecting the F direction to the signal line 21, so the input selection circuit 11 selects the F direction. As a result.
Ｆ方向に接続された計算機からの命令あるいはデータが
入力選択回路１１、通信データ信号路１６を通ってデー
タ処理部１５に入力される。命令には送信先計算機、バ
イパス要求の有無等が含まれている。こ＼で、送信先計
算機としてＢ方向が指定されていると、データ処理部１
５はバイパス状態保持回路１４に出力方向としてＢ方向
をセットする。これにより、バイパス状態保持回路１４
はＢ方向を選択する切替信号を信号線２３に出力するた
め、出力選択回路１３はＢ方向を選択する。Commands or data from the computers connected in the F direction are input to the data processing section 15 through the input selection circuit 11 and the communication data signal path 16. The command includes the destination computer, whether or not there is a bypass request, etc. Here, if direction B is specified as the destination computer, data processing unit 1
5 sets the B direction as the output direction in the bypass state holding circuit 14. As a result, the bypass state holding circuit 14
outputs a switching signal for selecting the B direction to the signal line 23, so the output selection circuit 13 selects the B direction.
また、命令がバイパスを要求していない場合、データ処
理部１５からバイパス状態保持回路１４へはバイパスが
指示されず、バイパス回路１２はオフのま＼である。Further, if the instruction does not request bypass, the data processing unit 15 does not instruct the bypass state holding circuit 14 to perform bypass, and the bypass circuit 12 remains off.
このようにして、バイパスが要求されない場合は、Ｆ方
向に接続された計算機からの命令、データ等は入力選択
回路１１、通信データ通信路１６を通ってデータ処理部
１５に入力されて処理され、処理結果が通信データ信号
路１７、出力選択回路１３を通ってＢ方向に接続された
計算機へ出力される。In this way, when bypass is not requested, instructions, data, etc. from the computer connected in the F direction are input to the data processing unit 15 through the input selection circuit 11 and the communication data channel 16, and are processed. The processing result is outputted to the computer connected in the B direction through the communication data signal path 17 and the output selection circuit 13.
一方、命令がＢ方向に接続される計算機へのバイパスに
よる通信を要求している場合には、データ処理部１５は
バイパス状態保持回路１４に、出力方向としてＢ方向を
セットすると共にバイパス状態をセットする。これによ
り、バイパス状態保持回路１４は信号線２２を介してバ
イパス回路１２をオン状態に切替える。この場合、Ｆ方
向に接続された計算機からの以後の命令、データ等は入
力選択回路１１、バイパス回路１２、出力選択回路１３
を経由してＢ方向の計算機へ直接出力され、該当計算機
のデータ処理部１５はバイパスされる。On the other hand, if the instruction requests communication by bypass to a computer connected in the B direction, the data processing unit 15 sets the B direction as the output direction in the bypass state holding circuit 14, and also sets the bypass state. do. Thereby, the bypass state holding circuit 14 switches the bypass circuit 12 to the on state via the signal line 22. In this case, subsequent instructions, data, etc. from the computers connected in the F direction are sent to the input selection circuit 11, the bypass circuit 12, and the output selection circuit 13.
The data is directly output to the computer in the B direction via , and the data processing unit 15 of the computer in question is bypassed.
他の方向間のバイパスも同様である６バイパス状態保持
回路１４におけるバイパス状態のリセットは、例えば通
信要求信号線２４とは別にバイパスリセット線を設け、
データ処理部１５がバイパスリセットを受は取って行っ
てもよく、あるいは通信要求信号線２４の該当通信要求
がオフになったことを検知して行ってもよい。The same applies to bypasses between other directions.6 To reset the bypass state in the bypass state holding circuit 14, for example, a bypass reset line is provided separately from the communication request signal line 24,
The data processing unit 15 may receive and perform the bypass reset, or may perform the bypass reset by detecting that the corresponding communication request on the communication request signal line 24 is turned off.
このような構成になっているから、バイパス状態保持回
路１４をセットすると、それ以降は通信データ等はデー
タ処理部１５を経由することがなくなり、従来の方式の
ようにデータ処理部１５が受信した通信データを再び送
信しなおす動作が不要となり、遅延なく通信できること
になる。また。With this configuration, once the bypass state holding circuit 14 is set, communication data etc. no longer go through the data processing unit 15, and the data processing unit 15 receives the data as in the conventional system. There is no need to resend communication data, and communication can be performed without delay. Also.
入力選択回路１１、出力選択回路１３を設けることによ
りバイパス回路１２は一つの経路のバイパスを導通させ
るだけで済み、バイパスが簡単かつ少ないハードウェア
で実現できることになる。なお、本発明は第２図以外の
例えば本状等の結合方式をとる並列計算機にも適用でき
る。By providing the input selection circuit 11 and the output selection circuit 13, the bypass circuit 12 only needs to conduct the bypass of one path, and the bypass can be realized easily and with less hardware. Note that the present invention can also be applied to parallel computers that use a combination method other than that shown in FIG. 2, such as a book-like combination method.
以上説明したように、本発明によれば、計算機のデータ
処理部とは別に設けたバイパス状態保持回路をセットし
、計算機の入力と出力をバイパスすることにより、計算
機のデータ処理部を介すことがなくなるため、計算機間
の通信が高速化できる。また、入力選択回路および出力
選択回路を設けることにより、バイパス回路が簡単かつ
、少ないハードウェアで実現できる利点がある。As explained above, according to the present invention, by setting a bypass state holding circuit provided separately from the data processing section of the computer and bypassing the input and output of the computer, the input and output of the computer can be passed through the data processing section of the computer. This eliminates the need for communication between computers, which speeds up communication between computers. Further, by providing an input selection circuit and an output selection circuit, there is an advantage that the bypass circuit can be realized simply and with less hardware.
第１図は本発明の一実施例の構成図、第２図は本発明で
対象とする並列計算機の構成例を示す図である。
１・・・計算機、 ２・・・通信路、
１１・・・入力選択回路、 １２・・・バイパス回路
、１３・・・出力選択回路、 １４・・・バイパス状態
保持回路、 １５・・・データ処理部。
代理人弁理士 鈴 木 誠 ：ｌＪ：１−、、、
、．１FIG. 1 is a configuration diagram of an embodiment of the present invention, and FIG. 2 is a diagram showing an example configuration of a parallel computer targeted by the present invention. DESCRIPTION OF SYMBOLS 1... Computer, 2... Communication path, 11... Input selection circuit, 12... Bypass circuit, 13... Output selection circuit, 14... Bypass state holding circuit, 15... Data processing section. Representative patent attorney Makoto Suzuki:lJ:1-,,,
,．． 1
Claims (1)
計算機において、各計算機毎に、当該計算機と接続され
る計算機からの入力を選択する入力選択回路、出力先の
計算機を選択する出力選択回路、入力選択回路の出力と
出力選択回路の入力を直接に接続するバイパス回路、バ
イパス状態保持回路を設け、前記バイパス状態保持回路
により入力と出力の任意の計算機の組合せを前記バイパ
ス回路を通してバイパス接続することを特徴とする並列
計算機の信号バイパス方式。(1) In a parallel computer in which multiple computers with the same configuration are connected to each other, for each computer, an input selection circuit selects the input from the connected computer, and an output selection circuit selects the output destination computer. , a bypass circuit that directly connects the output of the input selection circuit and the input of the output selection circuit, and a bypass state holding circuit are provided, and the bypass state holding circuit bypass-connects any combination of input and output of the computer through the bypass circuit. A signal bypass method for parallel computers characterized by the following.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2183186A JPS62180456A (en) | 1986-02-03 | 1986-02-03 | Signal bypass system for parallel computer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2183186A JPS62180456A (en) | 1986-02-03 | 1986-02-03 | Signal bypass system for parallel computer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62180456A true JPS62180456A (en) | 1987-08-07 |
Family
ID=12066014
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2183186A Pending JPS62180456A (en) | 1986-02-03 | 1986-02-03 | Signal bypass system for parallel computer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62180456A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01320564A (en) * | 1988-06-23 | 1989-12-26 | Hitachi Ltd | Parallel processor |
| JPH0293970A (en) * | 1988-09-30 | 1990-04-04 | Nec Corp | Multiprocessor system |
| US7568084B2 (en) | 2003-07-09 | 2009-07-28 | Hitachi, Ltd. | Semiconductor integrated circuit including multiple basic cells formed in arrays |
| JP2009527816A (en) * | 2006-02-16 | 2009-07-30 | ブイエヌエス ポートフォリオ リミテッド ライアビリティ カンパニー | Method and apparatus for monitoring input to a computer |
-
1986
- 1986-02-03 JP JP2183186A patent/JPS62180456A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01320564A (en) * | 1988-06-23 | 1989-12-26 | Hitachi Ltd | Parallel processor |
| US5388230A (en) * | 1988-06-23 | 1995-02-07 | Hitachi, Ltd. | Parallel processor having multi-processing units either connected or bypassed in either series or parallel by the use of bus switching |
| JPH0293970A (en) * | 1988-09-30 | 1990-04-04 | Nec Corp | Multiprocessor system |
| US7568084B2 (en) | 2003-07-09 | 2009-07-28 | Hitachi, Ltd. | Semiconductor integrated circuit including multiple basic cells formed in arrays |
| JP2009527816A (en) * | 2006-02-16 | 2009-07-30 | ブイエヌエス ポートフォリオ リミテッド ライアビリティ カンパニー | Method and apparatus for monitoring input to a computer |
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