JPS62179119A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62179119A JPS62179119A JP2013086A JP2013086A JPS62179119A JP S62179119 A JPS62179119 A JP S62179119A JP 2013086 A JP2013086 A JP 2013086A JP 2013086 A JP2013086 A JP 2013086A JP S62179119 A JPS62179119 A JP S62179119A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- dimensional shift
- pressure
- flow rate
- stable
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- 239000004065 semiconductor Substances 0.000 title claims description 3
- 238000000034 method Methods 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 239000007789 gas Substances 0.000 claims 1
- 239000001307 helium Substances 0.000 claims 1
- 229910052734 helium Inorganic materials 0.000 claims 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 238000001020 plasma etching Methods 0.000 claims 1
- 238000001312 dry etching Methods 0.000 abstract description 10
- 239000000654 additive Substances 0.000 abstract 1
- 230000000996 additive effect Effects 0.000 abstract 1
- 230000003292 diminished effect Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910004738 SiO1 Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体製造工程のホ） ｌ）ノグラフイ技術に
係り、特に３層レジストを用いて正確なパターン転写を
行うのに好適なレジストエツチング法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor manufacturing process e) l) noography technology, and particularly a resist etching method suitable for performing accurate pattern transfer using a three-layer resist. Regarding.
段差を有するウェハ表面に、段差の上、下に共に微ａな
マスクパターン全正確【転写する方法として３層レジス
ト法がある。３層レジスト法を５ｉＯｔ［＋ｌ上のポリ
ノリコン１漠をパターニングする場合を列にとって第２
図で説明する。There is a three-layer resist method as a method for completely accurately transferring a microscopic mask pattern both above and below the step onto a wafer surface having a step. The 3-layer resist method is used in the second row for patterning a polygon layer on 5iOt[+l].
This will be explained with a diagram.
第２図（ａ）の如く、Ｓｉ基板１上にｓｔｏｗ膜２が、
更にその上にポリシリコン膜３が形成されている。この
ＳｉＯ１段差の上に形成されたポリシリコン嘆に３層レ
ジスト法を用いて正確にパターン転写をしようとする場
合、まず、段差を埋めるように厚いレジスト材４を、引
続きレジスト材４をドライエツチングする際のマスク材
として、例えばＳｔＯ，膜５を形成する。このようＫし
て段差を平担化した陵、通常のホトリソ手法で、正確に
マスクパターンをホトレジストに転写し、レジストパタ
ーン６を形成する。次に、第２図（ｂ）の如く、ＳｉＯ
２膜をドライエツチングによりパターニングする。次に
第２図（Ｃ）のｙ口＜、ＳｉＯ，＋ｉ５をマスクにドラ
イエツチングでレジスト４をパターニングする。最後に
第２図（ｄ）の如く、レジスト４をマスクにドライエツ
チングでポリノリコンをエツチングし、所望のポリシリ
コンパターン３が得られる。このような３層レジスト法
については、段差の上下での寸法差を小さくする点で非
常に有効であるカベ通常のホトリノ・ドライエツチング
工程に比べ、ドライエツチングの回数が増えるため、各
ドライエツチングでの寸法シフトを小さくすることが、
全体の寸法シフトを小さくするために必要である。特に
、最下層の厚いレジストのドライエツチングの際の寸法
シフトが大きく、これを小さくしなければならない。As shown in FIG. 2(a), a stow film 2 is formed on the Si substrate 1.
Furthermore, a polysilicon film 3 is formed thereon. When attempting to accurately transfer a pattern using the three-layer resist method to the polysilicon layer formed on this SiO1 step, first a thick resist material 4 is applied to fill the step, and then the resist material 4 is dry-etched. For example, a film 5 made of StO is formed as a mask material during this process. The mask pattern is accurately transferred onto the photoresist using a normal photolithography method, and a resist pattern 6 is formed using the ridges with the steps flattened by the K process. Next, as shown in FIG. 2(b), SiO
The two films are patterned by dry etching. Next, the resist 4 is patterned by dry etching using y<, SiO, +i5 as shown in FIG. 2(C) as a mask. Finally, as shown in FIG. 2(d), the polysilicon is etched by dry etching using the resist 4 as a mask to obtain a desired polysilicon pattern 3. This type of three-layer resist method requires more dry etching than the regular photolithography dry etching process, which is very effective in reducing the dimensional difference between the top and bottom of the step. To reduce the dimensional shift of
This is necessary to reduce the overall dimensional shift. In particular, the dimensional shift during dry etching of the thick resist at the bottom layer is large and must be reduced.
最下層のレジストハ、通常Ｏ，ガスでドライエツチング
するが、例えば、特公昭５９−１３３２９に示されてい
るようにＯｆの圧力を下げることにより、寸法シフトが
小さくなることが知られている。しかし、実際には、装
置依存性があり低圧で安定ＶＣＯ，プラズマを得ること
がむずかしく、又、圧力を上げれは、寸法シフトが大き
くなるというトレードオフがあり、寸法／フトの低減に
は限界がある場合が多い。The bottom resist layer is usually dry etched using O gas, but it is known that the dimensional shift can be reduced by lowering the pressure of Of, as shown in Japanese Patent Publication No. 59-13329, for example. However, in reality, it is difficult to obtain stable VCO and plasma at low pressure due to device dependence, and there is a trade-off that increasing the pressure increases dimensional shift, so there is a limit to the reduction of dimension/ft. There are many cases.
本発明の目的は、安定にＯ，プラズマが得られ、しかも
寸法シフトの小さいレジストのドライエツチング方法を
提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for dry etching a resist in which O plasma can be stably obtained and the dimensional shift is small.
本発明はＯ６の流量を増すことなく、Ｈｅを添加するこ
とにより、圧力を高め安定なプラズマ放電を得、しかも
、寸法Ｚ７トの小さいレジストのドライエツチングを可
能にしたものである。In the present invention, by adding He without increasing the flow rate of O6, the pressure is increased and a stable plasma discharge is obtained, and furthermore, it is possible to dry-etch a resist having a small dimension Z7.
以下、本発明の詳細な説明する。被エツチングレジスト
として、２００Ｃ１Ｎ！雰囲気でベークした厚さ２μｍ
のポジレジスト（東京応化社製、ＯＡＰＭ８００型）、
エツチングマスクとして１９０ＯＮ！雰囲気でベークし
た塗布型ｓｉｏ、膜（東京応化社製８１−４８０００型
）を用いる場合、第１図に示すように、０．流量１１０
５ＣＣ、圧力Ｌ５Ｐａ一定として、Ｈｅを添加すると、
添加量の増加に伴って寸法シフト量が小さくなる。また
、０．のみでは、上記実施列の１．５Ｐａ以下では放電
せず、０、のみで、寸法シフトを小さくすることは不可
能である。本実施例によれば、レジストドライエツチン
グの寸法シフト低減の効果がある。The present invention will be explained in detail below. As the resist to be etched, 200C1N! 2μm thick baked in atmosphere
positive resist (manufactured by Tokyo Ohka Co., Ltd., OAPM800 type),
190ON as an etching mask! When using a coating-type sio film (Model 81-48000 manufactured by Tokyo Ohka Co., Ltd.) baked in an atmosphere, as shown in FIG. Flow rate 110
When He is added with 5CC and pressure L5Pa constant,
As the amount added increases, the amount of dimensional shift becomes smaller. Also, 0. With only 0, no discharge occurs at 1.5 Pa or less in the above-mentioned example row, and it is impossible to reduce the dimensional shift with only 0. According to this embodiment, there is an effect of reducing dimensional shift during resist dry etching.
以上述べたように、本発明によれば、０． Ｉｃ）（ｅ
を添加することによりＯｔの分圧を下げ、実効的に、０
．のみで、低圧の場合と同様に寸法シフトの小さい、し
かも放電の安定したレジストドライエツチングが可能と
なる効果がある。As described above, according to the present invention, 0. Ic) (e
By adding , the partial pressure of Ot is lowered, effectively becoming 0
．． This has the effect of making it possible to perform resist dry etching with small dimensional shift and stable discharge as in the case of low pressure.
第１図は本発明の効果を示す曲線図、第２図は３層レジ
スト法を示す工程図である。
４・・・被エツチングレジスト、５・・・エツチングマ
スク（ｓｔｏｗ）。FIG. 1 is a curve diagram showing the effects of the present invention, and FIG. 2 is a process chart showing the three-layer resist method. 4... Resist to be etched, 5... Etching mask (stow).
Claims (1)
スク材を用いプラズマエッチングする工程において、エ
ッチングガスとしてＯ＿２を用い、これにヘリウムを添
加することを特徴とする半導体装置の製造法。1. A method for manufacturing a semiconductor device, characterized in that in the step of plasma etching an organic resist layer using a mask material that is stable against oxygen plasma, O_2 is used as an etching gas and helium is added thereto.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013086A JPS62179119A (en) | 1986-02-03 | 1986-02-03 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013086A JPS62179119A (en) | 1986-02-03 | 1986-02-03 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62179119A true JPS62179119A (en) | 1987-08-06 |
Family
ID=12018549
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013086A Pending JPS62179119A (en) | 1986-02-03 | 1986-02-03 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62179119A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0529211A (en) * | 1991-07-18 | 1993-02-05 | Sharp Corp | Multi-layer resist method |
| US5756167A (en) * | 1995-04-07 | 1998-05-26 | Hashimoto Forming Industry Co., Ltd. | Rigid elongated member for use in vehicles and producing method and apparatus therefor |
| US7135409B2 (en) * | 2003-08-29 | 2006-11-14 | Oki Electric Industry Co., Ltd. | Plasma etching method for semiconductor device |
-
1986
- 1986-02-03 JP JP2013086A patent/JPS62179119A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0529211A (en) * | 1991-07-18 | 1993-02-05 | Sharp Corp | Multi-layer resist method |
| US5756167A (en) * | 1995-04-07 | 1998-05-26 | Hashimoto Forming Industry Co., Ltd. | Rigid elongated member for use in vehicles and producing method and apparatus therefor |
| US5926930A (en) * | 1995-04-07 | 1999-07-27 | Hashimoto Forming Industry Co., Ltd. | Apparatus for producing rigid elongated member for use in vehicles |
| US7135409B2 (en) * | 2003-08-29 | 2006-11-14 | Oki Electric Industry Co., Ltd. | Plasma etching method for semiconductor device |
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