JPS62177129U - - Google Patents
Info
- Publication number
- JPS62177129U JPS62177129U JP6532386U JP6532386U JPS62177129U JP S62177129 U JPS62177129 U JP S62177129U JP 6532386 U JP6532386 U JP 6532386U JP 6532386 U JP6532386 U JP 6532386U JP S62177129 U JPS62177129 U JP S62177129U
- Authority
- JP
- Japan
- Prior art keywords
- phase
- pulse signal
- voltage
- frequency
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図は本考案の位相同期回路の原理ブロツク
図、第２図は本考案の一実施例の位相同期回路の
ブロツク図、第３図ａ〜ｅは一実施例の位相同期
回路の動作を説明するための図、第４図は従来の
位相同期回路のブロツク図、第５図ａ〜ｄは従来
の位相同期回路の動作を説明するための図である
。
図において、１は電圧制御発振器（ＶＣＯ）、
２は周波数位相弁別器、３はフイルタ、４は可変
減衰手段、５は位相差計測器、６は制御電圧発生
回路、７はＦＥＴ、８はリツプル除去フイルタを
示している。
Fig. 1 is a block diagram of the principle of a phase-locked circuit according to the present invention, Fig. 2 is a block diagram of a phase-locked circuit according to an embodiment of the present invention, and Fig. 3 a to e illustrate the operation of a phase-locked circuit according to an embodiment of the present invention. FIG. 4 is a block diagram of a conventional phase-locked circuit, and FIGS. 5a to 5-d are diagrams for explaining the operation of the conventional phase-locked circuit. In the figure, 1 is a voltage controlled oscillator (VCO),
2 is a frequency phase discriminator, 3 is a filter, 4 is a variable attenuation means, 5 is a phase difference measuring device, 6 is a control voltage generation circuit, 7 is an FET, and 8 is a ripple removal filter.
Claims (1)
ス信号を周波数位相弁別器２に入力して前記両パ
ルス信号の位相差を示す電圧を検出し、該検出電
圧により前記電圧制御発振器の出力パルス信号の
位相を前記入力パルス信号の位相に同期せしめる
位相同期回路において、前記周波数位相弁別器の
出力電圧を位相差に対応して減衰する可変減衰手
段４を設けて成ることを特徴とする位相同期回路
。 The input pulse signal and the output pulse signal of the voltage controlled oscillator 1 are input to a frequency phase discriminator 2, a voltage indicating the phase difference between the two pulse signals is detected, and the detected voltage is used to determine the phase of the output pulse signal of the voltage controlled oscillator. 2. A phase synchronized circuit for synchronizing the frequency and phase discriminator with the phase of the input pulse signal, characterized in that the phase synchronized circuit is provided with variable attenuation means 4 for attenuating the output voltage of the frequency phase discriminator in accordance with the phase difference.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6532386U JPS62177129U (en) | 1986-04-29 | 1986-04-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6532386U JPS62177129U (en) | 1986-04-29 | 1986-04-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62177129U true JPS62177129U (en) | 1987-11-10 |
Family
ID=30902285
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6532386U Pending JPS62177129U (en) | 1986-04-29 | 1986-04-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62177129U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0287822A (en) * | 1988-09-26 | 1990-03-28 | Nec Corp | Automatic phase control circuit |
-
1986
- 1986-04-29 JP JP6532386U patent/JPS62177129U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0287822A (en) * | 1988-09-26 | 1990-03-28 | Nec Corp | Automatic phase control circuit |
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