JPS62171197A - High density hybrid integrated circuit - Google Patents
High density hybrid integrated circuitInfo
- Publication number
- JPS62171197A JPS62171197A JP61013331A JP1333186A JPS62171197A JP S62171197 A JPS62171197 A JP S62171197A JP 61013331 A JP61013331 A JP 61013331A JP 1333186 A JP1333186 A JP 1333186A JP S62171197 A JPS62171197 A JP S62171197A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- hybrid integrated
- substrates
- wiring conductor
- density hybrid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 34
- 239000000919 ceramic Substances 0.000 claims description 21
- 239000004020 conductor Substances 0.000 claims description 15
- 239000011521 glass Substances 0.000 claims description 11
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 239000011368 organic material Substances 0.000 claims description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims 1
- YOCUPQPZWBBYIX-UHFFFAOYSA-N copper nickel Chemical compound [Ni].[Cu] YOCUPQPZWBBYIX-UHFFFAOYSA-N 0.000 claims 1
- 229910052763 palladium Inorganic materials 0.000 claims 1
- 229910052709 silver Inorganic materials 0.000 claims 1
- 239000004332 silver Substances 0.000 claims 1
- 238000000034 method Methods 0.000 description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 239000010408 film Substances 0.000 description 5
- 238000007650 screen-printing Methods 0.000 description 4
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 3
- 229910002113 barium titanate Inorganic materials 0.000 description 3
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229910052707 ruthenium Inorganic materials 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000009966 trimming Methods 0.000 description 2
- 241000785681 Sander vitreus Species 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 238000002485 combustion reaction Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012761 high-performance material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
本発明は多層配線に有利な高密度混成集積回路およびそ
のマルチパッケージに関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a high-density hybrid integrated circuit advantageous for multilayer wiring and its multi-package.
従来の技術
半導体ＩＣの高密度化に伴い、混成集積回路は益々高密
度化が必要となってきており、例えば１００００ゲート
のゲートアレイを搭載する場合、信号線は６００〜８０
０本となり、一平面上では配線できなくなってきている
。BACKGROUND TECHNOLOGY With the increasing density of semiconductor ICs, hybrid integrated circuits have become increasingly required to have higher densities.For example, when mounting a gate array of 10,000 gates, the number of signal lines is 600 to 80.
0, and it is becoming impossible to wire on one plane.
また高速信号処理のため、配線はできる限り短く、また
クコストーク防止のために３次元的な配線の必要性が生
じてきている。Furthermore, for high-speed signal processing, there is a need for wiring to be as short as possible, and three-dimensional wiring to prevent walleye talk.
一方、高機能、高精度化のため信号のデジタル化が進み
、デジタル、アナログを混載した高密度化が必要となり
つつあり、信号線や抵抗素子、容量素子も含めた３次元
的な回路網が必要となってきている。On the other hand, the digitization of signals is progressing in order to achieve higher functionality and precision, and it is becoming necessary to increase the density of digital and analog components. It's becoming necessary.
これらに対して、従来厚膜多層法、グリーンシート多層
法などが提案されている。Conventionally, thick film multilayer methods, green sheet multilayer methods, and the like have been proposed for these methods.
発明が解決しようとする問題点
これらの多層法は、信号線の３次元化は可能であるが、
抵抗素子や容量性素子を内蔵させた場合、基板と同時に
これらの抵抗素子や容量性素子を焼成するため、内蔵さ
れたこれらの素子の抵抗値調整や容量値調整は不可能で
あった。Problems to be Solved by the Invention Although these multilayer methods can make signal lines three-dimensional,
When a resistive element or a capacitive element is built in, it is impossible to adjust the resistance value or capacitance value of the built-in element because the resistive element or capacitive element is fired at the same time as the substrate.
一方、この問題点に対して抵抗、容量性素子をセラミッ
ク基板に焼付けた後、レーザーなどで調整した上、ポリ
イミドなどで多層に形成する方法やカーボンの印刷抵抗
を用い、エポキシ樹脂などで絶縁して多層にする方法な
どが提案されているが、前者はポリイミドのビアホール
形成が複雑で高価なことおよび抵抗、容量性素子は一平
面上しか形成できな゛いこと、後者はルテニウム抵抗な
どの高密度の抵抗素子ではな（、カーボン抵抗を用いる
ため、抵抗値のドリフトが８％もあり、精度の高い抵抗
を形成できないなどの問題を有していた。On the other hand, to solve this problem, resistors and capacitors are baked on a ceramic substrate, adjusted with a laser, etc., and then formed in multiple layers with polyimide, or printed resistors of carbon are used and insulated with epoxy resin. However, the former method is complicated and expensive to form via holes in polyimide, and the resistor and capacitive elements can only be formed on one plane, while the latter method requires high-performance materials such as ruthenium resistors. However, since it uses a carbon resistor, there is a drift in resistance value of as much as 8%, which makes it impossible to form a highly accurate resistor.
問題点を解決するための手段
本発明は上述の問題点を解消するため、予め焼結した厚
さ３０〜１００μｍのセラミック基板上に配線導体層お
よび抵抗体層を設けかつ上記基板を貫通するビアホール
を設け、該基板を複数枚積重ねると共に上記ビアホール
を通じて基板間を結線したことを特徴とする高密度混成
集積回路で、積重ねる前にセラミック基板上に設けた厚
膜、または薄膜抵抗体層はレーザートリミングやサンド
ブラストなどの公知の手段により各々精密にトリミング
８周整される。Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a wiring conductor layer and a resistor layer on a pre-sintered ceramic substrate with a thickness of 30 to 100 μm, and a via hole passing through the substrate. A high-density hybrid integrated circuit characterized in that a plurality of substrates are stacked together and the substrates are interconnected through the via holes, and the thick film or thin film resistor layer provided on the ceramic substrate before stacking is Each piece is precisely trimmed eight times by known means such as laser trimming and sandblasting.
作用
本発明は上述の方式を用いることにより、精度の高い窒
化タンクルやルテニウム抵抗を用い、抵抗値調整を行っ
た上、回路網を形成した各々の基板をビアホールを通し
て結線するため、ドリフトやＴＣＲの小さい窒化タンタ
ルやルテニウム抵抗などの高精度な抵抗を用いることが
でき、かつそれらの抵抗は個々の基板上で精度良くトリ
ミングが可能になる。By using the method described above, the present invention uses highly accurate nitride tanks and ruthenium resistors, adjusts the resistance value, and connects each board on which a circuit network is formed through via holes, thereby eliminating drift and TCR. High-precision resistors such as small tantalum nitride or ruthenium resistors can be used, and these resistors can be precisely trimmed on individual substrates.
同様に容量性素子もタンタルやチタン酸バリウムなどの
スパッタによる薄膜容量性素子やチタン酸バリウムやＰ
ｂ （ＦｅＩＡＮｂ％） Ｃｈ、Ｐｂ （Ｆｅ２／３
Ｗ１／３ ） Ｏ，系の厚膜容量性素子を設けた上、
上部電極をトリミングして精度の高い容量性素子を内蔵
することができる。Similarly, capacitive elements are thin film capacitive elements made by sputtering such as tantalum or barium titanate, or barium titanate or P.
b (FeIANb%) Ch, Pb (Fe2/3
W1/3) O, in addition to providing a thick film capacitive element,
By trimming the upper electrode, a highly accurate capacitive element can be incorporated.
また本発明の他の特徴は個々の層の基板を独立して形成
するため、信号配線やアース配線の配線導体層として銀
パラジニウム合金以外にも安価なニッケルや銅の金属を
用いることが可能である。Another feature of the present invention is that since each layer of the substrate is formed independently, it is possible to use inexpensive metals such as nickel and copper in addition to silver-palladinium alloys as wiring conductor layers for signal wiring and ground wiring. be.
即ち従来の厚膜多層やグリーンシート多層の場合に内部
配線を銅やニッケルを用いると、銅やニッケルの酸化を
防止するため還元性雰囲気で焼成する必要があるが、誘
電体層のバインダーの逸散が還元性雰囲気中の焼成では
困難であり、銅や二・／ケル電極にブリスタが発生し、
配線導体層の断線が生じる虞れがあったが、本発明は焼
成済の厚さ３０〜１００μｍのセラミック基板に配線導
体層を設けるため、電極焼成時に基板からのバインダ燃
焼のガス発生がないため、配線導体層として銅や二、ゲ
ルなどの金属を用いることが可能となる。In other words, if copper or nickel is used for internal wiring in the case of conventional thick film multilayer or green sheet multilayer, it is necessary to bake in a reducing atmosphere to prevent oxidation of the copper or nickel. It is difficult to dissipate when firing in a reducing atmosphere, and blisters occur on copper or 2/Kel electrodes.
There was a risk that the wiring conductor layer would break, but in the present invention, the wiring conductor layer is provided on a fired ceramic substrate with a thickness of 30 to 100 μm, so there is no generation of gas due to binder combustion from the substrate during electrode firing. , it becomes possible to use metals such as copper and gel as the wiring conductor layer.
上記焼結したセラミック基板の個々の厚さを３０〜１０
０μｍに限定した理由は以下の通りである。The individual thickness of the above sintered ceramic substrate is 30~10
The reason why it is limited to 0 μm is as follows.
スクリーン印刷手法により、上層の基板のビアホールを
通じて下層の基板の配線導体層と接続するため、ビアホ
ールに導電ペーストを充填する必要があり、セラミック
基板厚みが１００μｍを超えるとスクリーン印刷手法で
はビアホール部にぶ電ペーストが完全に充填できず、断
線する。またセラミック基板の厚みが３０μｍ未満では
、基板の強度が弱く、スクリーン印刷時に亀裂や割れが
発生する。そのためセラミック基板の厚さは３０〜１０
０μｍの範囲で、好ましくは３０〜６０μｍの範囲にな
る。Since the screen printing method connects the wiring conductor layer of the lower board through the via hole of the upper board, it is necessary to fill the via hole with conductive paste. The electrical paste cannot be filled completely and the wire breaks. Further, if the thickness of the ceramic substrate is less than 30 μm, the strength of the substrate is weak, and cracks and cracks occur during screen printing. Therefore, the thickness of the ceramic substrate is 30 to 10
It is in the range of 0 μm, preferably in the range of 30 to 60 μm.
実施例
次に本発明をさらに詳しく説明するために本発明の一実
施例を第１図および第２図に基づき説明する。Embodiment Next, in order to explain the present invention in more detail, an embodiment of the present invention will be explained based on FIGS. 1 and 2.
マス、第１図（イ）のように焼結済のセラミ・ツク基板
ｌにアース電極や信号線となる導電ペーストを印刷し、
８５０℃で１０分間焼成し、配線導体層２を形成する。As shown in Figure 1 (a), conductive paste is printed on the sintered ceramic substrate l, which will become the ground electrode and signal line.
The wiring conductor layer 2 is formed by baking at 850° C. for 10 minutes.
次に直径２００μｍのビアホール３を予め設けた厚み６
０μｍの焼結済セラミック基板４に信号線となる導電ペ
ーストを印刷し、８５０℃にて１ｏ分間焼成し第１図（
ｏ）のように配線導体層５を形成する。Next, a via hole 3 with a diameter of 200 μm was provided in advance to a thickness 6.
A conductive paste that will become a signal line is printed on a sintered ceramic substrate 4 with a thickness of 0 μm, and is baked at 850°C for 10 minutes as shown in Figure 1 (
A wiring conductor layer 5 is formed as shown in o).
さらに第１図（ハ）のように直径２００μｍのビアホー
ル３を予め設けた厚み６０μｍの焼結済セラミック基板
６に信号線となる導電ペーストを印刷し、８５０℃にて
１０分間焼成し配線導体層７を形成し、容量性素子は上
記配線導体Ｎ７につながる下部電極Ｎ８上にチタン酸バ
リウムとガラスフリフトからなるペーストを印刷し、９
００℃１０分間焼成して誘電体層９を形成した後、上部
電極用導電ペーストおよび抵抗ペーストを印刷し、８５
０℃で１０分間焼成し、上部電極層１０および抵抗体層
１１を形成する。Further, as shown in FIG. 1(C), a conductive paste to be a signal line is printed on a sintered ceramic substrate 6 with a thickness of 60 μm in which a via hole 3 with a diameter of 200 μm has been formed in advance, and is baked at 850° C. for 10 minutes to form a wiring conductor. 7, and the capacitive element is formed by printing a paste made of barium titanate and glass lift on the lower electrode N8 connected to the wiring conductor N7, and forming the capacitive element 9.
After baking at 00°C for 10 minutes to form the dielectric layer 9, a conductive paste for the upper electrode and a resistive paste were printed.
Baking is performed at 0° C. for 10 minutes to form the upper electrode layer 10 and the resistor layer 11.
その後抵抗体Ｎ１１上にオーバーコートガラスを印刷し
、５００°Ｃで１０分間焼成してオーバーコートガラス
層１２を形成した後、抵抗および容量素子をレーザーに
より設定値になるようトリミングする。Thereafter, overcoat glass is printed on the resistor N11 and baked at 500° C. for 10 minutes to form an overcoat glass layer 12, and then the resistor and capacitor elements are trimmed to set values using a laser.
同様にして第１図（ニ）、（ネ）のようにセラミック基
板１３．１４を作成し、最上層のビアホール３を設けた
厚み６０μｍの焼結済セラミック基板１４に半導体のポ
ンディングランドＮ１５および受動部品の半田付ランド
層１６を印刷し、８５０℃で１０分間焼成する。Similarly, ceramic substrates 13 and 14 were created as shown in FIGS. 1(D) and 1(N), and semiconductor bonding lands N15 and A soldering land layer 16 of the passive component is printed and baked at 850° C. for 10 minutes.
このようにして回路網を形成した各々のセラミック基板
１．４．６．１３．１４を用いて、まずセラミック基板
１上にオーバーコート用ガラスペースト１７を印刷し、
その上にセラミック基板４を載値し、ガラスペースト１
７でセラミック基板１と４を融着して一体化し、ビアホ
ール３部分にスクリーン印刷により導電ペーストをうず
め、焼成、硬化させることによりセラミック基板１と４
との電気的接続を行う。Using each of the ceramic substrates 1, 4, 6, 13, and 14 on which a circuit network has been formed in this way, first, an overcoat glass paste 17 is printed on the ceramic substrate 1,
A ceramic substrate 4 is placed on top of it, and a glass paste 1 is placed on it.
In Step 7, the ceramic substrates 1 and 4 are fused and integrated, and a conductive paste is filled in the via hole 3 portion by screen printing, and the ceramic substrates 1 and 4 are baked and hardened.
Make an electrical connection with the
以下同様にセラミック基板４と６および６と１３および
１３と１４を積重ねた後焼成し、各々の配線導体層間を
接続する。そして最上部のセラミック基板１４上に半導
体素子１８を上記ランド層１５．１６上にグイポンドお
よびワイヤボンディングし、コンデンサなどの個別受動
部品１９をはんだ付けして第２図のように構成する。Thereafter, ceramic substrates 4 and 6, 6 and 13, and 13 and 14 are stacked and fired in the same manner, and the respective wiring conductor layers are connected. Then, a semiconductor element 18 is bonded and wire bonded onto the land layer 15, 16 on the topmost ceramic substrate 14, and individual passive components 19 such as a capacitor are soldered to form the structure as shown in FIG.
なお、２０はガラスペーストを硬化したオーバーコート
ガラス層である。Note that 20 is an overcoat glass layer made of hardened glass paste.
また上述の実施例のガラスペースト１７の代わりにエポ
キシ樹脂などの有機材料を用いて接着しても同様な高密
度混成集積回路を構成することができる。Further, a similar high-density hybrid integrated circuit can be constructed by using an organic material such as an epoxy resin for bonding instead of the glass paste 17 of the above-described embodiment.
発明の効果
以上述べた３次元回路網において、抵抗や容量性素子は
個々の焼結されたセラミック基板で作成するため、スパ
ッタリング蒸着などによる薄膜手法やスクリーン印刷に
よる厚膜手法を用いることが可能となり、高精度で高密
度の混成集積回路が実現でき、工業的ならびに実用的価
値の大なるものである。Effects of the invention In the three-dimensional circuit network described above, the resistors and capacitive elements are created using individual sintered ceramic substrates, making it possible to use thin film techniques such as sputtering vapor deposition and thick film techniques such as screen printing. , it is possible to realize a high-precision, high-density hybrid integrated circuit, and it is of great industrial and practical value.
第１図および第２図は本発明に係る高密度混成集積回路
の製造工程における断面図を示す。
１．４．６．１３．１４：予め焼結したセラミック基板
３：ビアホール ５．７：配、ｖｌ導体層１１：抵抗体
層
１７：オーバーコートガラスペースト
２０：オーバ−コートガラス層FIGS. 1 and 2 show cross-sectional views during the manufacturing process of a high-density hybrid integrated circuit according to the present invention. 1.4.6.13.14: Pre-sintered ceramic substrate 3: Via hole 5.7: Distribution, VL conductor layer 11: Resistor layer 17: Overcoat glass paste 20: Overcoat glass layer
Claims (4)
基板上に配線導体層および抵抗体層を設けかつ上記基板
を貫通するビアホールを設け、該基板を複数枚積重ねる
と共に上記ビアホールを通して基板間を結線したことを
特徴とする高密度混成集積回路。(1) A wiring conductor layer and a resistor layer are provided on a pre-sintered ceramic substrate with a thickness of 30 to 100 μm, and a via hole is provided that penetrates the substrate, and a plurality of the substrates are stacked and connections are made between the substrates through the via hole. A high-density hybrid integrated circuit characterized by wire connections.
層を被覆するオーバーコートガラスで融着したことを特
徴とする特許請求の範囲第１項記載の高密度混成集積回
路。(2) The high-density hybrid integrated circuit according to claim 1, wherein the plurality of substrates are fused together with an overcoat glass that covers a wiring conductor layer or a resistor layer.
料で接着したことを特徴とする特許請求の範囲第１項記
載の高密度混成集積回路。(3) The high-density hybrid integrated circuit according to claim 1, wherein the plurality of substrates are bonded together using an organic material such as an epoxy resin.
どの金属からなることを特徴とする特許請求の範囲第１
項記載の高密度混成集積回路。(4) Claim 1, wherein the wiring conductor layer is made of metal such as silver, palladium, nickel copper, etc.
High-density hybrid integrated circuit as described in Section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61013331A JPS62171197A (en) | 1986-01-23 | 1986-01-23 | High density hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61013331A JPS62171197A (en) | 1986-01-23 | 1986-01-23 | High density hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62171197A true JPS62171197A (en) | 1987-07-28 |
Family
ID=11830156
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61013331A Pending JPS62171197A (en) | 1986-01-23 | 1986-01-23 | High density hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62171197A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6489393A (en) * | 1987-09-29 | 1989-04-03 | Kyocera Corp | Multilayer interconnection board |
| JPH01321695A (en) * | 1988-06-23 | 1989-12-27 | Mitsubishi Mining & Cement Co Ltd | Ceramic composite circuit substrate |
| JPH04225594A (en) * | 1990-04-09 | 1992-08-14 | Internatl Business Mach Corp <Ibm> | Multilayer circuit package and its making method |
| JPH0541579A (en) * | 1991-08-05 | 1993-02-19 | Nikko Co | Low temperature sintered multilayer board |
-
1986
- 1986-01-23 JP JP61013331A patent/JPS62171197A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6489393A (en) * | 1987-09-29 | 1989-04-03 | Kyocera Corp | Multilayer interconnection board |
| JPH01321695A (en) * | 1988-06-23 | 1989-12-27 | Mitsubishi Mining & Cement Co Ltd | Ceramic composite circuit substrate |
| JPH04225594A (en) * | 1990-04-09 | 1992-08-14 | Internatl Business Mach Corp <Ibm> | Multilayer circuit package and its making method |
| JPH0541579A (en) * | 1991-08-05 | 1993-02-19 | Nikko Co | Low temperature sintered multilayer board |
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