JPS62169898U - - Google Patents
Info
- Publication number
- JPS62169898U JPS62169898U JP5684386U JP5684386U JPS62169898U JP S62169898 U JPS62169898 U JP S62169898U JP 5684386 U JP5684386 U JP 5684386U JP 5684386 U JP5684386 U JP 5684386U JP S62169898 U JPS62169898 U JP S62169898U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- intrusion
- circuit
- detection circuit
- reactance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims description 8
- 239000003990 capacitor Substances 0.000 claims description 2
- 238000012544 monitoring process Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Burglar Alarm Systems (AREA)
Description
第1図は本考案の一実施例を示す検知回路に用
いられる保持回路の構成図、第2図は保持回路の
各部の波形を示す波形図、第3図は従来の検知回
路の構成図、第4図は検知回路の動作の説明のた
めの波形図である。
8,9……ゲート回路、10……リアクタンス
回路、11……抵抗、12……コンデンサ。
FIG. 1 is a configuration diagram of a holding circuit used in a detection circuit showing an embodiment of the present invention, FIG. 2 is a waveform diagram showing waveforms of each part of the holding circuit, and FIG. 3 is a configuration diagram of a conventional detection circuit. FIG. 4 is a waveform diagram for explaining the operation of the detection circuit. 8, 9...Gate circuit, 10...Reactance circuit, 11...Resistor, 12...Capacitor.
Claims (1)
侵入監視領域から退出した時の退出信号をそれぞ
れ検出し、侵入信号を検出した時から一定の時間
上記侵入信号を保持して、この保持時間内に上記
退出信号を検出したとき侵入検出信号を出力する
検知回路において、 上記検知回路を基準電圧に対して所定の電圧が
入力された時一定レベルの信号を出力するゲート
回路と、ゲート回路の出力端に接続されるリアク
タンス成分を有するリアクタンス回路とで構成し
たことを特徴とする検知回路。 (2) 前記リアクタンス回路は抵抗とコンデンサ
とからなる並列回路で構成したことを特徴とする
実用新案登録請求の範囲第1項記載の検知回路。[Scope of claim for utility model registration] (1) An intrusion signal when an intrusion monitoring area is entered;
Detects each exit signal when exiting from the intrusion monitoring area, holds the above intrusion signal for a certain period of time from when the intrusion signal is detected, and outputs an intrusion detection signal when the above exit signal is detected within this holding time. In the detection circuit, the detection circuit is composed of a gate circuit that outputs a signal at a constant level when a predetermined voltage is input with respect to a reference voltage, and a reactance circuit having a reactance component connected to the output terminal of the gate circuit. A detection circuit characterized by comprising: (2) The detection circuit according to claim 1, wherein the reactance circuit is constituted by a parallel circuit consisting of a resistor and a capacitor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5684386U JPH057669Y2 (en) | 1986-04-17 | 1986-04-17 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5684386U JPH057669Y2 (en) | 1986-04-17 | 1986-04-17 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62169898U true JPS62169898U (en) | 1987-10-28 |
JPH057669Y2 JPH057669Y2 (en) | 1993-02-25 |
Family
ID=30886022
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5684386U Expired - Lifetime JPH057669Y2 (en) | 1986-04-17 | 1986-04-17 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH057669Y2 (en) |
-
1986
- 1986-04-17 JP JP5684386U patent/JPH057669Y2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH057669Y2 (en) | 1993-02-25 |
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