JPS6216523A - Method and device for developing of resist pattern - Google Patents
Method and device for developing of resist patternInfo
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- JPS6216523A JPS6216523A JP15639185A JP15639185A JPS6216523A JP S6216523 A JPS6216523 A JP S6216523A JP 15639185 A JP15639185 A JP 15639185A JP 15639185 A JP15639185 A JP 15639185A JP S6216523 A JPS6216523 A JP S6216523A
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Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明はレジストパターンの現像方法および現像装置、
特に半導体基板上に形成されたレジストパターンの現像
方法および現像装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a resist pattern developing method and a developing device;
In particular, the present invention relates to a method and a developing apparatus for developing a resist pattern formed on a semiconductor substrate.
半導体装置の集積度が益々高まる中で、微細にしてかつ
高精度のパターン形成技術が要求されている。、また、
Ｒ産効果を高め、再現性のよいパターン形成を達成し、
更に人為作業によるダスト付着を防止するためには、半
導体装ｌめ製造プロセスの自動化が必要不可欠の状況と
なってきている。2. Description of the Related Art As the degree of integration of semiconductor devices continues to increase, techniques for forming fine and highly accurate patterns are required. ,Also,
Enhances the R production effect and achieves pattern formation with good reproducibility.
Furthermore, in order to prevent dust adhesion due to manual operations, automation of semiconductor device manufacturing processes has become essential.
半導体基板−Ｌのレジストパターンの形成は、一般に次
のような方法が採られている。まず、半導体ウェハある
いはマスクブランクス等の被処理基板の上に、電子線感
応レジストを回転塗布法や浸漬法等によって塗布する。The following method is generally used to form a resist pattern on the semiconductor substrate-L. First, an electron beam sensitive resist is applied onto a substrate to be processed, such as a semiconductor wafer or a mask blank, by a spin coating method, a dipping method, or the like.
次にこのレジスト膜をオーブンあるいは熱板等の加熱手
段によって所定８ｉ度で加熱し、プリベークを行った後
、このレジスト膜に応じた所定の露光儂で電子線露光を
行い、更に現像処理、リンス処理を施してレジストパタ
ーンを形成する。Next, this resist film is heated at a predetermined temperature of 8i degrees using a heating means such as an oven or a hot plate, and after prebaking, electron beam exposure is performed at a predetermined exposure level depending on the resist film, and further development processing and rinsing are performed. A resist pattern is formed by processing.
最近では高スループツトを得るために高感度レジスト、
例えば電子線感応レジストのポリ（フロロエチルαクロ
ロアクリレート）等を用いたレジストパターン形成が行
われているが、このような高感度レジストは感度変化が
激しいため現像が非常に不安定になりやすく、従来は基
板を１枚ずつ手作業で現像処理していた。高感度レジス
トの不安定な感度変化が生じる要因としては、（１）湿
度、湿度等の環境条件、（２）レジストの緩和現象によ
ると考えられている経時変化、（３）パターンの疎密に
よる基板間の相対的な吸収エネルギーの差、等が挙げら
れる。いずれにせよ、このような手作業による現像処理
では、（１）パターン寸法の確認作業、追加現像作業が
必要となるためスルーブツトが低い、（２）手作業であ
るため、現像中にダスト混入が起こり、これによる欠陥
が多くなる、（３）処理ミスが発生しゃすい、等の問題
がある。Recently, high-sensitivity resists have been developed to obtain high throughput.
For example, resist pattern formation using electron beam-sensitive resists such as poly(fluoroethyl alpha chloroacrylate) has been carried out, but such high-sensitivity resists have rapid sensitivity changes and are prone to extremely unstable development. In the past, each board was developed by hand, one by one. Factors that cause unstable sensitivity changes in high-sensitivity resists include (1) environmental conditions such as humidity, (2) changes over time thought to be due to resist relaxation, and (3) substrate due to pattern density. For example, the difference in relative absorption energy between In any case, with this type of manual development processing, (1) the throughput is low because it requires checking the pattern dimensions and additional development work, and (2) since it is done manually, there is a risk of dust contamination during development. (3) Processing errors are more likely to occur.
そこで本発明は高精度のパターンを高スループツトで形
成させることのできるレジストパターンの現像方法およ
び現像装置を提供することを目的とする。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a resist pattern developing method and a developing apparatus that can form a highly accurate pattern at a high throughput.
（発明の概要）
本発明の第１の特徴は、表面に形成されたレジスト膜に
所定のビームを選択的に照射してパターン露光を行った
基板を現像する現像方法において、基板の表面に向かい
あうように電極を設け、基板の表面と電極との間にレジ
スト膜を現像するための現像液を満たして現像処理を開
始し、この現像処理によって流れる電極と基板との間の
電流値に基づいて現像処理時間を決定するようにし、高
精度のパターンを高スループツトで形成できるようにし
た点にある。(Summary of the Invention) The first feature of the present invention is that in a developing method for developing a substrate that has been subjected to pattern exposure by selectively irradiating a resist film formed on the surface with a predetermined beam, A developing solution is filled between the surface of the substrate and the electrode to develop the resist film, and the developing process is started. The development processing time is determined so that highly accurate patterns can be formed with high throughput.
本発明の第２の特徴は、レジストパターンの現像装置に
おいて、レジストパターンを有する被処理基板を支持す
る支持装置と、この支持装置上に載せられた被処理基板
の表面に向かいあうように設けられた電極と、被処理基
板と電極との間に現像液を供給する現像液供給装置と、
被処理基板と電極との間に流れる電流を測定する電流測
定装置と、を設け、高精度のパターンを高スループツト
で形成できるようにした点にある。A second feature of the present invention is that the resist pattern developing apparatus includes a support device that supports a substrate to be processed having a resist pattern, and a support device provided to face the surface of the substrate to be processed placed on the support device. a developer supply device that supplies a developer between the electrode, the substrate to be processed, and the electrode;
The present invention includes a current measuring device that measures the current flowing between the substrate to be processed and the electrode, thereby making it possible to form highly accurate patterns with high throughput.
以下本発明を図示する実施例に基づいて説明する。第１
図は本発明に係る現像方法の原理図である。いま、ブラ
ンクスとしての被処理基板１が、ガラス基板１ａ、Ｃｒ
、Ｓｉ、Ａｎ等の金属膜１ｂおよびレジスト１１１Ｇか
ら構成されているものとし、このレジスト膜１ｃに形成
されているレジストパターンを現像するものとする。ま
ず、この基板１の表面に向かいあうように電極２を設け
る。この電極２はｐｔ等の不活性金属にするのが好まし
く、また図のようなメツシュ構造とするのがよい。次に
この電極２と基板１との間に現像液を満たして現像を行
う。現像液が一様に満たされるように、現像液ｌおよび
電極と基板間の間隔１を調整する。このとき基板１と電
極２との間を流れる電流をＴｉ流測測定装置ｆｆ３測定
し、この測定結果を検出器４および増幅温５を介してデ
ータ処理系に転送する。電流測定装Ｍ３は電源３ａと抵
抗３ｂを有し、基板１とｆｆｉ極２との間に流れる電流
を抵抗３ｂに導き、この抵抗３ｂの両端子ＡＢ間の電圧
値として測定結果を検出１４に与える。電源３ａは基板
１と電極２との間に所定の電圧を印加する働きをする。The present invention will be described below based on illustrated embodiments. 1st
The figure is a principle diagram of the developing method according to the present invention. Now, the substrate 1 to be processed as a blank is a glass substrate 1a, a Cr
, Si, An, etc., and a resist 111G, and a resist pattern formed on this resist film 1c is developed. First, electrodes 2 are provided on the surface of this substrate 1 so as to face each other. This electrode 2 is preferably made of an inert metal such as PT, and preferably has a mesh structure as shown in the figure. Next, a developing solution is filled between the electrode 2 and the substrate 1 to perform development. The developer l and the distance 1 between the electrode and the substrate are adjusted so that the developer is uniformly filled. At this time, the current flowing between the substrate 1 and the electrode 2 is measured by the Ti current measuring device ff3, and the measurement result is transferred to the data processing system via the detector 4 and the amplification temperature 5. The current measuring device M3 has a power supply 3a and a resistor 3b, and guides the current flowing between the substrate 1 and the ffi pole 2 to the resistor 3b, and sends the measurement result to the detection 14 as a voltage value between both terminals AB of the resistor 3b. give. The power supply 3a functions to apply a predetermined voltage between the substrate 1 and the electrode 2.
電源３ａを設けずに測定を行なうこともできるが、電源
３ａによって所定の電圧を印加することにより両端子Ａ
Ｂ閤の電圧値が増大し、より正確な測定を行うことが゛
できる。Although it is possible to perform measurements without providing the power source 3a, both terminals A can be connected by applying a predetermined voltage using the power source 3a.
The voltage value of the B voltage increases and more accurate measurements can be made.
基板１と電極２との間に起電力が発生するのは、現像液
の電気化学反応に起因する。例えば金属膜１ｂ＄Ｃｒで
あり、電極２がＰｔである場合は、Ｃ−令。 。−−ｃ
ｒ”
なる反応が生じ起電力が発生する。現像液を満たした後
の両端子ＡＢ間の出力電圧の変化は第２図のようになる
。まず現像を開始するとレジスト膜１Ｃ中の電荷が逃げ
、時間１−０〜ｔ、までは出力電圧が低下してゆく。ｔ
”” ｔ ｓにおいてレジス１−１１１ｃが除去され
金属膜１ｂ、即ち、Ｃｒ面が露出するとＣｒが現像液中
に表出し、前述した電気化学反応によって起電力が生じ
、出力電圧は上昇してゆく。この１−１．以後の電圧変
化のグラフは、レジストパターンのパターン構成が同一
であれば非常に再現性よく得られることが実験的に確め
られている。そこで、テスト用の基板を用い、各パター
ンについての最適現像時＠ｔＥを測定しておけば、その
パターンについてはＣｒ表出後Δ１−１［−１，だけの
時開現像すれば、常に最適の現像結果が得られることに
なる。あらかじめ疎密度の異なるいくつかのパターンに
ついて、このΔｔを求めテーブル化しておけば、どのよ
うなパターンについてもほぼ最適な現像時間を得ること
ができる。The electromotive force generated between the substrate 1 and the electrode 2 is due to the electrochemical reaction of the developer. For example, when the metal film 1b is made of Cr and the electrode 2 is made of Pt, it is C-order. . --c
r'' reaction occurs and an electromotive force is generated.The change in the output voltage between both terminals AB after filling with the developer is as shown in Figure 2.First, when development is started, the charges in the resist film 1C escape. , the output voltage decreases from time 1-0 to t.
At ts, when the resist 1-111c is removed and the metal film 1b, that is, the Cr surface is exposed, Cr is exposed in the developer, and the electrochemical reaction described above generates an electromotive force, and the output voltage increases. . This 1-1. It has been experimentally confirmed that subsequent graphs of voltage changes can be obtained with very good reproducibility if the pattern configuration of the resist pattern is the same. Therefore, if you use a test board and measure the optimum development time @tE for each pattern, you can always develop the pattern at the optimum development time by Δ1-1 [-1, after Cr is exposed. This results in a development result of . If this Δt is determined and tabulated in advance for several patterns with different density, it is possible to obtain an almost optimal development time for any pattern.
続いて具体的な現像処理の一例を示す。まず電子線感応
レジストとしてポリ（７０ロエチルαり０ロアクリレー
ト）□をマスクブランクス上に！！□転塗布し、０．６
μｍ程度のレジスト膜を形成し、このレジスト膜を１８
０℃のオープン内で１時間プリベークした。その後、ビ
ーム電流４４０ｎＡ。Next, an example of a specific development process will be shown. First, as an electron beam sensitive resist, poly (70 loethyl α ri 0 loacrylate) □ is placed on the mask blank! ! □Re-coating, 0.6
A resist film of about 18 μm is formed, and this resist film is
It was prebaked for 1 hour in an open oven at 0°C. After that, the beam current was 440 nA.
ビーム径０．５μｍ１加速電圧２０ＫＶの条件で所定の
パターンを露光した。このようにして形成したレジスト
パターンを前述した方法で現像処理した。現像液にはＭ
ＩＢＫ（メチルイソブチルケトン）、リンス液にはＩＰ
Ａ（イソプロピルアルコール）を用い、現像液温は２５
℃±０．２℃とした。レジストパターンのエリアは５イ
ンチ乾板上の５０−の部分である。データ部と非データ
部との比が１：１であるようなパターンの場合、。A predetermined pattern was exposed under the conditions of a beam diameter of 0.5 μm and an acceleration voltage of 20 KV. The resist pattern thus formed was developed by the method described above. M in developer
IBK (methyl isobutyl ketone), IP for rinse solution
Using A (isopropyl alcohol), the developer temperature was 25
The temperature was set at ±0.2°C. The area of the resist pattern is a 50-inch area on a 5-inch dry plate. In the case of a pattern where the ratio of data part to non-data part is 1:1.
Δｔ＝４Ｑｓｅｃ（パドル方式の現像液供給管を用いた
とき）またはΔｔ＝３４８０ｃ（スプレー方式の現像液
供給管を用いたとき）という結果が得られた。同一のパ
ターンを用いて再現性を確認したところ、Δｔが、±１
Ｑｓｅｃ以内であれば形成されたパターンの寸法が±０
．２μｍ以内におさまることがわかった。上述のテスト
では、データ部と非データ部との比が１：１の場合につ
いてのΔｔを求めたが、この比を変化させてそれぞれの
Δｔを求めテーブル化してお番プばよい。A result of Δt=4Qsec (when using a paddle type developer supply pipe) or Δt=3480c (when using a spray type developer supply pipe) was obtained. When we checked the reproducibility using the same pattern, Δt was ±1
The dimension of the formed pattern is ±0 if it is within Qsec
．． It was found that the thickness was within 2 μm. In the above test, Δt was obtained when the ratio of the data part to the non-data part was 1:1, but it is sufficient to vary this ratio to obtain each Δt and create a table.
第３図に本発明に係る現像装置の一実施例を示す。チャ
ンバ６内には支持装置ｔ！７が設けられており、この上
に処理すべき基板１が載置される。支持装置Ｉ７は駆動
部８によって回転する。電極２′はこの回転中は彼処“
理基板１からはずれる。現像液供給管［９からは電磁弁
１０を介して現像液がチＶンバ６内に導入される。この
導入はスプレーノズル１１またはパドルオリフィス１２
を通じて行われる。スプレーノズル１１はチＶンバ６内
に現像液を噴霧し、パドルオリフィス１２は現像液を滴
下する。チャンバ６内の雰囲気は吸引装置１３によって
吸引されている。基板１の上方には電極２が設けられて
いるが、この電極は第１図に示したようにメツシュ構造
のものであるため、現像液の噴霧または滴下が妨げられ
ることはない。FIG. 3 shows an embodiment of the developing device according to the present invention. Inside the chamber 6 is a support device t! 7 is provided, on which the substrate 1 to be processed is placed. The support device I7 is rotated by a drive 8. During this rotation, the electrode 2' is
It comes off from the physical board 1. A developer is introduced into the chamber 6 from the developer supply pipe [9] via a solenoid valve 10. This introduction can be done through the spray nozzle 11 or paddle orifice 12.
It is done through. The spray nozzle 11 sprays the developer into the chamber 6, and the paddle orifice 12 drops the developer. The atmosphere inside the chamber 6 is suctioned by a suction device 13. An electrode 2 is provided above the substrate 1, but since this electrode has a mesh structure as shown in FIG. 1, spraying or dripping of the developer is not hindered.
前述のように基板１と電極部２との間の電流は電流測定
装置１３で測定され、測定結果は検出器４、増幅Ｍ５を
介してデータ処１！回路１４に与えられる。このような
系によって現像テストを行い、いくつかのパターンにつ
いて求めたΔｔを中央制御回路１５にテーブルとして記
憶させておく。このとぎ、各パターンについてのデータ
部と非データ部との比、用いたレジスト、露光条件、露
光エリア、等の諸条件もいっしょに入出力装置１６から
データとして入力しておく。As mentioned above, the current between the substrate 1 and the electrode part 2 is measured by the current measuring device 13, and the measurement result is sent to the data processor 1! via the detector 4 and the amplifier M5. the circuit 14; A development test is performed using such a system, and Δt obtained for several patterns is stored in the central control circuit 15 as a table. At this time, various conditions such as the ratio of the data part to the non-data part, the resist used, the exposure conditions, the exposure area, etc. for each pattern are also input as data from the input/output device 16.
このようにして各条件におけるΔｔのテーブルが求まれ
ば、自動的に現像を行うことができるようになる。即ち
、被処理基板をチャンバ６内にセットして現像を開始し
た後、第２図に示すように両端子ＡＢ間の出力電圧をモ
ニタすれば、出力電圧の変極点として時刻ｔｓが求まる
。従ってこのｔ、の時点から、テーブルより求めたΔｔ
の時間だけ現像処理を行えばよいことになる。このよう
にして現像処理の終点を正確に知ることができるように
なるため、パターンの寸法精度が向上することになり、
また追加現像の必要がなくなるため高スルーブツトで生
産を行うことができる。更に、従来のような手作業によ
る処理ではないため、処理中のダスト混入も防止でき、
チャンバ内で現像処理からリンス処理への切換えも瞬時
に行うことができるようになる。If the table of Δt under each condition is determined in this manner, development can be performed automatically. That is, after setting the substrate to be processed in the chamber 6 and starting development, as shown in FIG. 2, by monitoring the output voltage between both terminals AB, the time ts can be determined as the inflection point of the output voltage. Therefore, from the time point t, Δt calculated from the table
This means that the development process only needs to be carried out for a period of time. In this way, it becomes possible to accurately know the end point of the development process, which improves the dimensional accuracy of the pattern.
Further, since there is no need for additional development, production can be performed at a high throughput. Furthermore, since the process is not done manually like in the past, it is possible to prevent dust from entering the process.
It also becomes possible to instantly switch from development processing to rinsing processing within the chamber.
以上のとおり本発明によればレジストパターンの現像に
おいて、被処理基板とこれに対向して設しプた電極との
間の電流値に基づいて現像処理時間を決定するようにし
たため、高精度のパターンを高スルーブツトで形成でき
るようになる。As described above, according to the present invention, when developing a resist pattern, the developing processing time is determined based on the current value between the substrate to be processed and the electrode placed opposite thereto. Patterns can be formed with high throughput.
第１図は本発明の原理を示す説明図、第２図は本発明に
係る方法を説明するグラフ、第３図は本発明に係る装置
の一実施例の説明図である。
１・・・被処理基板、１ａ・・・ガラス基板、１ｂ・・
・金属膜、１Ｃ・・・レジスト膜、２・・・電極、３・
・・電流測定装置、３ａ・・・′Ｉ８源、３ｂ・・・抵
抗、４・・・検出器、５・・・増幅器、６・・・チャン
バ、７・・・支持装置、８・・・駆動部、９・・・現像
液供給装置、１０・・・Ｔｉ磁弁、１１・・・スプレー
ノズル、１２・・・オリフィス、１３・・・吸引装置、
１４・・・データ処理回路、１５・・・中央制御回路、
１６・・・入出力装置。FIG. 1 is an explanatory diagram showing the principle of the invention, FIG. 2 is a graph explaining the method according to the invention, and FIG. 3 is an explanatory diagram of an embodiment of the apparatus according to the invention. 1...Substrate to be processed, 1a...Glass substrate, 1b...
・Metal film, 1C...Resist film, 2...Electrode, 3.
...Current measuring device, 3a...'I8 source, 3b...Resistor, 4...Detector, 5...Amplifier, 6...Chamber, 7...Support device, 8... Drive unit, 9... Developer supply device, 10... Ti magnetic valve, 11... Spray nozzle, 12... Orifice, 13... Suction device,
14... Data processing circuit, 15... Central control circuit,
16...I/O device.
Claims (1)
的に照射してパターン露光を行つた基板を現像する現像
方法であって、前記基板の表面に向かいあうように電極
を設け、前記基板の表面と前記電極との間に前記レジス
ト膜を現像するための現像液を満たして現像処理を開始
し、この現像処理によって流れる前記電極と前記基板と
の間の電流値に基づいて前記現像処理時間を決定するこ
とを特徴とするレジストパターンの現像方法。 ２、レジストパターンを有する被処理基板を支持する支
持装置と、この支持装置上に載せられた被処理基板の表
面に向かいあうように設けられた電極と、前記被処理基
板と前記電極との間に現像液を供給する現像液供給装置
と、前記被処理基板と前記電極との間に流れる電流を測
定する電流測定装置と、をそなえることを特徴とするレ
ジストパターンの現像装置。 ３、電極がメッシュ構造をしていることを特徴とする特
許請求の範囲第２項記載のレジストパターンの現像装置
。 ４、現像液供給装置がパドル方式の供給管を有すること
を特徴とする特許請求の範囲第２項または第３項記載の
レジストパターンの現像装置。 ５、現像液供給装置がスプレー方式の供給管を有するこ
とを特徴とする特許請求の範囲第２項乃至第４項のいず
れかに記載のレジストパターンの現像装置。 ６、電流測定装置が、被処理基板と電極との間に電圧を
印加する電圧印加装置を有することを特徴とする特許請
求の範囲第２項乃至第５項のいずれかに記載のレジスト
パターンの現像装置。[Scope of Claims] 1. A developing method for developing a substrate which has been subjected to pattern exposure by selectively irradiating a resist film formed on the surface with a predetermined beam, wherein electrodes are placed facing each other on the surface of the substrate. A developing solution for developing the resist film is filled between the surface of the substrate and the electrode to start a developing process, and the value of the current flowing between the electrode and the substrate due to the developing process is A method for developing a resist pattern, characterized in that the development processing time is determined based on the development time. 2. A support device that supports a substrate to be processed having a resist pattern, an electrode provided to face the surface of the substrate to be processed placed on this support device, and a space between the substrate to be processed and the electrode. A resist pattern developing device comprising: a developer supply device that supplies a developer; and a current measurement device that measures a current flowing between the substrate to be processed and the electrode. 3. The resist pattern developing device according to claim 2, wherein the electrode has a mesh structure. 4. The resist pattern developing device according to claim 2 or 3, wherein the developer supplying device has a paddle type supply pipe. 5. The resist pattern developing device according to any one of claims 2 to 4, wherein the developer supply device has a spray type supply pipe. 6. The resist pattern according to any one of claims 2 to 5, wherein the current measurement device has a voltage application device that applies a voltage between the substrate to be processed and the electrode. Developing device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15639185A JPS6216523A (en) | 1985-07-16 | 1985-07-16 | Method and device for developing of resist pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15639185A JPS6216523A (en) | 1985-07-16 | 1985-07-16 | Method and device for developing of resist pattern |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6216523A true JPS6216523A (en) | 1987-01-24 |
Family
ID=15626716
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15639185A Pending JPS6216523A (en) | 1985-07-16 | 1985-07-16 | Method and device for developing of resist pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6216523A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6143206A (en) * | 1998-06-24 | 2000-11-07 | Tdk Corporation | Organic positive temperature coefficient thermistor and manufacturing method therefor |
| EP1752993A2 (en) | 2002-06-24 | 2007-02-14 | TDK Corporation | PTC thermistor body and PTC thermistor |
| JP2008501562A (en) * | 2004-06-03 | 2008-01-24 | ジーエム・グローバル・テクノロジー・オペレーションズ・インコーポレーテッド | Safety device for automobile interior |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3577026A (en) * | 1969-06-24 | 1971-05-04 | Atomic Energy Commission | Method for producing ions utilizing a charge-transfer collision |
| JPS57192954A (en) * | 1981-05-23 | 1982-11-27 | Dainippon Screen Mfg Co Ltd | Surface processing method |
| JPS5870530A (en) * | 1981-10-22 | 1983-04-27 | Toshiba Corp | Resist pattern formation |
| JPS5895349A (en) * | 1981-11-30 | 1983-06-06 | Fuji Photo Film Co Ltd | Replenishing method of replenishing developer of photosensitive plate |
-
1985
- 1985-07-16 JP JP15639185A patent/JPS6216523A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3577026A (en) * | 1969-06-24 | 1971-05-04 | Atomic Energy Commission | Method for producing ions utilizing a charge-transfer collision |
| JPS57192954A (en) * | 1981-05-23 | 1982-11-27 | Dainippon Screen Mfg Co Ltd | Surface processing method |
| JPS5870530A (en) * | 1981-10-22 | 1983-04-27 | Toshiba Corp | Resist pattern formation |
| JPS5895349A (en) * | 1981-11-30 | 1983-06-06 | Fuji Photo Film Co Ltd | Replenishing method of replenishing developer of photosensitive plate |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6143206A (en) * | 1998-06-24 | 2000-11-07 | Tdk Corporation | Organic positive temperature coefficient thermistor and manufacturing method therefor |
| EP1752993A2 (en) | 2002-06-24 | 2007-02-14 | TDK Corporation | PTC thermistor body and PTC thermistor |
| JP2008501562A (en) * | 2004-06-03 | 2008-01-24 | ジーエム・グローバル・テクノロジー・オペレーションズ・インコーポレーテッド | Safety device for automobile interior |
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