JPS62163368A - Lateral-type shottky barrier semiconductor device - Google Patents

Abstract

PURPOSE:To improve characteristics of small forward voltage in a high-current region without enlarging diode capacity, by making concentration of a semiconductor substrate located between a shottky electrode and a contact one be of the same conduction type and higher than surface concentration of the shottky junction part. CONSTITUTION:The same conduction type of impurities are introduced inside from a surface part of the semiconductor substrate neighboring an insulator layer 2 covering the surface of the semiconductor substrate 1, to form a high concentration region 6. An ohmic electrode 7 and a shottky barrier electrode 8 are formed on a surface of a semiconductor substrate 1 neighboring and following the high concentration layer 6. For example, a silicon dioxide film 2 is formed on the surface of the n-type Si semiconductor substrate 1 and then an opening 3 is formed. After a silicon dioxide film 4 is formed on the opening 3, ion implantation of P is performed, besides with a silicon dioxide film 5 piled. Then, the high concentration region 6 is formed by thermal diffusion of P. A window 9 is formed on the other surface region of the silicon dioxide layer on the silicon semiconductor substrate 1 neighboring and following the high concentration region 6, and then a shottky junction opening is formed to pile Mo and Al here and on the window 9 and form the electrodes 7 and 8.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明はショットキバリヤを利用したラテラル構造をも
つ半導体装置の改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement in a semiconductor device having a lateral structure using a Schottky barrier.

〔発明の技術的背景〕[Technical background of the invention]

ショットキバリヤを持った半導体装置を利用したダブル
バランスミキサ回路が知られており、この回路特性を満
すには使用する各半導体装置特性が揃っていることが必
要となる。A double-balanced mixer circuit using a semiconductor device with a Schottky barrier is known, and in order to satisfy this circuit characteristic, it is necessary that the characteristics of each semiconductor device used be the same.

このショットキバリヤダイオードとしてはいオ〕ゆるバ
ーチカル（Ｖｅｒｔｉｃａｌ）タイプとラテラルタイプ
があるが、前者はある導電型の半導体基板にこれより不
純物濃度の低くかつ同一導電型を示す気相成長層を最大
１ｓｔｎｎ程度堆積し、この気相成長層を被覆する絶縁
層に開孔を設け、二へにショットキ金属を被着してショ
ットキバリヤダイオードを得るのが通常である。従って
、この半導体基板に複数個のショットキバリヤダイオー
ドをモノリシックに集積するとこの半導体基板が電気的
に共通となるので、前述のダブルバランスミキサ回路を
構成するには適当な分離構造が必要となる。しかも、前
述のように濃度の低い気相成長層を、′ａ度が大きい半
導体基板に堆積するため外方拡散等が起りＶＦならびに
容量が揃ったショットキダイオードが得難い。このため
、ウェハーから分割するチップとしては隣接する位置の
ものをダブルバランスミキサ回路用に利用する手法を採
用しても尚前述の揃った特性をもつものが得蔑い。There are two types of Schottky barrier diodes: the vertical type and the lateral type.The former uses a semiconductor substrate of a certain conductivity type with a vapor-grown layer of the same conductivity type and with a lower impurity concentration than the semiconductor substrate of a maximum of about 1stnn. It is customary to deposit a Schottky barrier diode by providing an aperture in the insulating layer covering the vapor grown layer and depositing Schottky metal on the second half. Therefore, when a plurality of Schottky barrier diodes are monolithically integrated on this semiconductor substrate, this semiconductor substrate becomes electrically common, and therefore an appropriate separation structure is required to construct the above-mentioned double-balanced mixer circuit. Furthermore, as described above, since a vapor-phase growth layer with a low concentration is deposited on a semiconductor substrate with a high degree of a, outward diffusion occurs, making it difficult to obtain a Schottky diode with uniform VF and capacitance. For this reason, even if a technique is adopted in which chips are separated from a wafer and chips located adjacent to each other are used for a double-balanced mixer circuit, it is still difficult to obtain chips that have the same characteristics as described above.

したがって、パーティカルタイプに代えてラテラル型シ
ョットキダイオードが採用されているが、これを第７図
により説明すると、比抵抗０．４Ω印程度の珪素半導体
基板（２ｏ）を用意しその表面に厚さ２μの酸化珪素膜
（２１）を被覆後、所定の距ＦａＱだけ離した位置を開
孔し、二＼にオーミック電極（２２）及びショットキ電
極（２３）を形成する。ショットキ電極（２２）として
はＭＯ及びＡｌ１　　を連続蒸着によって合計２μｍ程
度堆積して形成するが、その中ＭＯは２０００人〜３０
００人の厚さとし、オーミック電極（２３）の形成に当
ってはＰＯＣＱ　３によって開孔がらＰを導入して１０
”ａｔｏｍｓ／ｃｃｌ’ｉｊ度の表面濃度を持った拡散
層（２４）を設け、更にＡＱを堆積してオーミック電極
（２３）を得ている。Therefore, a lateral type Schottky diode is used instead of a particle type, but this can be explained using Fig. 7. A silicon semiconductor substrate (2O) with a resistivity of about 0.4Ω is prepared, and a thickness of After covering with a silicon oxide film (21) of 2 μm, holes are opened at positions separated by a predetermined distance FaQ, and an ohmic electrode (22) and a Schottky electrode (23) are formed on the second side. The Schottky electrode (22) is formed by depositing MO and Al1 by continuous evaporation to a total thickness of about 2 μm.
When forming the ohmic electrode (23), P was introduced into the hole by POCQ 3 and the thickness was 100 mm.
A diffusion layer (24) having a surface concentration of "atoms/ccl'ij" is provided, and AQ is further deposited to obtain an ohmic electrode (23).

〔背景技術の問題点〕[Problems with background technology]

前述のダブルバランスミキサ回路に使用するショットキ
バリヤダイオードに要求される特性は次の通りである。The characteristics required of the Schottky barrier diode used in the double-balanced mixer circuit described above are as follows.

慣千〆Ａ） ところで、ショットキバリヤダイオードの容量ＣＴ≦Ｊ
Ｎｓ（Ｎｓ：不純物４４度）の関係は良く知られれでい
るところであるが、　ラテラル構造ではｖＦを小さく抑
えるとこの関係式から判るように容；１（が増大する関
係にある。すなわちこのｖＦ、特性を改善するために、
ショットキ′市極及びコンタクト電極間に位置する半導
体基板に含有する不純物３１１度を増大するとＣＴが増
大することになりｖＦだけを小さくするには前述のＱを
可能な限り小さくすれば良い。しかし、写真食刻技術の
限界等もあって通常５μ程度であり、ｖＦ２特性では不
利な状況にあり、その改善が望まれている。By the way, the capacitance CT≦J of Schottky barrier diode
The relationship between Ns (Ns: impurity 44 degrees) is well known, but in a lateral structure, if vF is kept small, as can be seen from this relational expression, there is a relationship in which the volume; In order to improve the characteristics,
If the impurity 311 degrees contained in the semiconductor substrate located between the Schottky electrode and the contact electrode is increased, CT will increase, and in order to reduce only vF, the above-mentioned Q should be made as small as possible. However, due to the limitations of photoetching technology, etc., the thickness is usually about 5μ, which is disadvantageous in terms of vF2 characteristics, and an improvement is desired.

〔発明の目的〕[Purpose of the invention]

本発明は、上記難点を克服した新規なラテラル型ショッ
トキバリヤ半導体装置を提供するもので、特にダイオー
ド容量を大きくせずに高電流領域での小順方向電圧特性
を改良する。The present invention provides a novel lateral Schottky barrier semiconductor device that overcomes the above-mentioned difficulties, and particularly improves the small forward voltage characteristics in a high current region without increasing the diode capacitance.

〔発明の概要〕[Summary of the invention]

上記目的を達成するに当って、ショットキ電極ならびに
コンタクト電極間に位置する半導体基板Ｑの濃度をショ
ットキ接合部の表面濃度より同一導電型でかつ高くして
、このＱ部分での抵抗成分を小さくしかつ高電流領域で
の順方向電圧を、容量を増大させることなく減少させた
ものである。To achieve the above objective, the concentration of the semiconductor substrate Q located between the Schottky electrode and the contact electrode is made to be of the same conductivity type and higher than the surface concentration of the Schottky junction, thereby reducing the resistance component in this Q portion. In addition, the forward voltage in the high current region is reduced without increasing the capacity.

〔発明の実施例〕[Embodiments of the invention]

第１図乃至第６図により本発明を詳述する。 The present invention will be explained in detail with reference to FIGS. 1 to 6.

比抵抗（ρ）約０．４Ω印のｎ導電型Ｓｉ半導体基板（
１）を用意し、その表面に二酸化珪素膜■を常法のスチ
ーム酸化１０００℃×４０分によって第２図（ａ）に示
すように形成後、写真食刻技術によって開孔（３）を設
ける。この開孔■は背景技術欄に示したＱに相当する位
置である。An n-conductivity type Si semiconductor substrate with a specific resistance (ρ) of approximately 0.4Ω (
1) is prepared, and a silicon dioxide film (2) is formed on its surface by conventional steam oxidation at 1000°C for 40 minutes as shown in Fig. 2(a), and then holes (3) are formed by photolithography. . This opening (■) is located at a position corresponding to Q shown in the background art section.

次に再度酸化をＤｒｙ０２１０５０℃×６０分の条件下
で実施してこの開孔■に約１０００人の二酸化珪素膜Ｇ
）を第２図すに示すように形成後、この半導体基板（１
）全面ニ加速’ｉｊ’１．圧１３０ＫｅＶ　テＰ　ヲ３
　Ｘ　１０１３個／ａｎ−”イオン注入し、更にＣＶＤ
法により二酸化珪素膜０を第２図Ｃのように約０．５μ
堆積する。更に、イオン注入したＰをＮ　ｚ　／　Ｏｚ
雰囲気テ１２００’ｃ　ｌ　Ｈ熱拡散して第２図（ｃ）
に示すように熱拡散していわゆるＱの部分には８１半導
体基板のより高、加変の領域０を形成する。Next, oxidation was carried out again under the dry conditions of 50°C x 60 minutes, and about 1000 silicon dioxide films were applied to the openings.
) is formed as shown in Figure 2, this semiconductor substrate (1
) Full-plane acceleration 'ij'1. Pressure 130KeV TeP wo3
X 1013/an-” ion implantation and further CVD
As shown in Figure 2C, the silicon dioxide film 0 is coated with a thickness of about 0.5μ by
accumulate. Furthermore, the ion-implanted P is reduced to Nz/Oz
Atmosphere temperature 1200'c l H heat diffusion and Figure 2(c)
As shown in FIG. 8, a higher and variable region 0 of the semiconductor substrate 81 is formed in the so-called Q portion by thermal diffusion.

更に第２図ｄのようにオーミック電極■ならびに第１図
のショットキバリヤ電極■の形成工程に移行する。Further, the process moves on to the formation process of the ohmic electrode (2) as shown in FIG. 2(d) and the Schottky barrier electrode (2) of FIG.

すなわち、第２図ｄに示すように、高濃度領域０に隣接
して連続する珪素半導体基板（１）の表面他部分の二酸
化珪素層には写真食刻技術で窓■）を設け、　コ＞　４
：ＰＯＣＱ　、を１０００’ＣテＤ　ｅｐｏ　Ｌ　”Ｃ
カラ、　：：の窓附近に被着するＰ２Ｏ９層をｖＯＱ％
でＨ２Ｏ：！１００．　Ｈｌ”　：　４５．　ＨＮ　Ｏ
，：　３０（７）組成を持ツタ食刻液で除去して、１０
２’　ａｔｏｍｓ／ｃｃ程度の拡散層（１０）を形成す
る。引続いて、ショットキ接合用開孔を、第１図に示す
ように高濃度領域０を挟んでオーミック接合用拡散層（
１０）に対向する半導体ノλ板に積層する絶縁物層を除
去して後、こシ及びオーミック接合用窓（９）とにＭＯ
及びＡＱ　　をスパッタ法で連続して堆積して電極■な
らびに■を形成する。この場合Ｍｏは２０００〜３００
０人の厚さとし、　合計で約２μｍの厚さにするが、オ
ーミック接合用窓では高、ノ′ツ度な拡散層（１０）が
存在しているのでショットキバリヤ接合は形成されず通
常のオーミック電極が得られ、他方の開孔では約１×１
０”’ａｔｏｍｓ／ｃｃの不純物、１４度をもつ半導体
基板（１）にＭＯが接触してオーミック接合が得られる
と共にショットキバリヤ′社極（８）が得られる。That is, as shown in FIG. 2d, a window (■) is provided by photolithography in the silicon dioxide layer on the surface and other parts of the silicon semiconductor substrate (1) which is adjacent to and continuous with the high concentration region 0. 4
:POCQ、1000'C teDepo L"C
Kara, P2O9 layer deposited near the window of :: vOQ%
And H2O:! 100. Hl”: 45.HN O
, : 30 (7) composition, removed with ivy etching solution, 10
A diffusion layer (10) of approximately 2' atoms/cc is formed. Subsequently, the Schottky junction opening is inserted into the ohmic junction diffusion layer (
10) After removing the insulating layer laminated on the semiconductor lambda plate facing
and AQ are successively deposited by sputtering to form electrodes (1) and (2). In this case, Mo is 2000-300
The total thickness is approximately 2 μm, but since the ohmic bonding window has a highly active diffusion layer (10), a Schottky barrier bond is not formed and a normal ohmic bond is formed. An electrode is obtained, in the other aperture approximately 1 × 1
The MO is brought into contact with the semiconductor substrate (1) having an impurity of 0''atoms/cc and a temperature of 14 degrees, thereby obtaining an ohmic contact and a Schottky barrier electrode (8).

第４図（ａ）（ｂ）には他の実施例を示す。FIGS. 4(a) and 4(b) show other embodiments.

この例の出発材料は実施例１と同様であり、ウェル層（
１２）をリンのイオン注入法によって設け、更にこのウ
ェル層には配着濃度領域（１３）も形成するが、その位
置はショットキ電極（１４）下に形成するショットキ接
合を包むように隣接して形成し、オーミック電極（１５
）は実施例１と同じくｎ導電型を示し１０１０２１ａｔ
ｏ／ｃｃ程度の表面濃度を持つ不純物拡散領域（１６）
に接続して設置する。この電極（１５）は高濃度ｆ：Ｑ
　ｈ々（Ｉ３）を包み隣接する位置に形成する。The starting materials for this example are the same as in Example 1, with a well layer (
12) is provided by phosphorous ion implantation, and a coordinating concentration region (13) is also formed in this well layer, which is formed adjacent to the Schottky junction so as to surround the Schottky junction formed under the Schottky electrode (14). Ohmic electrode (15
) indicates n conductivity type as in Example 1 and 101021at
Impurity diffusion region (16) with a surface concentration of about o/cc
Connect and install it. This electrode (15) has a high concentration f:Q
Wrap the h (I3) and form it at an adjacent position.

尚第４図すはａの上面図である。In addition, FIG. 4 is a top view of a.

第５図ａ、ｂには前述のＱ（第１図ａに示す）部分の表
面３ｊ５度を高める手段として適用するイオン注入工程
をショットキならびにオーミック電極形成後に実施する
例を示した。FIGS. 5a and 5b show an example in which the ion implantation process, which is applied as a means for increasing the surface 3j5 degree of the Q portion (shown in FIG. 1a) described above, is performed after the Schottky and ohmic electrodes are formed.

すなわち、オーミック電極及びショットキ電極を形成し
たシリコン半導体基板のＱの位置以外をＷなどの高融点
金属層を被着後、これをマスクとしてリンをイオン注入
し更にフラッシュアニール工程で活性化して高濃度領域
（１７）を設けて抵抗成分を減少する。この方法ではシ
ョットキ接合とのすき間を最小に抑えることができるの
で優れた順方向特性を持つショットキバリヤダイオード
が得られる。That is, after depositing a high melting point metal layer such as W on a silicon semiconductor substrate other than the Q position on which the ohmic electrode and Schottky electrode are formed, phosphorus is ion-implanted using this layer as a mask, and is further activated in a flash annealing process to form a high concentration layer. A region (17) is provided to reduce the resistance component. In this method, the gap with the Schottky junction can be minimized, so a Schottky barrier diode with excellent forward characteristics can be obtained.

〔発明の効果〕〔Effect of the invention〕

第６図には本発明によって得られラテラル型ショットキ
バリヤダイオードの順方向特性を示した。FIG. 6 shows the forward characteristics of a lateral Schottky barrier diode obtained according to the present invention.

この図から明らかなように、高濃度領域を形成した素子
の方が窩電流領域での順方向電圧が改善されており、そ
の程度はＱの部分の表面濃度が高い素子が良い結果を示
している。しかし、この高濃度領域に隣接する半導体基
板表面にはショットキ金属を被着してショットキ接合を
形成しており、その不純物濃度Ｉ　Ｘ　１０１０１７ａ
ｔｏ／ｃｃに対して高濃度領域の不純物濃度は５　Ｘ　
１０”ａｔｏｍｓ／ｃｃが最高値である。と言うのはこ
の高濃度領域に隣接してオーミック接合を設けており、
従って無制限に高濃度にすると写真食刻工程での合せ精
度±１μからオーミック接合の形成を防止するためであ
るにのような高濃度領域をもったショットキバリヤダイ
オードはそのＱ部分での抵抗値を下げて順方向電圧が改
善されて第３図に示したダブルバランスミキサ回路に使
用しても良結果が得られる。As is clear from this figure, the forward voltage in the cavity current region is improved in the device with a high concentration region, and to this extent, the device with a high surface concentration in the Q region shows better results. There is. However, the surface of the semiconductor substrate adjacent to this high concentration region is coated with Schottky metal to form a Schottky junction, and its impurity concentration I x 101017a
The impurity concentration in the high concentration region is 5X with respect to to/cc
The highest value is 10"atoms/cc. This is because an ohmic junction is provided adjacent to this high concentration region.
Therefore, if the concentration is increased without limit, the alignment accuracy in the photolithography process is ±1μ to prevent the formation of an ohmic junction.A Schottky barrier diode with a high concentration region, such as The forward voltage is improved by lowering the voltage, and good results can be obtained even when used in the double-balanced mixer circuit shown in FIG.

と言うのは高ＩＩＨ“９度領域の形成によって前述の順
方向電圧特性が改善され、しかもイオン注入による不純
物４３度制御が確実になって特性の揃った素子が得られ
るためダブルバランスミキサ回路としての機能が確実に
発揮されるのも大きな特徴である。This is because the forward voltage characteristics mentioned above are improved by forming the high IIH 9 degree region, and the impurity 43 degree control by ion implantation is ensured, resulting in an element with uniform characteristics, which makes it suitable for use as a double-balanced mixer circuit. Another major feature is that the functions are reliably demonstrated.

第５図によって得られる素子では電極をセルファライン
に利用できるのでマスク合せ精度が向上する利点も持っ
ている。The device obtained as shown in FIG. 5 has the advantage that the mask alignment accuracy is improved because the electrode can be used as a self-alignment line.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明に係るショットキバリヤダイオードの断
面図、第２図ａ　＝　ｄは第１図に示す素子の製造経過
を示す断面図、第３図はダブルバランスミキサ回路の結
線図、第４図ａ、ｂは他の実施例を示す断面図、第５図
ａ、ｂはその他の実施例を示す断面図及び上面図、第６
図は本発明に係る素子の特性を示す曲線図、第７図は従
来の素子の断面図である。FIG. 1 is a sectional view of a Schottky barrier diode according to the present invention, FIG. 2 a = d is a sectional view showing the manufacturing process of the device shown in FIG. 1, FIG. 3 is a wiring diagram of a double balanced mixer circuit, and FIG. Figures a and b are sectional views showing other embodiments, Figures 5 a and b are sectional views and top views showing other embodiments, and Figure 6
The figure is a curve diagram showing the characteristics of the element according to the present invention, and FIG. 7 is a sectional view of the conventional element.

Claims (1)

【特許請求の範囲】[Claims] ある導電型の半導体基板と、この半導体基板表面を被覆
する絶縁物層と、この絶縁物層に隣接する半導体基板表
面部分から内部に同一導電型の不純物を導入して形成す
る高濃度領域と、この高濃度層に隣接かつ連続する半導
体基板の表面に設けるオーミック電極及びショットキバ
リヤ電極とを具備することを特徴とするラテラル型ショ
ットキバリヤ半導体装置。A semiconductor substrate of a certain conductivity type, an insulating layer covering the surface of the semiconductor substrate, and a high concentration region formed by introducing impurities of the same conductivity type into the semiconductor substrate from a surface portion of the semiconductor substrate adjacent to the insulating layer; A lateral Schottky barrier semiconductor device comprising an ohmic electrode and a Schottky barrier electrode provided on the surface of a semiconductor substrate adjacent to and continuous with the high concentration layer.