JPS62155549A - Large-scale integrated circuit - Google Patents

Large-scale integrated circuit

Info

Publication number
JPS62155549A
JPS62155549A JP29572885A JP29572885A JPS62155549A JP S62155549 A JPS62155549 A JP S62155549A JP 29572885 A JP29572885 A JP 29572885A JP 29572885 A JP29572885 A JP 29572885A JP S62155549 A JPS62155549 A JP S62155549A
Authority
JP
Japan
Prior art keywords
flip
functional blocks
functional
flop
scale integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29572885A
Other languages
Japanese (ja)
Inventor
Sunao Takahata
高畠　直
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP29572885A priority Critical patent/JPS62155549A/en
Publication of JPS62155549A publication Critical patent/JPS62155549A/en
Pending legal-status Critical Current

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To test the trouble of a flip-flop circuit at high speed by forming a pad for a prober capable of observing a flip-flop circuit scan-path output signal as one of connections among functional blocks. CONSTITUTION:A system is divided into each functional block and designed logically, and the functional blocks are arranged and wired by four functional- block wiring regions 1-4 in size required for laying out respective functional block. Each functional block is wired mutually and the functional blocks and an I/O cell region 6 are wired by a wiring region 5 among the functional blocks. When the test facilitation of flip-flop circuits 10 by shift operation is executed, having a shift chaining system in which the flip-flop circuits for the functional blocks are connected sequentially, pads 7 for probers capable of observing among the functional blocks are formed.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は、大規模集積回路に関し、特に、回路試験を容
易化した大規模集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a large-scale integrated circuit, and particularly to a large-scale integrated circuit that facilitates circuit testing.

（従来の技術） 大規模集積回路において、急速な集積度の向上につれて
集積回路の設計法も、設計品質の低下を防ぎ設計期間の
短縮をはかるために機能ブロック単位での分割設計が採
用され、回路試験については、フリツプフロッ１回路全
シーケンシャルに接続したシフト連鎖方式にエフシフト
動作によるフリップフロップ回路の試験容易化設計を行
って、故障検出率の向上およびテストパターン数の圧縮
を図っている。(Prior art) As the degree of integration in large-scale integrated circuits rapidly increases, integrated circuit design methods have adopted divided design into functional blocks in order to prevent deterioration in design quality and shorten the design period. Regarding circuit testing, we designed the flip-flop circuit to be easier to test by using an F-shift operation in a shift chain system in which all flip-flop circuits are sequentially connected to improve the failure detection rate and reduce the number of test patterns.

（発明が解決しようとする問題点） 上述の、回路紙ｒｆｌｌを考慮したフリップフロップ回
路のシフト動作による試験容易化設計４施した大規模集
積回路では、観測点はスキャンパス入力端子に対してス
キャンパス出力端子のみであるので、故障検出率の向上
およびテストパターン数の圧縮に効果がある反面、フリ
ップフロップ回路自身の故障試験、チップの良品選別お
よび不良領域の限定に時間がかかるという欠点があつ７
ｔ。(Problems to be Solved by the Invention) In the large-scale integrated circuit that has been designed for testability by the shift operation of the flip-flop circuit in consideration of the circuit paper rflll, the observation point is located at the scan path input terminal. Since it has only a campus output terminal, it is effective in improving the fault detection rate and reducing the number of test patterns, but it has the disadvantage that it takes time to test the flip-flop circuit itself, select non-defective chips, and limit the defective area. 7
t.

本発明に、上記問題点に鑑みてなされ友ものであり、フ
リップフロップ回路の故障試験を高速で行うことができ
、チップの良品選別および機能ブロック単位での不良領
域の限定全高速で行うことのできる大規模集積回路全提
供すること全目的とする。The present invention has been developed in view of the above-mentioned problems, and is capable of high-speed failure testing of flip-flop circuits, as well as the ability to select non-defective chips and limit defective areas in functional block units at full speed. The entire purpose is to provide all possible large-scale integrated circuits.

（問題点を解決するための手段） 上記目的を達成するため、本発明の大規模集積回路は、
フリップフロップ回路をシーケンシャルに接続し九シフ
ト連鎖方式を有してシフト動作によるフリップフロップ
回路の試験容易化設計を備え、機能ブロック単位の階層
的分割レイアラトラ施しており、機能ブロック間結線の
ひとつであるフリップフロップ回路スキャンパス出力信
号を観測可能なグローバ用パッドを設けるように構成し
τいる。(Means for Solving the Problems) In order to achieve the above object, the large-scale integrated circuit of the present invention has the following features:
Flip-flop circuits are connected sequentially and the flip-flop circuit has a nine-shift chaining system, which is designed to facilitate testing of flip-flop circuits through shift operations.It also has a hierarchical division layout in functional block units, and is one of the connections between functional blocks. The flip-flop circuit is constructed so as to provide a glover pad that allows the scan path output signal to be observed.

（実　施　例） 次に、本発明について図面全参照して説明する。(Example) Next, the present invention will be explained with reference to all the drawings.

第１図は、本発明による大規模集積回路の一実施例の構
成図である。FIG. 1 is a block diagram of an embodiment of a large-scale integrated circuit according to the present invention.

図において、１，２，３．４はそれぞれ機能ブロック配
線領域（１）　、　（２）　、　（３）　、　（４）、
５は機能ブロック間配線領域、６はＩ１０セル領域、７
はグローバ用ハツト、８はＩ１０パッド、９はスキャン
パス信号、１０はフリップフロップ回路、１１はスキャ
ンパス入力端子、１２はスキャンパス出力端子を示す。In the figure, 1, 2, 3.4 are functional block wiring areas (1), (2), (3), (4), respectively.
5 is the wiring area between functional blocks, 6 is the I10 cell area, 7
Reference numeral 8 indicates a glover hat, 8 indicates an I10 pad, 9 indicates a scan path signal, 10 indicates a flip-flop circuit, 11 indicates a scan path input terminal, and 12 indicates a scan path output terminal.

この図においては、機能ブロックを４分割した例を示し
ているが、機能ブロックの均等性および個数はこれに限
定されるものではない。Although this figure shows an example in which the functional blocks are divided into four, the uniformity and number of functional blocks are not limited to this.

システムを各機能ブロックに分けて論理設計し、その配
置配線を各機能ブロックのレイアウトに必要とする大き
さの（１）〜（４）の機能ブロック配線領域１〜４で行
う。機能ブロック間配線領域５により各機能ブロック間
及びＩ１０セル領域６の配線を行う。機能ブロックのフ
リップフロップ回路ＩＯをシーケンシャルに接続したシ
フト連鎖方式を有してシフト動作によるフリップフロッ
プ回路の試験容易化が施されている場合、機能ブロック
間結線のひとつでちるフリップフロップ回路スキャンパ
ス出力信号９が観測可能なグローバ用パッド７を設ける
。The system is divided into functional blocks and logically designed, and the layout and wiring are performed in functional block wiring areas 1 to 4 (1) to (4) of a size required for the layout of each functional block. Wiring between each functional block and the I10 cell area 6 is performed using the inter-functional block wiring area 5. If the flip-flop circuit IO of the functional blocks is connected sequentially to make it easier to test the flip-flop circuit using a shift chain method, one of the connections between the functional blocks can be used to output the scan path of the flip-flop circuit. A glover pad 7 from which a signal 9 can be observed is provided.

従来は、スキャンパス信号の観測点はスキャンパス入力
端子１１に対してスキャンパス出力端子１２のみであっ
たが、上記パッド７を設けることによｐフリップフロッ
プ回路の故障試験を高速で行うことができる。また、チ
ップの良品選別および機能ブロック単位での不良領域の
限定を高速で行うことができる。Conventionally, the scan path signal observation points were only the scan path output terminal 12 with respect to the scan path input terminal 11, but by providing the pad 7, it is possible to conduct a failure test of the p-flip-flop circuit at high speed. can. In addition, it is possible to select non-defective chips and to limit defective areas in units of functional blocks at high speed.

（発明の効果） 以上説明し友ように、本発明は、フリップフロップ回路
をシーケンシャルに接続したシフト連鎖方式を有し、シ
フト動作によるフリップフロップ回路の試験容易化設計
を施し、機能ブロック単位の階層的分割レイアウｉ施し
た大規模集積回路において、機能ブロック間結線のひと
つであるフリップフロップ回路スキャンパス出力信号が
観測可能なプローバ用パッドを設けることにエフ、フリ
ップフロップ回路の故障試験を高速に行うことができ、
チップの良品選別および機能ブロック単位での不良領域
の限定を高速に行うことができる。(Effects of the Invention) As explained above, the present invention has a shift chain system in which flip-flop circuits are connected sequentially, is designed to facilitate testing of the flip-flop circuit by shift operation, and has a hierarchy of functional blocks. In a large-scale integrated circuit with a divided layout, it is possible to perform high-speed failure tests on flip-flop circuits by providing a prober pad that can observe the scan path output signal of the flip-flop circuit, which is one of the connections between functional blocks. It is possible,
It is possible to quickly select non-defective chips and limit defective areas in units of functional blocks.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明による大規模集積回路の一実施例の構成
図である。 ７・・・プローバ用パッド １０川フリップフロッ１回路FIG. 1 is a block diagram of an embodiment of a large-scale integrated circuit according to the present invention. 7...Prober pad 10 flip-flop 1 circuit

Claims (1)

【特許請求の範囲】[Claims] シーケンシャルに接続されたシフト動作可能な複数のフ
リップフロップ回路を有する大規模集積回路において、
フリップフロップ回路スキャンパス出力信号を観測可能
なプローバ用パッドを設けたことを特徴とする大規模集
積回路。In a large-scale integrated circuit having a plurality of sequentially connected flip-flop circuits capable of shift operation,
A large-scale integrated circuit characterized by being provided with a prober pad capable of observing a flip-flop circuit scan path output signal.
JP29572885A 1985-12-27 1985-12-27 Large-scale integrated circuit Pending JPS62155549A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29572885A JPS62155549A (en) 1985-12-27 1985-12-27 Large-scale integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29572885A JPS62155549A (en) 1985-12-27 1985-12-27 Large-scale integrated circuit

Publications (1)

Publication Number Publication Date
JPS62155549A true JPS62155549A (en) 1987-07-10

Family

ID=17824399

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29572885A Pending JPS62155549A (en) 1985-12-27 1985-12-27 Large-scale integrated circuit

Country Status (1)

Country Link
JP (1) JPS62155549A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6487682B2 (en) 1991-09-18 2002-11-26 Fujitsu Limited Semiconductor integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6487682B2 (en) 1991-09-18 2002-11-26 Fujitsu Limited Semiconductor integrated circuit

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