JPS62153518U - - Google Patents
Info
- Publication number
- JPS62153518U JPS62153518U JP4138186U JP4138186U JPS62153518U JP S62153518 U JPS62153518 U JP S62153518U JP 4138186 U JP4138186 U JP 4138186U JP 4138186 U JP4138186 U JP 4138186U JP S62153518 U JPS62153518 U JP S62153518U
- Authority
- JP
- Japan
- Prior art keywords
- signal processing
- processing circuits
- selection circuit
- output selection
- manual switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Indicating Measured Values (AREA)
Description
第1図は、この考案の電子機器の回路図、第2
図は、従来の電子機器の回路図である。
図において、4はリセツトスイツチ、5は0.
1秒タイマ、6は1秒タイマ、7は制御パルス選
択回路、8は機能切換スイツチ、9は機能切換制
御回路、10は平均車速演算回路、14は距離カ
ウンタ、15は時刻アラーム回路、21は出力選
択回路。尚、図中、同一符号は、同一又は、相当
部分を示す。
Figure 1 is the circuit diagram of the electronic device of this invention, Figure 2 is the circuit diagram of the electronic device of this invention.
The figure is a circuit diagram of a conventional electronic device. In the figure, 4 is a reset switch, 5 is a 0.
1 second timer, 6 is a 1 second timer, 7 is a control pulse selection circuit, 8 is a function changeover switch, 9 is a function changeover control circuit, 10 is an average vehicle speed calculation circuit, 14 is a distance counter, 15 is a time alarm circuit, 21 is a Output selection circuit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
数の信号処理回路10,14,15の夫々の動作
結果又は動作条件等を選択的に出力する出力選択
回路21と、前記複数の信号処理回路10,14
,15に対するその動作制御用の複数の制御パル
スを単一のマニユアルスイツチ4の押圧時間の長
短により夫々独立的に発生する複数の制御パルス
発生回路5,6と、前記出力選択回路21によつ
て選択された前記複数の信号処理回路10,14
,15の何れか1つに対してそれに対応する前記
制御パルスを選択的に供給する制御パルス選択回
路7とからなることを特徴とする電子機器。 A plurality of signal processing circuits 10, 14, 15, an output selection circuit 21 that selectively outputs the operation results or operating conditions of the plurality of signal processing circuits 10, 14, 15, and the plurality of signal processing circuits. 10,14
, 15 by a plurality of control pulse generation circuits 5, 6 which independently generate a plurality of control pulses for controlling the operation of the single manual switch 4 depending on the length of time the single manual switch 4 is pressed, and the output selection circuit 21. The plurality of selected signal processing circuits 10, 14
, 15 selectively supplies the corresponding control pulse to any one of the control pulses.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4138186U JPH053931Y2 (en) | 1986-03-20 | 1986-03-20 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4138186U JPH053931Y2 (en) | 1986-03-20 | 1986-03-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62153518U true JPS62153518U (en) | 1987-09-29 |
JPH053931Y2 JPH053931Y2 (en) | 1993-01-29 |
Family
ID=30856329
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4138186U Expired - Lifetime JPH053931Y2 (en) | 1986-03-20 | 1986-03-20 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH053931Y2 (en) |
-
1986
- 1986-03-20 JP JP4138186U patent/JPH053931Y2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH053931Y2 (en) | 1993-01-29 |