JPS6214877U - - Google Patents
Info
- Publication number
- JPS6214877U JPS6214877U JP10657785U JP10657785U JPS6214877U JP S6214877 U JPS6214877 U JP S6214877U JP 10657785 U JP10657785 U JP 10657785U JP 10657785 U JP10657785 U JP 10657785U JP S6214877 U JPS6214877 U JP S6214877U
- Authority
- JP
- Japan
- Prior art keywords
- correction data
- circuit
- correction
- display area
- convergence
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 12
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Landscapes
- Video Image Reproduction Devices For Color Tv Systems (AREA)
Description
第1図はこの考案に係るデジタルコンバーセン
ス回路の概略構成図、第2図はこの考案の一実施
例を示す構成説明図、第3図はこの考案の回路に
よるコンバーセンス調整中に得られるパラボラ波
信号、第4図は、タイミング発生回路のタイミン
グカウンタの構成例を示す図、第5図はアドレス
発生回路の例を示す図、第6図は第5図の回路の
タイミングチヤート、第7図は第2図のラツチ回
路のラツチタイミングとそのデータを示す説明図
、第8図は第2図の補正量発生部のタイミングを
得る回路を示す図、第9図は第8図の回路のタイ
ミングチヤート、第10図は第2図のメモリ及び
バツフア回路のタイミングを得る回路を示す図、
第11図は第10図の回路のタイミングチヤート
、第12図は第2図のメモリの書き込み読み出し
切換信号発生回路を示す図、第13図はコンバー
ゼンセ回路の概略を示す回路図、第14図は第1
3図の出力回路の具体例を示す回路図、第15図
、第16図はそれぞれ従来のコンバーゼンス回路
によるパラボラ波信号の説明図である。
231,234……信号切換器、232……加
算器、233……ラツチ回路、241……メモリ
、242,245……バツフア回路、243,2
44……ラツチ回路。
Figure 1 is a schematic configuration diagram of a digital convergence circuit according to this invention, Figure 2 is a configuration explanatory diagram showing an embodiment of this invention, and Figure 3 is a parabola obtained during convergence adjustment by the circuit of this invention. FIG. 4 is a diagram showing an example of the configuration of a timing counter in a timing generation circuit, FIG. 5 is a diagram showing an example of an address generation circuit, FIG. 6 is a timing chart of the circuit in FIG. 5, and FIG. is an explanatory diagram showing the latch timing of the latch circuit in FIG. 2 and its data, FIG. 8 is a diagram showing a circuit for obtaining the timing of the correction amount generating section in FIG. 2, and FIG. 9 is a diagram showing the timing of the circuit in FIG. 8. Chart, FIG. 10 is a diagram showing a circuit for obtaining the timing of the memory and buffer circuit of FIG.
FIG. 11 is a timing chart of the circuit in FIG. 10, FIG. 12 is a diagram showing the write/read switching signal generation circuit of the memory in FIG. 2, FIG. 13 is a circuit diagram showing an outline of the convergence circuit, and FIG. 1st
FIG. 3 is a circuit diagram showing a specific example of the output circuit, and FIGS. 15 and 16 are explanatory diagrams of a parabolic wave signal by a conventional convergence circuit, respectively. 231, 234... Signal switcher, 232... Adder, 233... Latch circuit, 241... Memory, 242, 245... Buffer circuit, 243, 2
44...Latch circuit.
Claims (1)
コンバーゼンス補正点を設定し、メモリの前記補
正点に対応したアドレスに補正データを記憶せし
め、前記補正データを読み出すことでコンバーゼ
ンス補正波形を作るデジタルコンバーゼンス回路
において、 前記補正データをその値を補正するために読み
出す読み出し手段と、前記補正データの値を操作
に応じて修正し読み出したアドレスと同じアドレ
スに修正した補正データを書き込む手段と、前記
補正データが前記非表示領域のデータである場合
に、その補正データを強制的に一定の値にして前
記メモリに書き込む手段とを具備したことを特徴
とするデジタルコンバーゼンス回路。[Claims for Utility Model Registration] Setting a plurality of convergence correction points across a display area and a non-display area of a screen, storing correction data in an address corresponding to the correction points in a memory, and reading out the correction data. A digital convergence circuit that generates a convergence correction waveform in a digital convergence circuit that reads out the correction data in order to correct its value, and correction data that corrects the value of the correction data according to an operation and corrects it to the same address as the read address. and, when the correction data is data of the non-display area, a means for forcing the correction data to a constant value and writing it into the memory.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10657785U JPS6214877U (en) | 1985-07-12 | 1985-07-12 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10657785U JPS6214877U (en) | 1985-07-12 | 1985-07-12 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6214877U true JPS6214877U (en) | 1987-01-29 |
Family
ID=30982068
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10657785U Pending JPS6214877U (en) | 1985-07-12 | 1985-07-12 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6214877U (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61284282A (en) * | 1985-06-07 | 1986-12-15 | アツプリカ葛西株式会社 | Assembling toy |
JPH07184223A (en) * | 1993-05-07 | 1995-07-21 | Mitsubishi Electric Corp | Digital convergence device |
-
1985
- 1985-07-12 JP JP10657785U patent/JPS6214877U/ja active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61284282A (en) * | 1985-06-07 | 1986-12-15 | アツプリカ葛西株式会社 | Assembling toy |
JPH07184223A (en) * | 1993-05-07 | 1995-07-21 | Mitsubishi Electric Corp | Digital convergence device |
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