JPS62144157U - - Google Patents

Info

Publication number
JPS62144157U
JPS62144157U JP1986032227U JP3222786U JPS62144157U JP S62144157 U JPS62144157 U JP S62144157U JP 1986032227 U JP1986032227 U JP 1986032227U JP 3222786 U JP3222786 U JP 3222786U JP S62144157 U JPS62144157 U JP S62144157U
Authority
JP
Japan
Prior art keywords
signal
circuit
output
set value
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1986032227U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986032227U priority Critical patent/JPS62144157U/ja
Publication of JPS62144157U publication Critical patent/JPS62144157U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Constituent Portions Of Griding Lathes, Driving, Sensing And Control (AREA)
  • Control Of Position Or Direction (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の制御回路のブロツク図、第2
図は測定信号の波形説明図、第3図は第1図の
,,における波形図。 1:コンパレータ回路、2:タイマー回路、4
:定寸信号回路。
Figure 1 is a block diagram of the control circuit of the present invention, Figure 2 is a block diagram of the control circuit of the present invention.
The figure is an explanatory diagram of the waveform of the measurement signal, and FIG. 3 is a waveform diagram at , , in FIG. 1. 1: Comparator circuit, 2: Timer circuit, 4
: Sizing signal circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 寸法に係る測定信号と設定値Aと比較し、設定
値Aに入つているとき発信するコンパレータ回路
の信号と、この信号のもどり信号aにより設定
時間Tの間だけ出力するタイマー回路の信号との
論理和により、その出力をもつて作動信号とする
定寸回路とからなる自動定寸装置のデジタル制御
回路。
The measurement signal related to the dimension is compared with the set value A, and the signal of the comparator circuit is emitted when the value is within the set value A, and the signal of the timer circuit is output only for the set time T based on the return signal A2 of this signal. A digital control circuit for an automatic sizing device, which consists of a sizing circuit that uses the logical sum of , and uses its output as an activation signal.
JP1986032227U 1986-03-06 1986-03-06 Pending JPS62144157U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986032227U JPS62144157U (en) 1986-03-06 1986-03-06

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986032227U JPS62144157U (en) 1986-03-06 1986-03-06

Publications (1)

Publication Number Publication Date
JPS62144157U true JPS62144157U (en) 1987-09-11

Family

ID=30838704

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986032227U Pending JPS62144157U (en) 1986-03-06 1986-03-06

Country Status (1)

Country Link
JP (1) JPS62144157U (en)

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