JPS62142346A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS62142346A
JPS62142346A JP60283621A JP28362185A JPS62142346A JP S62142346 A JPS62142346 A JP S62142346A JP 60283621 A JP60283621 A JP 60283621A JP 28362185 A JP28362185 A JP 28362185A JP S62142346 A JPS62142346 A JP S62142346A
Authority
JP
Japan
Prior art keywords
conducting layer
conductivity type
trench groove
trench
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60283621A
Other languages
Japanese (ja)
Inventor
Kenji Tominaga
健司 富永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP60283621A priority Critical patent/JPS62142346A/en
Publication of JPS62142346A publication Critical patent/JPS62142346A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate

Landscapes

  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To implement a capacitor having a large storing capacitance, by constituting capacitors between a reverse-conductivity type diffused region formed on the inner surface of a trench groove and a first conducting layer and between the first conducting layer and a second conducting layer, and obtaining the sum of the capacitances of the two capacitors. CONSTITUTION:An element isolating structure 2 is formed in a one-conductivity type semiconductor substrate 1. Then a trench groove 3 is formed. A reverse-conductivity type first impurity diffused region 4 with respect to the semiconductor substrate 1 is formed on the entire inner wall of the trench groove 3 and a part of the semiconductor substrate 1. A first insulating film (dielectric film) 5 is formed on the entire surface. The first conducting layer 6 and the first insulating film 5 at the bottom of the trench grove 3 are removed, and an opening part 8 is formed at the bottom surface of the trench groove. A second insulating film (dielectric film) 7 is formed on the surface of the first conducting film layer 6. Then, a second conducting layer 9 and a second impurity diffused region 10, which has the same conductivity type as that of the first impurity diffused region 4, are formed. The first diffused ration 4 is ohmic-conducted to the second conducting layer 9 through the opening part 8 at the bottom surface of the trench groove and the second diffused region 10. The part becomes a counter electrode for the first conducting layer 6, and electric charge is stored. Thus, the effective capacitor area is strikingly increased.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はダイナミックメモリのセルキャパシタ構造に関
するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to cell capacitor structures for dynamic memories.

従来の技術 第３図の断面図に従来のダイナミックメモリのキャパシ
タ構造を示す。一導電形半導体基板１に素子分離構造２
を形成した後、キャパシタ部に選択的に前記半導体基板
１と反対導電形の不純物拡散層４を形成した後、全面に
絶縁膜５及び選択的に導電膜６を形成し、前記不純物拡
散層４及び導電膜６間に電荷を蓄積してメモリ機能をも
たせる。BACKGROUND OF THE INVENTION A cross-sectional view of FIG. 3 shows a capacitor structure of a conventional dynamic memory. Element isolation structure 2 on one conductivity type semiconductor substrate 1
After forming, an impurity diffusion layer 4 of the opposite conductivity type to the semiconductor substrate 1 is selectively formed in the capacitor portion, an insulating film 5 and a conductive film 6 are selectively formed on the entire surface, and the impurity diffusion layer 4 is And electric charges are accumulated between the conductive films 6 to provide a memory function.

発明が解決しようとする問題点 ダイナミックメモリの高集積化にはメモリセル面積の低
減が必要不可決であるが、構造を変えずにセルキャパシ
タの面積を縮少すると、キャパシタ容量が減少してンフ
トエラー等の問題が発生する。その解決策としては、キ
ャパシタ絶縁膜を薄くする、キャパシタを三次元化して
二次元的セル面積を増大させずに実効的キャパシタ容量
を増大させる等が実施されるが、前者の方法はキャパシ
タ絶縁膜の膜厚が非常に薄くなった場合、歩留や信頼性
に問題が生じる。本発Ｆ！Ａは後者の方法分用いて、そ
の問題点を解決する手段を提供するものである。Problems to be Solved by the Invention It is essential to reduce the area of memory cells in order to increase the integration density of dynamic memories, but if the area of cell capacitors is reduced without changing the structure, the capacitance will decrease and errors will occur. Problems such as this may occur. Solutions to this problem include thinning the capacitor insulating film and making the capacitor three-dimensional to increase the effective capacitance without increasing the two-dimensional cell area. If the film thickness becomes very thin, problems will arise in yield and reliability. Original F! A uses the latter method to provide a means to solve the problem.

問題点を解決するための手段 本発明は、一導電形半導体基板の表面部にトレンチ溝を
有し、同トレンチ溝の内面に反対導電形の拡散領域、誘
電体膜を介して前記拡散領域に対面する第１導電層およ
び誘電体膜を介して前記第１４電層に対面し、かつ、前
記拡散領域に前記トレンチ溝底部で接触した第２導電層
をそなえた半導体記憶装置である。Means for Solving the Problems The present invention has a trench groove on the surface of a semiconductor substrate of one conductivity type, a diffusion region of the opposite conductivity type on the inner surface of the trench groove, and a diffusion region connected to the diffusion region via a dielectric film. The semiconductor memory device includes a second conductive layer that faces the fourteenth conductive layer through a first conductive layer and a dielectric film that face each other and is in contact with the diffusion region at the bottom of the trench.

作　　用 本発明によると、トレンチ溝の内面に形成された反対導
電形の拡散領域と第１導電層との間および第１導電層と
第２導電層との間にそれぞれキャパシタを構成し、同キ
ャパシタ容量も両者の和となるので、大きな蓄積容量の
キャパシタが実現でき、この構造のキャパシタをメモリ
のセルキャパシタに用いることによって、半導体基板上
でのセル占有面積が小さく、実効的に大きな蓄積容量を
もったメモリセルが得られる。According to the present invention, capacitors are formed between the diffusion region of opposite conductivity type formed on the inner surface of the trench groove and the first conductive layer, and between the first conductive layer and the second conductive layer, respectively. Since the capacitor capacitance is the sum of both, a capacitor with a large storage capacity can be realized. By using a capacitor with this structure as a memory cell capacitor, the cell occupies a small area on the semiconductor substrate and can effectively achieve a large storage capacity. A memory cell with .

実施例 第１図に本発明の実施例装置の要部断面図を示す。本発
明では実効的キャパシタ面積を飛躍的に増大させるため
、一導電形の半導体基板１に素子分離構造２を形成した
後、トレンチ溝３′ｆ：形成する。そして、このトレン
チ溝３の内壁全面及び前記半導体基板１の一部に半導体
基板１と反対導電形の第１不純物拡散領域４′ｆｆ：形
成し、全面に第１絶縁膜（誘電体膜）５を形成する。さ
らにトレンチ溝３の内壁全面及び前記半導体基板１の一
部に第１導電層６を形成した後、前記トレンチ溝３底面
の第１導電層６及び第１絶縁膜５を除去してトレンチ溝
底面開口部８を形成する。第１導電層６の表面に第２絶
縁膜（誘電体膜）７を形成した後、前記トレンチ溝底面
開口部８全面及び第２絶縁膜７上の一部に第２導電層９
を形成し、さらにトレンチ溝底面開口部８よシ半導体基
板１に第１不純物拡散領域４と同一定形の第２不純物拡
散領域１０を形成する。Embodiment FIG. 1 shows a sectional view of a main part of an embodiment of the present invention. In the present invention, in order to dramatically increase the effective capacitor area, after forming the element isolation structure 2 on the semiconductor substrate 1 of one conductivity type, the trench 3'f is formed. Then, a first impurity diffusion region 4'ff of a conductivity type opposite to that of the semiconductor substrate 1 is formed on the entire inner wall of the trench groove 3 and a part of the semiconductor substrate 1, and a first insulating film (dielectric film) 5 is formed on the entire surface. form. Further, after forming a first conductive layer 6 on the entire inner wall of the trench groove 3 and a part of the semiconductor substrate 1, the first conductive layer 6 and the first insulating film 5 on the bottom surface of the trench groove 3 are removed, and the bottom surface of the trench groove 3 is removed. An opening 8 is formed. After forming a second insulating film (dielectric film) 7 on the surface of the first conductive layer 6, a second conductive layer 9 is formed on the entire surface of the trench bottom opening 8 and a part of the second insulating film 7.
Further, a second impurity diffusion region 10 having the same shape as the first impurity diffusion region 4 is formed in the semiconductor substrate 1 from the bottom opening 8 of the trench.

第２導電層９０表面に第３絶縁膜１１を形成した後、残
るトレンチ溝を導電膜あるいは絶縁膜１２でうめて平担
化を図る。第１拡散領域４と第２導電層９はトレンチ溝
底面開口部８及び第２拡散領域１０を通じてオーミック
に導通し、共に第１導第２図ａ　”’−ｅに本発明の実
施例を製造工程順断面図を示し、これによって詳しくの
べる。第２図ａに示すように、Ｐ形シリコン単結晶基板
１に選択酸化膜２を形成し、異方性ドライエツチング法
でトレンチ溝３を形成し、用トレンチ溝３の内壁全面及
びシリコン基板１の上面の一部に第１リン拡散領域４を
形成し、さらに全面を熱酸化して第１酸化膜５を形成す
る。次に第２図すに示すように選択的に第１ポリシリコ
ン層６を形成した後、第２図Ｃに示すようにフォトレジ
ストパターンおよび異方性ドライエツチング法を用いて
トレンチ溝底面の第１ポリシリコン層６及び第１酸化膜
５を除去してトレンチ溝底面開口部８全形成し、さらに
第１ポリシリコン層６０表面を酸化して第２　　、酸化
膜７を形成する。After forming the third insulating film 11 on the surface of the second conductive layer 90, the remaining trenches are filled with a conductive film or an insulating film 12 to planarize them. The first diffusion region 4 and the second conductive layer 9 are ohmically conductive through the trench bottom opening 8 and the second diffusion region 10, and both the first conductive layer 4 and the second conductive layer 9 are connected to each other through the trench bottom opening 8 and the second conductive layer 10. A cross-sectional view of the process is shown, and the details will be explained using these.As shown in FIG. , a first phosphorus diffusion region 4 is formed on the entire inner wall of the trench groove 3 and a part of the upper surface of the silicon substrate 1, and then the entire surface is thermally oxidized to form a first oxide film 5. Next, as shown in FIG. After selectively forming the first polysilicon layer 6 as shown in FIG. 2C, the first polysilicon layer 6 and The first oxide film 5 is removed to form the entire trench bottom opening 8, and the surface of the first polysilicon layer 60 is further oxidized to form a second oxide film 7.

次に第２図ｄに示すようにあらかじめリンドーグした第
２ポリシリコン層９を形成し、トレンチ溝底面開口部８
よＩ）　Ｉ）ンを熱拡散して第２リン拡散領域１ｏを形
成して第２ポリシリコン層９と第１リン拡散領域４とが
オーミックに接触できるようにする。最後に第２図ｅに
示すように第２ポリシリコン層９の表面に第２酸化膜１
１を形成後、残るトレンチ溝を第３ポリシリコン１２で
うめ、エッチバンク法で平担化する。Next, as shown in FIG. 2d, a second polysilicon layer 9 which has been doped in advance is formed, and the bottom opening 8 of the trench groove is formed.
The second phosphorus diffusion region 1o is formed by thermally diffusing the phosphorus ions, so that the second polysilicon layer 9 and the first phosphorus diffusion region 4 can come into ohmic contact. Finally, as shown in FIG. 2e, a second oxide film 1 is formed on the surface of the second polysilicon layer 9.
1, the remaining trenches are filled with third polysilicon 12 and planarized by an etch bank method.

発明の効果 以上より明らかなように本発明にかかるダイナミックメ
モリのセルキャパシタは第１導電層と第１不純物拡散領
域との間及び第１導電層と第２導電層との間に電荷蓄積
部を有し、従来の構造に比してトレンチ溝の深さを適描
にとることにより容易に数倍以上の面積利用率をもち、
大容量ダイナミックメモリのメモリセルキャパシタ構造
として非常に有用で６１）、その工業的価値は太きい。Effects of the Invention As is clear from the above, the cell capacitor for a dynamic memory according to the present invention has a charge storage portion between the first conductive layer and the first impurity diffusion region and between the first conductive layer and the second conductive layer. By carefully planning the depth of the trench, the area utilization rate can be easily several times higher than that of the conventional structure.
It is extremely useful as a memory cell capacitor structure for large-capacity dynamic memories61), and its industrial value is great.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明実施例装置の要部断面図、第２図ｄ〜ｅ
は本発明実施例装置を工程順に示す断面図、第３図は従
来例装置の断面図である。 １・・・・・・半導体基板（Ｐ形単結晶シリコン基板）
、２・・・・・・素子分離構造、（選択酸化膜）、３・
・・・・・トレンチ溝、４・・・・・・第１不純物拡散
領域（第１リン拡散領域）、５・・・・・・第１絶縁膜
（第１ゲート酸化膜）、６・・・・・・第１導電層（第
１ポリシリコン層ＬＴ・・・・・・第２絶縁膜（第２ゲ
ート酸化膜）、８・・・・−・トレンチ溝底面開口部、
９・・・・・・第２導電層（第２ポリシリコン層）、１
ｏ・・・・・・第２不純物拡散領域（第２リン拡散領域
）、１１・・・・・・第３絶縁膜（第２ポリシリコン酸
化膜）。 代理人の氏名　弁理士　中　尾　敏　男　ほか１名第２
図 符２図Figure 1 is a sectional view of the main parts of the device according to the present invention, Figures 2 d to e
FIG. 3 is a cross-sectional view showing an apparatus according to an embodiment of the present invention in the order of steps, and FIG. 3 is a cross-sectional view of a conventional apparatus. 1...Semiconductor substrate (P-type single crystal silicon substrate)
, 2... Element isolation structure, (selective oxide film), 3.
...Trench groove, 4...First impurity diffusion region (first phosphorus diffusion region), 5...First insulating film (first gate oxide film), 6... ...First conductive layer (first polysilicon layer LT...Second insulating film (second gate oxide film), 8...Trench bottom opening,
9... Second conductive layer (second polysilicon layer), 1
o... Second impurity diffusion region (second phosphorous diffusion region), 11... Third insulating film (second polysilicon oxide film). Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure 2

Claims (2)

【特許請求の範囲】[Claims] （１）一導電形半導体基板の表面部にトレンチ溝を有し
、同トレンチ溝の内面に反対導電形の拡散領域、誘電体
膜を介して前記拡散領域に対面する第１導電層および誘
電体膜を介して前記第１導電層に対面し、かつ、前記拡
散領域に前記トレンチ溝底部で接触した第２導電層をそ
なえた半導体記憶装置。(1) A trench groove is provided on the surface of a semiconductor substrate of one conductivity type, a diffusion region of the opposite conductivity type is formed on the inner surface of the trench groove, and a first conductive layer and a dielectric material face the diffusion region through a dielectric film. A semiconductor memory device comprising a second conductive layer that faces the first conductive layer through a film and contacts the diffusion region at the bottom of the trench. （２）第１、第２導電層が多結晶シリコンでなる特許請
求の範囲第１項記載の半導体記憶装置。（３）誘電体膜
が酸化シリコン膜でなる特許請求の範囲第１項記載の半
導体記憶装置。(2) The semiconductor memory device according to claim 1, wherein the first and second conductive layers are made of polycrystalline silicon. (3) The semiconductor memory device according to claim 1, wherein the dielectric film is a silicon oxide film.
JP60283621A 1985-12-17 1985-12-17 Semiconductor memory device Pending JPS62142346A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60283621A JPS62142346A (en) 1985-12-17 1985-12-17 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60283621A JPS62142346A (en) 1985-12-17 1985-12-17 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS62142346A true JPS62142346A (en) 1987-06-25

Family

ID=17667880

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60283621A Pending JPS62142346A (en) 1985-12-17 1985-12-17 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS62142346A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02153560A (en) * 1988-08-18 1990-06-13 Matsushita Electron Corp Semiconductor memory device and manufacture thereof
EP3832709A4 (en) * 2018-08-01 2021-08-11 Nissan Motor Co., Ltd. Semiconductor device, power module, and manufacturing method for semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02153560A (en) * 1988-08-18 1990-06-13 Matsushita Electron Corp Semiconductor memory device and manufacture thereof
EP3832709A4 (en) * 2018-08-01 2021-08-11 Nissan Motor Co., Ltd. Semiconductor device, power module, and manufacturing method for semiconductor device
US11664466B2 (en) 2018-08-01 2023-05-30 Nissan Motor Co., Ltd. Semiconductor device, power module and method for manufacturing the semiconductor device

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