JPS62140456A - Semiconductor storage - Google Patents
Semiconductor storageInfo
- Publication number
- JPS62140456A JPS62140456A JP60281027A JP28102785A JPS62140456A JP S62140456 A JPS62140456 A JP S62140456A JP 60281027 A JP60281027 A JP 60281027A JP 28102785 A JP28102785 A JP 28102785A JP S62140456 A JPS62140456 A JP S62140456A
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- groove
- island
- layer
- mos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench
- H10B12/395—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench the transistor being vertical
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- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、１トランジスタ／１キヤパシタのメモリモル
構造を持つ半導体記憶装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device having a memory structure of one transistor/one capacitor.
従来、半導体基板に形成される記憶装置として、−個の
ＭＯＳトランジスタと一個のＭＯＳキャパシタによりメ
モリセルを構成するＭＯ８型ダイナミックＲＡ Ｍ （
ｄ ＲＡＭ ）が知られている。このｄ Ｒ，ＡＭでは
、情報の記憶はＭＯＳキャパシタに電荷が蓄積されてい
るか否かにより行われ、情報の読み出しはＭＯＳキャパ
シタの電荷をＭＯＳトランジスタを介してビット線に放
出してその電位変化を検出することにより行われる。近
年の半導体技術の進歩、特に微細加工技術の進歩により
、ｄＲＡＭの大容量化は急速に進んでいる。Conventionally, as a memory device formed on a semiconductor substrate, there is an MO8 type dynamic RAM (MO8 type dynamic RAM) in which a memory cell is configured by - MOS transistors and one MOS capacitor.
dRAM) is known. In this dR,AM, information is stored depending on whether or not charge is accumulated in the MOS capacitor, and information is read by discharging the charge of the MOS capacitor to the bit line via the MOS transistor and observing the potential change. This is done by detecting. Due to recent advances in semiconductor technology, particularly advances in microfabrication technology, the capacity of dRAM is rapidly increasing.
ｄＲＡＭを更に大容量化する上で最も大きい問題は、メ
モリセル面積を小さくしてしかもＭＯＳキャパシタの容
量を如何に大きく保つかという点にある。ｄＲＡＭの情
報読み出しの際の電位変化の大きさはＭＯＳキャパシタ
の蓄積電荷量で決まり、動作余裕、α線入射等のノイズ
に対する余裕を考えると、最小限必要な電荷量が決まる
。そして蓄積電荷量はＭＯＳキャパシタの容量と印加電
圧で決まり、印加電圧は電源電圧で決まるので、ＭＯＳ
キャパシタ容量をある値以上確保することが必要となる
。The biggest problem in increasing the capacity of dRAM is how to keep the capacitance of the MOS capacitor large while reducing the memory cell area. The magnitude of potential change when reading information from dRAM is determined by the amount of charge accumulated in the MOS capacitor, and the minimum required amount of charge is determined by considering operating margin and margin against noise such as α-ray incidence. The amount of accumulated charge is determined by the capacitance of the MOS capacitor and the applied voltage, and the applied voltage is determined by the power supply voltage, so the MOS
It is necessary to secure the capacitor capacity above a certain value.
ＭＯＳキャパシタの容量を大きくするためには、用いる
ゲート絶縁膜の膜厚を小さくするか、誘電率を大きくす
るか、または面積を大きくすることが必要である。しか
し、絶縁膜厚を小さくすることは信頼性上限界がある。In order to increase the capacitance of a MOS capacitor, it is necessary to reduce the thickness, increase the dielectric constant, or increase the area of the gate insulating film used. However, reducing the thickness of the insulating film has a limit in terms of reliability.
誘電率を大きくすることは例えば、酸化膜（Ｓｉｎ、膜
）に代わって窒化膜（Ｓｉ３Ｎ、膜）を用いること等が
考えられるが、これも主として信頼性上問題があり実用
的でない。One possible way to increase the dielectric constant is to use a nitride film (Si3N film) instead of an oxide film (Sin film), but this also mainly poses problems in terms of reliability and is not practical.
そうすると必要な容量を確保するためには、ＭＯＳキャ
パシタの面積を一定値以上確保することが必要になり、
これがメモリセルの面積を小さくしてｄ几ＡＭの高密度
化、大容量化を達成する上で大きな障害になっている。Then, in order to secure the necessary capacity, it is necessary to secure the area of the MOS capacitor over a certain value.
This is a major obstacle in reducing the area of the memory cell and achieving higher density and larger capacity of the DRAM.
メモリセルの占有面積を大きくすることなくＭＯＳキャ
パシタの容量を大きくする方法として、半導体基板内に
格子縞状の溝を設け、この溝により囲まれた領域を一つ
のメモリセル領域とし、溝の底部を分離領域として、溝
の側面にＭＯＳキャパシタを形成するものが提案されて
いる（特開昭５９−７２１６１号公報）。その構造を第
６図に示す。６１はｐｕｓ ｉ基板であり、これに格子
縞状の＠６２が形成されて、この溝の側壁にキャパシタ
絶縁膜６３を介してキャパシタ電極６４が溝６２に埋め
込まれ、溝で囲まれた島領域を囲むようにＭＯＳキャパ
シタが構成されている。溝６２の底部には素子分離用の
ｐ＋型層６５が形成されている。ＭＯＳトランジスタは
、溝６２で囲まれた領域の基板平坦部にゲート絶縁膜６
６を介してゲート電極６７を形成して構成されている。As a method of increasing the capacitance of a MOS capacitor without increasing the area occupied by the memory cell, a checkered groove is formed in the semiconductor substrate, the area surrounded by this groove is defined as one memory cell area, and the bottom of the groove is It has been proposed that a MOS capacitor is formed on the side surface of a trench as an isolation region (Japanese Patent Application Laid-open No. 72161/1983). Its structure is shown in FIG. Reference numeral 61 denotes a PUS I substrate, on which a checkered pattern @62 is formed, and a capacitor electrode 64 is embedded in the groove 62 through a capacitor insulating film 63 on the side wall of this groove, forming an island region surrounded by the groove. MOS capacitors are arranged to surround it. A p+ type layer 65 for element isolation is formed at the bottom of the groove 62. The MOS transistor has a gate insulating film 6 on a flat part of the substrate in a region surrounded by a trench 62.
A gate electrode 67 is formed through the gate electrode 6.
６８はドレインとなる計型層、６９はＳｉＯ，膜であり
、７０はビット線となる金属配線である。Reference numeral 68 is a metering layer that becomes a drain, 69 is an SiO film, and 70 is a metal wiring that becomes a bit line.
この構成では全ての溝の側面をＭＯＳキャパシタとして
利用しているため、大きい容量を容易に得ることができ
るという利点を有する。反面、溝で囲まれた島領域が一
つのメモリセル領域に対応し、かつこの島領域内で中央
部にコンタクト孔を設け、その周囲にＭＯ８Ｉ−ランジ
スタのゲート電極を形成するため、ＭＯＳトランジスタ
の占有面積が大きいものとなり、結局メモリセル全体と
しての占有面積を充分に小さくすることができない、と
いう欠点があった。This configuration has the advantage that a large capacitance can be easily obtained because the side surfaces of all the grooves are used as MOS capacitors. On the other hand, since the island region surrounded by the groove corresponds to one memory cell region, and a contact hole is provided in the center of this island region, and the gate electrode of the MO8I-transistor is formed around it, the MOS transistor is This results in a large occupied area, which has the disadvantage that the occupied area of the memory cell as a whole cannot be made sufficiently small.
又、１つの島領域に１つのメモリセルしか形成できない
ため、集積度が上がらないという問題点があった。Further, since only one memory cell can be formed in one island region, there is a problem that the degree of integration cannot be increased.
本発明は上記の点に鑑みなされたもので、メモリセル占
有面積を小さくしてしかも充分なキャパシタ容量を実現
した半導体記憶装置を提供することを目的とする。The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor memory device that reduces the area occupied by memory cells and realizes sufficient capacitor capacity.
本発明では、基板上に格子縞状の溝により分離された複
数の島状半導体層が配列形成され、各島状半導体層にそ
れぞれ１トランジスタ／１キヤパシタ構成のメモリセル
が形成される。この場合、ＭＯＳキャパシタは溝の途中
までキャパシタ電極が埋め込まれた状態で溝側壁を利用
して形成され、ＭＯＳトランジスタはこのキャパシタ電
極上にゲート電極が埋め込まれた状態でやはり溝側壁を
利用して形成される。従って溝で囲まれた島状半導体層
の上面にはＭＯ８Ｉ−ランジスタのドレイン領域のみが
設けられる。In the present invention, a plurality of island-shaped semiconductor layers separated by lattice-shaped grooves are arranged and formed on a substrate, and a memory cell having a one-transistor/one-capacitor configuration is formed in each island-shaped semiconductor layer. In this case, the MOS capacitor is formed using the trench sidewalls with the capacitor electrode buried halfway into the trench, and the MOS transistor is formed using the trench sidewalls with the gate electrode buried on the capacitor electrode. It is formed. Therefore, only the drain region of the MO8I transistor is provided on the upper surface of the island-shaped semiconductor layer surrounded by the groove.
又、島状半導体層の対向する側壁部には絶縁膜が埋設さ
れ、これ以外の溝に前記キャパシタ電極とゲート電極が
埋め込まれる。従って２ｃｅｌｌ／１ｓｌａｎｄ 構
成が達成される。Further, an insulating film is buried in the opposing sidewall portions of the island-shaped semiconductor layer, and the capacitor electrode and the gate electrode are buried in the other grooves. Therefore, a 2cell/1sland configuration is achieved.
本発明によれば、ＭＯＳキャパシタのみならずＭＯＳト
ランジスタも溝側壁を利用して形成されるため、メモリ
セル占有面積を従来に比べて小さいものとすることがで
き、しかもキャパシタ容量は島状半導体層を取り囲む側
面を利用することで充分大きい値を確保することができ
る。従って高集積化ｄ ＲＡ Ｍを実現することができ
る。According to the present invention, since not only the MOS capacitor but also the MOS transistor is formed using the trench sidewall, the area occupied by the memory cell can be made smaller than that of the conventional method, and the capacitance is smaller than that of the island-shaped semiconductor layer. A sufficiently large value can be secured by using the side surfaces surrounding the . Therefore, highly integrated dRAM can be realized.
又、２ ｃｅｌｌ／１ｓｌａｎｄ構成が可能となるため
高集積度が可能となる。Furthermore, since a 2 cell/1 sland configuration is possible, a high degree of integration is possible.
また本発明によれば、キャパシタ電極およびトランジス
タのゲート電極が共に格子縞状溝に埋め込まれるため、
これらの電極が形成された後の基板表面を平坦なものと
することができ、その後の金属配線工程で微細パターン
の形成が容易になるこのことはｄ几Ａ Ｍの一層の高集
積化と信頼性向上に寄与する。Further, according to the present invention, since both the capacitor electrode and the gate electrode of the transistor are embedded in the checkered groove,
After these electrodes are formed, the surface of the substrate can be flattened, making it easier to form fine patterns in the subsequent metal wiring process. Contributes to sexual improvement.
以下本発明の詳細な説明する。 The present invention will be explained in detail below.
第１図は一実施例のｄ几ＡＭ構成を示すもので、平面図
を示し、第２図（ａ）〜（ｉ）はＡ −Ａ１位置の製造
工程断面図である。FIG. 1 shows a plan view of the d-type AM configuration of one embodiment, and FIGS. 2(a) to 2(i) are sectional views of the manufacturing process at the A-A1 position.
即ち、り型Ｓｉ基板１１上にｐｓｉ層１２が設けられ、
そのフィールド領域にｆ８ ｉ基板１１ｉＣ達する溝が
堀られてＳｉ島がアレイ状に形成されている。そして、
Ｓｉ島は、一方向について溝が５ｉｎ２膜１５で埋込ま
れ、残る溝の下部にキャパシタ電極１９が埋設され、溝
上部にはゲート電極２２が設けられている。ゲート電極
２２は各セル連続して設けられ、ワード線を構成してい
る。またＳｉ島上部にはドレイン２３が設けられ、ビッ
ト線であるＡ４２５がワード線と直交して配設されてい
る。That is, a psi layer 12 is provided on a rectangular Si substrate 11,
A groove reaching the f8 i substrate 11iC is dug in the field region, and Si islands are formed in an array. and,
In the Si island, a groove is filled in one direction with a 5in2 film 15, a capacitor electrode 19 is buried in the lower part of the remaining groove, and a gate electrode 22 is provided in the upper part of the groove. The gate electrode 22 is provided continuously in each cell and constitutes a word line. Further, a drain 23 is provided above the Si island, and a bit line A425 is arranged perpendicular to the word line.
従って、Ｓｉｎ、膜１５を挟んでＳｉ島には側壁を利用
して２つのｄＲＡＭセルが・配される事になる。Therefore, two dRAM cells are arranged on the Si island with the Si film 15 in between, using the side walls.
製遁ｌこ際しては、高不純物濃度のｐ型Ｓｉ基板１１上
こ低不純物濃度のｐ−型Ｓｉ層１２をエピタキシャル成
長させ、島状半導体領域を形成する部分にシリコン酸化
膜１３を形成し、これをフォトレジスト１４をマスクに
パターニングする（第２図ａ）。At this time, a p-type Si layer 12 with a low impurity concentration is epitaxially grown on a p-type Si substrate 11 with a high impurity concentration, and a silicon oxide film 13 is formed on the part where the island-shaped semiconductor region is to be formed. This is then patterned using the photoresist 14 as a mask (FIG. 2a).
次屹これらをマスクにｆ型Ｓｉ層１２を反応性イオンエ
ツチング（ＲＩＢ）でエツチングし、格子縞状の溝をＳ
ｉ基板１１に達して形成する。そして、この溝にＣＶＤ
５ｉＯ，膜１５を平担に埋込む（第２図ｂ）。Next, using these as a mask, the f-type Si layer 12 is etched by reactive ion etching (RIB) to form checkered grooves.
The i-substrate 11 is reached and formed. Then, CVD is applied to this groove.
5iO, and the film 15 is buried flat (FIG. 2b).
次に、複数のＳｉ島を横切ってフォトレジストマスク１
６をストライプ状ｌこ設け、これをマスクニシテ、ＣＶ
Ｄ Ｓ ｉｏ ２ 膜１５ ヲＲＩ Ｅでｘ−、チン
グする。（第２図Ｃ）。これにより、ワード線配設方向
に、Ｓｉ島間の湾力≦ＣＶＤ５ｉＯ！膜で埋められる。Next, a photoresist mask 1 is applied across the plurality of Si islands.
6 is provided in a striped pattern, and this is used as a mask, CV
DS io 2 film 15 x- and ching with RI E. (Figure 2C). As a result, in the word line arrangement direction, the gulf force between Si islands ≦CVD5iO! Filled with membrane.
この後、ＰＳ、ＧＰＩＸ（図示せず）を全面にＣＶＩ）
被着し、熱処理を施すことにより酸化膜１５を除去した
部分のＳｉ島側壁にリンを拡散してｎ−型層１７を形成
し、ＰＥＧ膜を除去してキャパシタ絶縁膜１８として１
００Ａ程度の熱酸化膜を形成する（第２図ｄ）。After this, PS, GPIX (not shown) is applied to the entire surface (CVI)
The n-type layer 17 is formed by diffusing phosphorus onto the side wall of the Si island where the oxide film 15 has been removed by applying heat treatment, and the PEG film is removed to form a capacitor insulating film 18.
A thermal oxide film of about 00A is formed (FIG. 2d).
次いで、第１層多結晶シリコン膜１９を全面に堆積する
。この時、多結晶シリコン膜１９の表面は図示のように
平担化する（第２図ｅ）。そして、多結晶シリコン戻１
９を全面エツチングして溝の底部に残し、キャパシタ電
極とする。このキャパシタ電極１９は溝の途中まで埋込
まれた状態で形成される。Next, a first layer polycrystalline silicon film 19 is deposited over the entire surface. At this time, the surface of the polycrystalline silicon film 19 is flattened as shown in the figure (FIG. 2e). And polycrystalline silicon return 1
9 is etched on the entire surface and left at the bottom of the groove to serve as a capacitor electrode. This capacitor electrode 19 is formed so as to be buried halfway into the groove.
この後、キャパシタ絶縁膜１８を除去し、ＢＳＧ膜（図
示しない）等によって側壁及び上面にトランジスタのチ
ャネル領域となるｐ−型層２０を形成する（第２図ｆ）
。このとき、ｆ型層２０の形成時の拡散によってキャパ
シタの基板側電極となるｎ−型層１６が後退する。これ
を補償するためには予めこの後過分を引込んでキャパシ
タ電極の厚みを少し厚く選んでおいて、ｐ−型層２０の
形成後にキャパシタを極１９表面を僅かにエツチングす
る争が望よしい。Thereafter, the capacitor insulating film 18 is removed, and a p-type layer 20, which will become the channel region of the transistor, is formed on the sidewalls and top surface using a BSG film (not shown) or the like (FIG. 2f).
. At this time, the n-type layer 16, which becomes the substrate-side electrode of the capacitor, recedes due to diffusion during the formation of the f-type layer 20. In order to compensate for this, it is preferable to select a slightly thicker capacitor electrode by retracting the excess, and then slightly etching the surface of the capacitor electrode 19 after forming the p-type layer 20.
この後、ゲートｅａ膜２１として例えば２００Ａ厚程度
の熱酸化膜を各ｐ−型層の表面に形成し、次いでＭＯＳ
トランジスタのゲート電極として用いる第２層多結晶シ
リコン膜２２をＣＶＤで堆積する（第２図ｇ）。この第
２層多結晶シリコン膜２２は、図から明らかなように第
１層多結晶シリコン膜の場合のように表面は平担化しな
い。そして、この多結晶シリコン膜２２を几ＩＢなどの
異方性エツチングにより全面エツチングして８１島の側
壁部及び埋込んだ酸化膜１５の側壁部に自己整合して残
してゲート電極２３を形成する。こうして縦方向につな
がるゲート電極２３はワード線を構成する。この後、例
えばヒ素のイオン注入を行なって各Ｓｔ島表面にＭＯＳ
トランジスタのドレインとなるｎ型層２３を形成する（
第２図１１ ）。Thereafter, a thermal oxide film with a thickness of, for example, about 200A is formed as the gate EA film 21 on the surface of each p-type layer, and then the MOS
A second polycrystalline silicon film 22 to be used as the gate electrode of the transistor is deposited by CVD (FIG. 2g). As is clear from the figure, the surface of the second layer polycrystalline silicon film 22 is not flattened as in the case of the first layer polycrystalline silicon film. Then, this polycrystalline silicon film 22 is etched over the entire surface by anisotropic etching such as IB etching, and is left in self-alignment on the sidewalls of the 81 islands and the sidewalls of the buried oxide film 15 to form the gate electrode 23. . The gate electrodes 23 connected in the vertical direction constitute word lines. After this, for example, arsenic ion implantation is performed to form a MOS on the surface of each St island.
Form an n-type layer 23 that will become the drain of the transistor (
Figure 2 11).
最後に、全面にＣＶＤ酸化膜２４を形成し、これに横方
向のメモリセルのドレインを接続し、ヒツト線となるｋ
ｔ配線２５を形成する（第２図１）。Finally, a CVD oxide film 24 is formed on the entire surface, and the drains of the memory cells in the horizontal direction are connected to this, and the k
A t-wiring 25 is formed (FIG. 2 1).
かくして、ゲート電極はＳｉ島の１１１１１壁部に配置
されることとなり、１つの８１島に２つのメモリセルが
配され、キャパシタ容量が大きく高奮度のｄＲＡＭセル
か提供される。In this way, the gate electrode is placed on the 11111 wall of the Si island, two memory cells are placed on one 81 island, and a dRAM cell with a large capacitance and high performance is provided.
第３図は、ワード線の取り出しを示す、第１図のＢ −
Ｂ’断面を表わしている。FIG. 3 shows the extraction of word lines from B-- in FIG. 1.
B' section is shown.
第１図の（１１で示した線は、周辺回路領域とメモリセ
ルアレイ領域との境界を示している。この例では、ワー
ド線は９０°ねじられて周辺のｐ−型平担なＳ ｉ 層
１２上に導出されている。これは次の様にして形成する
事が出来る。即ち、第２図（ｇ）の上程で、第２層多結
晶シリコン漠２２を被着した後、レジストマスク（図示
せず）を用いて第１図で（ｎ）として示した領域部の段
差に被着された第２層多結晶シリコン膜２２をウェット
エツチングで除去第２ｊ輪多結晶シリコン膜２２を覆い
（第３図ａ）へ
それから第２図（ｈ）で説明したＲＩＥによる第２層多
結晶シリコン膜２２の全面エツチングを行なう。The line (11) in FIG. 1 indicates the boundary between the peripheral circuit area and the memory cell array area. 12. This can be formed in the following manner. That is, in the upper part of FIG. The second layer polycrystalline silicon film 22 deposited on the step in the region shown as (n) in FIG. 3a). Then, the entire surface of the second layer polycrystalline silicon film 22 is etched by RIE as explained in FIG. 2(h).
これにより、第３図（ｂ）に示す如くワード線は９０゜
ねじられて周辺部に延在される。希望によりこの延在部
上でｋｔとのコンタクトを取っても良い。As a result, the word line is twisted by 90 degrees and extended to the periphery as shown in FIG. 3(b). Contact with kt may be made on this extension if desired.
上記導出例では、第１図の（Ｉｔ）の部分の第２層多結
晶シリコン膜２２をフォトレジストマスクを用いて除去
した。しかし、この様な選択除去に代えて次の方法も可
能である。In the above derivation example, the second layer polycrystalline silicon film 22 in the part (It) in FIG. 1 was removed using a photoresist mask. However, instead of such selective removal, the following method is also possible.
即ち、第２図（ａ）の工程に先立って、第１図の周辺回
路とメモリセルアレイ領域との境界部のｐ−型Ｓｉ層に
Ｓｉ基板１１に達するＶ溝をテーパーエツチングにより
形成しておく。これにより、境界■のｆ型Ｓｉ層１２段
差部に例えば４ｆの傾きを持たせる。このようにすると
、第３図（ａ）の工程で第２層多結晶シリコン膜２２に
レジストパターン３１を載せて、几ＩＥで全面エツチン
グする時、隣り合うワード線間は自動的に分離される。That is, prior to the process shown in FIG. 2(a), a V groove reaching the Si substrate 11 is formed in the p-type Si layer at the boundary between the peripheral circuit and the memory cell array region shown in FIG. 1 by taper etching. . As a result, the stepped portion of the f-type Si layer 12 at the boundary (3) is given an inclination of, for example, 4f. By doing this, when the resist pattern 31 is placed on the second layer polycrystalline silicon film 22 and the entire surface is etched using the IE in the process shown in FIG. .
以上の実施例では、Ｓｉ島を４５°回転させた矩形の平
面パターンとした。しかし、第４図（ａ）に示す如く、
回転前の形としてもよいし、（ｂ）のように円形として
もよく、又、（Ｃ）に示す如く小判状の長円パターンと
しても良い。In the above embodiment, a rectangular planar pattern in which the Si islands were rotated by 45 degrees was used. However, as shown in Figure 4(a),
It may be in the shape before rotation, it may be circular as in (b), or it may be in an oval-shaped oval pattern as shown in (c).
これらの形は、先に本発明者により提案された１ ｃｅ
ｌｌ／１ｓｌａｎｄ形態のメモリセル（特願昭６０−８
０６１９号）に適用する事が可能である。These shapes are similar to the 1ce previously proposed by the inventor.
ll/1sland type memory cell (patent application 1986-8)
No. 0619).
第５図は、この様な例屹第４図（ｂ）の円形パターンを
適用した例を示しており、（ａ）は平面図、（ｂ）。FIG. 5 shows an example in which the circular pattern shown in FIG. 4(b) is applied, where (a) is a plan view and FIG. 5(b) is a plan view.
（Ｃ）は夫々Ａ−ＡＩ、Ｂ−Ｂｌ断面を示している。酸
化膜１５及びこれをパターニングするレジストマスク１
６を設けないだけで、後は第２図（ａ）〜（ｉ）と同一
工程で形成される。(C) shows the A-AI and B-Bl cross sections, respectively. Oxide film 15 and resist mask 1 for patterning it
6 is not provided, and the rest is formed in the same process as in FIGS. 2(a) to 2(i).
即ち、Ｓｉ島は、全周がキャパシタ電極とゲート電極の
積１−構造で囲まれ、ｌ ｃｅｌｌ／１ｓｌａｎｄ構成
となっており、第２図（ｇ）の工程で第２層多結晶シリ
コン膜２２を、ワード線形成方向のＳｉ島間の溝幅の１
／２より厚く成長させる事ｌこより、連続したワード線
と為している。That is, the Si island is surrounded all around by a product 1-structure of a capacitor electrode and a gate electrode, and has an 1 cell/1 sland structure, and the second layer polycrystalline silicon film 22 is is 1 of the groove width between Si islands in the word line forming direction.
By growing the word line thicker than /2, a continuous word line is formed.
さて、以上の説明では、センスアンプとつながれる一対
のビット線（ＢＬ、、ＢＬ’、）、（ＢＬ、、ＢＬＩ、
）は夫々１つおきにＳｉ島と接続したフォールデッド・
ビットライン構成としたか、オープン・ビットライン構
成として良い。また、素子間のアイソレーションはｐ”
Ｗ基ｒ１１１により行なったが、このようなエピタキシ
ャル成長ウェハを用いず、ｐ−型Ｓｉ基板を用いて、素
子間の溝底部にフィールド絶縁膜を一定厚さに埋設した
り、その下部に１層を形成する方法を採用する墨も出来
る。Now, in the above explanation, a pair of bit lines (BL,, BL',), (BL,, BLI,
) are folded islands connected to every other Si island.
A bit line configuration or an open bit line configuration may be used. Also, the isolation between elements is p”
However, instead of using such an epitaxial growth wafer, a p-type Si substrate is used, and a field insulating film is buried to a constant thickness at the bottom of the groove between the elements, or a single layer is placed below it. You can also make ink using the forming method.
第１図は本発明の実施例の平面図、第２図はその工程断
面図、第３図は導出部の断面図、第４図はＳｉ島の例を
示す平面図、第５図は他の例を示す図、第６図は従来例
を示す断面図である。
代理人 弁理士 則 近 憲 佑
同 竹 花 喜久男
第 １ 図
ＣＣ）
第 ２ 図
（ｄ）
（ｅ）
（Ｊ）
第 ２ 図
第 ２ 図
（α）
第３図
（ａ）
第 ４ 図
第５図
（ｂ）
（Ｃ）
第５図FIG. 1 is a plan view of an embodiment of the present invention, FIG. 2 is a sectional view of the process, FIG. 3 is a sectional view of the lead-out part, FIG. 4 is a plan view showing an example of Si islands, and FIG. FIG. 6 is a sectional view showing a conventional example. Agent Patent Attorney Yudo Nori Chika Kikuo Takehana Figure 1 CC) Figure 2 (d) (e) (J) Figure 2 Figure 2 (α) Figure 3 (a) Figure 4 Figure 5 (b) (C) Figure 5
Claims (1)
島状半導体領域と、この島状半導体領域の対向する側壁
部分の溝に埋設された絶縁膜と、この絶縁膜から露出す
る前記溝部に順次埋込まれたキャパシタ電極及びゲート
電極と、前記島状半導体領域上面に設けられた逆導電型
領域とを備えた事を特徴とする半導体記憶装置。An island-shaped semiconductor region formed by providing a groove in a field region of a semiconductor substrate, an insulating film buried in the groove on opposing sidewall portions of this island-shaped semiconductor region, and a groove portion exposed from this insulating film sequentially buried. 1. A semiconductor memory device comprising a capacitor electrode and a gate electrode embedded therein, and an opposite conductivity type region provided on an upper surface of the island-shaped semiconductor region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60281027A JPH0793372B2 (en) | 1985-12-16 | 1985-12-16 | Semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60281027A JPH0793372B2 (en) | 1985-12-16 | 1985-12-16 | Semiconductor memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62140456A true JPS62140456A (en) | 1987-06-24 |
| JPH0793372B2 JPH0793372B2 (en) | 1995-10-09 |
Family
ID=17633265
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60281027A Expired - Lifetime JPH0793372B2 (en) | 1985-12-16 | 1985-12-16 | Semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0793372B2 (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6351667A (en) * | 1986-08-21 | 1988-03-04 | Matsushita Electronics Corp | Semiconductor memory device |
| JPS6428951A (en) * | 1987-07-24 | 1989-01-31 | Sony Corp | Semiconductor memory device |
| JPH01108762A (en) * | 1987-10-21 | 1989-04-26 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JPH02132855A (en) * | 1988-06-09 | 1990-05-22 | Texas Instr Inc <Ti> | Dynamic ram cell having insulating trench-capacitor |
| US5028980A (en) * | 1988-12-21 | 1991-07-02 | Texas Instruments Incorporated | Trench capacitor with expanded area |
| US5057896A (en) * | 1988-05-28 | 1991-10-15 | Fujitsu Limited | Semiconductor device and method of producing same |
| US5106775A (en) * | 1987-12-10 | 1992-04-21 | Hitachi, Ltd. | Process for manufacturing vertical dynamic random access memories |
| EP0510604A2 (en) * | 1991-04-23 | 1992-10-28 | Canon Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
| EP0905771A2 (en) * | 1997-09-30 | 1999-03-31 | Siemens Aktiengesellschaft | Trench capacitor DRAM cell and method of making the same |
| WO2002011200A1 (en) * | 2000-07-31 | 2002-02-07 | Infineon Technologies Ag | Semiconductor memory cell arrangement and method for producing the same |
| WO2003028104A3 (en) * | 2001-09-05 | 2003-08-14 | Infineon Technologies Ag | Semiconductor memory with memory cells comprising a vertical selection transistor and method for production thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52134385A (en) * | 1976-05-04 | 1977-11-10 | Siemens Ag | Semiconductor memory |
| JPS57196565A (en) * | 1981-05-22 | 1982-12-02 | Ibm | Method of forming vertical fet |
| JPS59117258A (en) * | 1982-12-24 | 1984-07-06 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| JPS60152056A (en) * | 1984-01-20 | 1985-08-10 | Hitachi Ltd | Semiconductor memory device |
| JPS61174670A (en) * | 1984-10-31 | 1986-08-06 | テキサス インスツルメンツ インコ−ポレイテツド | Dram cell and making thereof |
-
1985
- 1985-12-16 JP JP60281027A patent/JPH0793372B2/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52134385A (en) * | 1976-05-04 | 1977-11-10 | Siemens Ag | Semiconductor memory |
| JPS57196565A (en) * | 1981-05-22 | 1982-12-02 | Ibm | Method of forming vertical fet |
| JPS59117258A (en) * | 1982-12-24 | 1984-07-06 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| JPS60152056A (en) * | 1984-01-20 | 1985-08-10 | Hitachi Ltd | Semiconductor memory device |
| JPS61174670A (en) * | 1984-10-31 | 1986-08-06 | テキサス インスツルメンツ インコ−ポレイテツド | Dram cell and making thereof |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6351667A (en) * | 1986-08-21 | 1988-03-04 | Matsushita Electronics Corp | Semiconductor memory device |
| JPS6428951A (en) * | 1987-07-24 | 1989-01-31 | Sony Corp | Semiconductor memory device |
| JPH01108762A (en) * | 1987-10-21 | 1989-04-26 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| US5106775A (en) * | 1987-12-10 | 1992-04-21 | Hitachi, Ltd. | Process for manufacturing vertical dynamic random access memories |
| US5057896A (en) * | 1988-05-28 | 1991-10-15 | Fujitsu Limited | Semiconductor device and method of producing same |
| JPH02132855A (en) * | 1988-06-09 | 1990-05-22 | Texas Instr Inc <Ti> | Dynamic ram cell having insulating trench-capacitor |
| US5028980A (en) * | 1988-12-21 | 1991-07-02 | Texas Instruments Incorporated | Trench capacitor with expanded area |
| US6373099B1 (en) | 1991-04-23 | 2002-04-16 | Canon Kabushiki Kaisha | Method of manufacturing a surrounding gate type MOFSET |
| EP0510604A3 (en) * | 1991-04-23 | 2001-05-09 | Canon Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
| EP0510604A2 (en) * | 1991-04-23 | 1992-10-28 | Canon Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
| EP0905771A2 (en) * | 1997-09-30 | 1999-03-31 | Siemens Aktiengesellschaft | Trench capacitor DRAM cell and method of making the same |
| EP0905771A3 (en) * | 1997-09-30 | 2001-10-24 | Siemens Aktiengesellschaft | Trench capacitor DRAM cell and method of making the same |
| WO2002011200A1 (en) * | 2000-07-31 | 2002-02-07 | Infineon Technologies Ag | Semiconductor memory cell arrangement and method for producing the same |
| US6853023B2 (en) | 2000-07-31 | 2005-02-08 | Infineon Technologies Ag | Semiconductor memory cell configuration and a method for producing the configuration |
| WO2003028104A3 (en) * | 2001-09-05 | 2003-08-14 | Infineon Technologies Ag | Semiconductor memory with memory cells comprising a vertical selection transistor and method for production thereof |
| US6977405B2 (en) | 2001-09-05 | 2005-12-20 | Infineon Technologies, Ag | Semiconductor memory with memory cells comprising a vertical selection transistor and method for fabricating it |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0793372B2 (en) | 1995-10-09 |
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