JPS62138228U - - Google Patents

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Publication number
JPS62138228U
JPS62138228U JP2379486U JP2379486U JPS62138228U JP S62138228 U JPS62138228 U JP S62138228U JP 2379486 U JP2379486 U JP 2379486U JP 2379486 U JP2379486 U JP 2379486U JP S62138228 U JPS62138228 U JP S62138228U
Authority
JP
Japan
Prior art keywords
power
switch
input
control signal
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2379486U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP2379486U priority Critical patent/JPS62138228U/ja
Publication of JPS62138228U publication Critical patent/JPS62138228U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例に係る電源制御回路
の構成を示すブロツク図、第２図は第１図を説明
するためのタイミングチヤート、第３図は従来の
電源制御回路の構成を示すブロツク図、第４図は
そのタイミングチヤートである。 １……時計ＬＳＩ、２……電源オン／オフスイ
ツチ、５，６……フリツプフロツプ。 FIG. 1 is a block diagram showing the configuration of a power supply control circuit according to an embodiment of the present invention, FIG. 2 is a timing chart for explaining FIG. 1, and FIG. 3 is a diagram showing the configuration of a conventional power supply control circuit. The block diagram and FIG. 4 are its timing chart. 1... Clock LSI, 2... Power on/off switch, 5, 6... Flip-flop.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 時計のアラームにより起動する計算機システム
の電源をオン、オフ制御する回路であつて、電源
オン／オフスイツチと、上記電源のオン中に上記
スイツチを入力するも直接的には電源オフ用の制
御信号は発生せず、上記スイツチの入力に基づく
中央処理部のステータス処理に応じて電源オフ用
の制御信号を発生する手段とを有することを特徴
とする電源制御回路。 This is a circuit that controls the power on and off of a computer system that is activated by a clock alarm.It is a power on/off switch, and although the above switch is input while the power is on, there is no direct control signal for power off. 1. A power supply control circuit comprising means for generating a power-off control signal in response to status processing of a central processing unit based on input from the switch.
JP2379486U 1986-02-20 1986-02-20 Pending JPS62138228U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2379486U JPS62138228U (en) 1986-02-20 1986-02-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2379486U JPS62138228U (en) 1986-02-20 1986-02-20

Publications (1)

Publication Number Publication Date
JPS62138228U true JPS62138228U (en) 1987-08-31

Family

ID=30822421

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2379486U Pending JPS62138228U (en) 1986-02-20 1986-02-20

Country Status (1)

Country Link
JP (1) JPS62138228U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5886618A (en) * 1981-11-18 1983-05-24 Mitsubishi Electric Corp Automatic power supply application device for computer system
JPS5933521A (en) * 1982-08-18 1984-02-23 Nec Corp Power supply control circuit
JPS5941025A (en) * 1982-08-31 1984-03-07 Toshiba Corp Power supply controller

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5886618A (en) * 1981-11-18 1983-05-24 Mitsubishi Electric Corp Automatic power supply application device for computer system
JPS5933521A (en) * 1982-08-18 1984-02-23 Nec Corp Power supply control circuit
JPS5941025A (en) * 1982-08-31 1984-03-07 Toshiba Corp Power supply controller

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