JPS62137859A - Lead frame - Google Patents
Lead frameInfo
- Publication number
- JPS62137859A JPS62137859A JP27970585A JP27970585A JPS62137859A JP S62137859 A JPS62137859 A JP S62137859A JP 27970585 A JP27970585 A JP 27970585A JP 27970585 A JP27970585 A JP 27970585A JP S62137859 A JPS62137859 A JP S62137859A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- island
- resin
- fixed
- island part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に使用されるリードフレームに関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lead frame used in a semiconductor device.
従来のこの種のリードフレームは適当な金属板をエツチ
ング法またはプレス法等にょシ成形し、更にダイボンデ
ィング部及び金属細線接続部に貴金属メッキが施されて
使用されている。Conventionally, this type of lead frame is used by forming a suitable metal plate by etching or pressing, and further plating the die bonding portion and the thin metal wire connection portion with noble metal.
このリードフレームのアイランド部2は第2図に示すよ
うに、その大きさに関係なく1枚の平担な板よす形成さ
れている。尚、第2図において、1は吊りビンである。As shown in FIG. 2, the island portion 2 of this lead frame is formed as a single flat plate regardless of its size. In addition, in FIG. 2, 1 is a hanging bottle.
上述した従来のリードフレームは、アイランドの大きさ
に関係なく1枚の平担な板より形成されているため、樹
脂封止した場合、リードフレーム、半導体基板、回路接
続用の金属細線及びモールド樹脂相互の熱膨張係数の差
による回路の断線および′モールド樹脂に発生するクラ
ック等により、半導体装置の信頼性が低下するという問
題点かあ、りた。The conventional lead frame described above is formed from one flat plate regardless of the size of the island, so when resin-sealed, the lead frame, semiconductor substrate, thin metal wire for circuit connection, and mold resin There was a problem in that the reliability of the semiconductor device decreased due to circuit breakage and cracks occurring in the molding resin due to the difference in their thermal expansion coefficients.
本発明の目的は、回路の断線及びモールド樹脂に発生す
るクラレフを少くし、信頼性の向上した半導体装置が得
られるリードフレームを提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a lead frame that reduces circuit disconnection and clarification occurring in mold resin, and provides a semiconductor device with improved reliability.
本発明のリードフレームはアイランド部にスリットを有
するものである。The lead frame of the present invention has a slit in the island portion.
次に本発明の実施例について図面を参照して説明する。 Next, embodiments of the present invention will be described with reference to the drawings.
第1図は本発明の一実施例のアイランド部の平面図であ
る。FIG. 1 is a plan view of an island portion according to an embodiment of the present invention.
第1図において、リードフレームのアイラントドを固着
し、樹脂でモールドした場合歪応力が働く方向に対して
直角方向が効果的である。In FIG. 1, when the eyelets of the lead frame are fixed and molded with resin, the direction perpendicular to the direction in which strain stress is applied is effective.
この様に構成された本実施例のアイランド部2に半導体
、ベレットを固着し、樹脂で固着した場合、発生する歪
による応力はこのスリット3の部分に吸収され他の部分
に影響を及ぼす事は少くなる。When a semiconductor and a pellet are fixed to the island part 2 of this embodiment configured in this way and fixed with resin, the stress due to the generated strain is absorbed by the slit 3 and does not affect other parts. It becomes less.
てもよい。It's okay.
以上説明したように本発明は、リードフレームのアイラ
ンド部にスリットを設けることによシ、アイランド部に
半導体ベレットを固着し樹脂モールドを行った場合、発
生する歪の応力を吸収できるので、回路の断線及びモー
ルド樹脂に発生するクラックが少くなり、信頼性の向上
した半導体装置を製造することのできるリードフレーム
が得られる効果がちる。As explained above, by providing a slit in the island part of the lead frame, the present invention can absorb the stress of distortion that occurs when a semiconductor pellet is fixed to the island part and resin molded. This has the effect of reducing wire breakage and cracks occurring in the molding resin, resulting in a lead frame that can manufacture semiconductor devices with improved reliability.
【図面の簡単な説明】
第1図は本発明の一実施例のアイランド部の平面図、第
2図は従来のリードフレームのアイランド部の平面図で
ある。
1・・・・・・吊シビーン、2・・・・・・アイランド
部、3・・・・・・スリット。壬遇ミ;
−一BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view of an island portion according to an embodiment of the present invention, and FIG. 2 is a plan view of an island portion of a conventional lead frame. 1...Hanging shebeen, 2...Island part, 3...Slit. -1
Claims (1)
徴とするリードフレーム。A lead frame characterized by having an island portion provided with a slit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27970585A JPS62137859A (en) | 1985-12-11 | 1985-12-11 | Lead frame |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27970585A JPS62137859A (en) | 1985-12-11 | 1985-12-11 | Lead frame |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62137859A true JPS62137859A (en) | 1987-06-20 |
Family
ID=17614727
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP27970585A Pending JPS62137859A (en) | 1985-12-11 | 1985-12-11 | Lead frame |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62137859A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02125651A (en) * | 1988-11-04 | 1990-05-14 | Nec Corp | Lead frame |
US5021864A (en) * | 1989-09-05 | 1991-06-04 | Micron Technology, Inc. | Die-mounting paddle for mechanical stress reduction in plastic IC packages |
US5075254A (en) * | 1988-04-26 | 1991-12-24 | National Semiconductor Corporation | Method and apparatus for reducing die stress |
US5708294A (en) * | 1995-02-28 | 1998-01-13 | Nec Corporation | Lead frame having oblique slits on a die pad |
-
1985
- 1985-12-11 JP JP27970585A patent/JPS62137859A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5075254A (en) * | 1988-04-26 | 1991-12-24 | National Semiconductor Corporation | Method and apparatus for reducing die stress |
JPH02125651A (en) * | 1988-11-04 | 1990-05-14 | Nec Corp | Lead frame |
US5021864A (en) * | 1989-09-05 | 1991-06-04 | Micron Technology, Inc. | Die-mounting paddle for mechanical stress reduction in plastic IC packages |
US5708294A (en) * | 1995-02-28 | 1998-01-13 | Nec Corporation | Lead frame having oblique slits on a die pad |
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