JPS62136922A - Output circuit for ttl integrated circuit - Google Patents
Output circuit for ttl integrated circuitInfo
- Publication number
- JPS62136922A JPS62136922A JP60278312A JP27831285A JPS62136922A JP S62136922 A JPS62136922 A JP S62136922A JP 60278312 A JP60278312 A JP 60278312A JP 27831285 A JP27831285 A JP 27831285A JP S62136922 A JPS62136922 A JP S62136922A
- Authority
- JP
- Japan
- Prior art keywords
- load
- circuit
- integrated circuit
- output
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
ＴＴＬ集積回路の出力回路において、負荷電流の増大に
よる出力電圧の低下を、外部の電源回路からの電流供給
により防止したものである。DETAILED DESCRIPTION OF THE INVENTION [Summary] In an output circuit of a TTL integrated circuit, a drop in output voltage due to an increase in load current is prevented by supplying current from an external power supply circuit.
本発明はＴＴＬ集積回路の出力回路の改良に関する。 The present invention relates to improvements in output circuits for TTL integrated circuits.
一般に、負荷増大に伴い出力回路から大電流を取り出す
ときは出力回路での電圧降下により負荷供給電圧が低下
するので、電圧降下を減少させる改善が望まれている。Generally, when a large current is extracted from an output circuit as the load increases, the load supply voltage decreases due to a voltage drop in the output circuit, so improvements that reduce the voltage drop are desired.
重負荷にて出力電圧低下を防ぐ従来のＴＴＬ集積回路の
出力回路は、ＴＴＬ集禎回路中に設けたバッファ回路を
使用している。The output circuit of a conventional TTL integrated circuit that prevents output voltage drop under heavy loads uses a buffer circuit provided in the TTL integrated circuit.
バッファ回路には、第２図ａに示す様なＴＴＬ出力回路
にバッファ増幅器３を追加するか、第２図すに示す様な
ファンアウト分割回路等が使用されている。For the buffer circuit, a buffer amplifier 3 is added to the TTL output circuit as shown in FIG. 2A, or a fan-out dividing circuit as shown in FIG. 2S is used.
上記の従来のＴＴＬ集積回路の出力回路は実使用時にお
いて、必ずしも負荷に対する最適なものではない。また
予め複雑なバッファ回路を築積回路中に設けておくこと
も有利なことではない。The output circuit of the conventional TTL integrated circuit described above is not necessarily optimal for the load in actual use. Furthermore, it is not advantageous to provide a complicated buffer circuit in advance in the built-up circuit.
ＴＴＬ集積回路の出力回路がスイッチングトランジスタ
である場合、電源から抵抗を介し供給される電流のオン
・オフをトランジスタにより行い負荷電圧をオフ・オン
する。トランジスタのオフ時負荷へは抵抗を介し電流が
供給されるから、重負荷時抵抗による電圧降下を生じ、
負荷電圧が低下する。この場合、ＴＴＬ集積回路中の抵
抗に大電流を流しても電圧降下の少ない様な抵抗を設け
ることは実現が困難である。When the output circuit of the TTL integrated circuit is a switching transistor, the transistor turns on and off a current supplied from a power source via a resistor, thereby turning a load voltage on and off. When the transistor is off, current is supplied to the load through the resistor, so when the load is heavy, a voltage drop occurs due to the resistor.
Load voltage decreases. In this case, it is difficult to provide a resistor in the TTL integrated circuit that causes a small voltage drop even when a large current is passed through the resistor.
上記の問題点は、
負荷回路に対するノＴＴＬ集積回路の出力トランジスタ
のコレクタ電極へ、付加的な外部の抵抗素子を介し電流
を供給するようにした構成をもつ、本発明によるＴＴＬ
集積回路の出力回路によって解決される。The above problem can be solved by the TTL integrated circuit according to the present invention, which has a configuration in which current is supplied to the collector electrode of the output transistor of the TTL integrated circuit for the load circuit through an additional external resistance element.
Solved by integrated circuit output circuit.
本発明のＴＴＬ集積回路の出力回路は外部に付加抵抗を
備えることにより、スイッチングトランジスタのオフ時
電源から負荷に電流を供給する集積回路中に設けた抵抗
と共に、外部に設けた付加抵抗によっても負荷に対して
電源から電流を供給することにより、負荷電圧の低下を
防止する。The output circuit of the TTL integrated circuit of the present invention is equipped with an external additional resistor, so that when the switching transistor is off, the output circuit supplies a current from the power supply to the load. By supplying current from the power supply to the terminal, a drop in load voltage is prevented.
〔実施例〕 図示実施例に従い本発明の詳細な説明する。〔Example〕 The present invention will be described in detail according to the illustrated embodiments.
第１図は本発明のＴＴＬ集禎回路の出力回路の一実施例
を示す回路図である。FIG. 1 is a circuit diagram showing an embodiment of the output circuit of the TTL integrated circuit of the present invention.
図において、１はＴＴＬ集禎回路、１１はスイッチング
トランジスタ、１２はＩＣ回路中に設けた抵抗、２は負
荷抵抗、４は本発明の負荷電流供給のための外部の付加
抵抗、ＶｃｃとＶｏは電源電圧である。In the figure, 1 is a TTL integrated circuit, 11 is a switching transistor, 12 is a resistor provided in the IC circuit, 2 is a load resistor, 4 is an external additional resistor for supplying the load current of the present invention, and Vcc and Vo are This is the power supply voltage.
ここで、Ｖｃｃ Ｓ Ｖｏに選ぶ。Here, select Vcc S Vo.
ＴＴＬ集積集積回路比力回路のスイッチングトランジス
タ１１がオンになると、負荷２へ地気電圧Ｇが供給され
る。When the switching transistor 11 of the TTL integrated circuit specific power circuit is turned on, the earth voltage G is supplied to the load 2.
ＴＴＬ集積回路１の出力回路のスイッチングトランジス
タ１１がオフになるとＩＣ回路中に設けた抵抗１２を介
し電源Ｖｃｃから負荷２へ電源電圧が供給される。この
時、負荷が重いと抵抗１２における電圧降下が大となり
、負荷電圧が低下するが、付加抵抗４は電源ｖＯから負
荷２へ負荷電流を供給することにより負荷電圧の低下を
防止する。When the switching transistor 11 of the output circuit of the TTL integrated circuit 1 is turned off, a power supply voltage is supplied from the power supply Vcc to the load 2 via the resistor 12 provided in the IC circuit. At this time, if the load is heavy, the voltage drop across the resistor 12 becomes large and the load voltage decreases, but the additional resistor 4 prevents the load voltage from decreasing by supplying the load current from the power source vO to the load 2.
付加抵抗はＩＣ回路中に設ける必要がなく、使用負荷量
に応じ必要な抵抗値を設定することが出来る。There is no need to provide an additional resistor in the IC circuit, and the required resistance value can be set according to the amount of load used.
本発明によれば、重負荷時におけるＴＴＬ集積回路の出
力スイッチングトランジスタのオフ時の負荷電圧の低下
を簡単な付加抵抗回路により防止出来るので、その作用
効果は極めて大きい。According to the present invention, a drop in the load voltage when the output switching transistor of the TTL integrated circuit is turned off during a heavy load can be prevented by a simple additional resistance circuit, so the effect is extremely large.
第１図は本発明のＴＴＬ築梼回路の出方回路の一実施例
を示す回路図、
第２図は従来のＴＴＬ集積回路の出方回路図を示す。
図において、
１はＴＴＬ集禎回路、
１１はスイッチングトランジスタ、
１２は抵抗、
２は負荷膚拭、
３はバッファ回路、
４は付加抵抗、
Ｖｃｃ 、 Ｖｏは電源電圧である。FIG. 1 is a circuit diagram showing an embodiment of the output circuit of a TTL construction circuit according to the present invention, and FIG. 2 is a circuit diagram showing an output circuit of a conventional TTL integrated circuit. In the figure, 1 is a TTL integrated circuit, 11 is a switching transistor, 12 is a resistor, 2 is a load wiper, 3 is a buffer circuit, 4 is an additional resistor, and Vcc and Vo are power supply voltages.
Claims (1)
（１）の出力トランジスタ（１１）のコレクタ電極へ、
該集積回路外部の付加抵抗（４）を介し、電源電圧を供
給可能に構成してなることを特徴とするＴＴＬ集積回路
の出力回路。to the collector electrode of the output transistor (11) of the TTL integrated circuit (1) having an output terminal for the load circuit (2);
An output circuit for a TTL integrated circuit, characterized in that it is configured to be able to supply a power supply voltage via an additional resistor (4) external to the integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60278312A JPS62136922A (en) | 1985-12-11 | 1985-12-11 | Output circuit for ttl integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60278312A JPS62136922A (en) | 1985-12-11 | 1985-12-11 | Output circuit for ttl integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62136922A true JPS62136922A (en) | 1987-06-19 |
Family
ID=17595582
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60278312A Pending JPS62136922A (en) | 1985-12-11 | 1985-12-11 | Output circuit for ttl integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62136922A (en) |
-
1985
- 1985-12-11 JP JP60278312A patent/JPS62136922A/en active Pending
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