JPS62136882A - High-speed field effect semiconductor device - Google Patents
High-speed field effect semiconductor deviceInfo
- Publication number
- JPS62136882A JPS62136882A JP27703685A JP27703685A JPS62136882A JP S62136882 A JPS62136882 A JP S62136882A JP 27703685 A JP27703685 A JP 27703685A JP 27703685 A JP27703685 A JP 27703685A JP S62136882 A JPS62136882 A JP S62136882A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gaas
- superlattice
- layers
- well
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 230000005669 field effect Effects 0.000 title claims abstract description 11
- 239000012535 impurity Substances 0.000 claims abstract description 15
- 230000004888 barrier function Effects 0.000 claims abstract description 13
- 239000012159 carrier gas Substances 0.000 claims abstract description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 19
- 230000005533 two-dimensional electron gas Effects 0.000 abstract description 11
- 230000012010 growth Effects 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 5
- 230000007423 decrease Effects 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 230000002411 adverse Effects 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
- H01L29/365—Planar doping, e.g. atomic-plane doping, delta-doping
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
本発明は、高速電界効果半導体装置に於いて、アン・ド
ープ半導体チャネル層を第１の超格子と第２の超格子と
で挟み、それ等超格子内のウェル層にのみ高濃度の不純
物をドーピングし、それ以外のゲート電極直下に於ける
半導体層はアン・ドープとすることに依り、２次元キャ
リヤ・ガス層のキャリヤ濃度を増加させ、半導体層に於
ける深い不純物準位の影響を回避し、ゲート耐圧を向上
させ得るようにしたものである。[Detailed Description of the Invention] [Summary] The present invention provides a high-speed field effect semiconductor device in which an undoped semiconductor channel layer is sandwiched between a first superlattice and a second superlattice. By doping only the well layer with a high concentration of impurity and leaving the other semiconductor layer directly under the gate electrode undoped, the carrier concentration in the two-dimensional carrier gas layer is increased and the semiconductor layer is This is to avoid the influence of deep impurity levels in the semiconductor device and to improve the gate breakdown voltage.
本発明は、ヘテロ界面に生成される２次元電子ガス層を
チャネルとして利用する高速電界効果半導体装置の改良
に関する。The present invention relates to improvements in high-speed field effect semiconductor devices that utilize a two-dimensional electron gas layer generated at a heterointerface as a channel.
第３図は一般的なこの種の高速電界効果半導体装置のゲ
ート電極直下に於けるエネルギ・バンド・ダイヤグラム
を表している。FIG. 3 shows an energy band diagram immediately below the gate electrode of a general high-speed field effect semiconductor device of this type.
図に於いて、ｌは金属ゲート電極、２はｎ型ＡβＧａＡ
ｓ電子供給層、３はアン・ドープＧａＡｓチャネル層、
４は２次元電子ガス層、Ｆ、ｃは伝導帯の下端、ＥＦは
フェルミ・レベル、Ｅｖは価電子帯の上端をそれぞれ示
している。In the figure, l is a metal gate electrode, 2 is an n-type AβGaA
s electron supply layer; 3 is an undoped GaAs channel layer;
4 is a two-dimensional electron gas layer, F and c are the lower end of the conduction band, EF is the Fermi level, and Ev is the upper end of the valence band.
この半導体装置では、２次元電子ガス層４をチャネルと
して用いている為、走行する電子がクーロン散乱を受け
ることがな（、従って、極めて高速で動作することが可
能である。In this semiconductor device, since the two-dimensional electron gas layer 4 is used as a channel, traveling electrons are not subjected to Coulomb scattering (therefore, it is possible to operate at extremely high speed).
ところで、この種の半導体装置に於いて、大きな電流を
取り出す為には、２次元電子ガス層４に於ける電子濃度
を高くすることが必要であるが、第３図に見られるシン
グル・ペテロ接合構造では限界がある。By the way, in order to extract a large current from this type of semiconductor device, it is necessary to increase the electron concentration in the two-dimensional electron gas layer 4. There are limits to the structure.
第４図は改良された高速電界効果半導体装置のゲート電
極直下に於けるエネルギ・バンド・ダイヤグラムを表し
、第３図に於いて用いた記号と同記号は同部分を示すか
或いは同じ意味を持つものとする。Figure 4 shows an energy band diagram directly under the gate electrode of the improved high-speed field effect semiconductor device, and the same symbols as those used in Figure 3 indicate the same parts or have the same meaning. shall be taken as a thing.
この半導体装置では、アン・ドープＧａＡｓチャネル層
３をｎ型ＡβＧａＡｓ電子供給層２Ａ及び２Ｂで挟む構
成にし、その両方の電子供給層２Ａ及び２Ｂから電子を
供給して２次元電子ガス層４に於ける電子濃度を高める
ようにしている。In this semiconductor device, an undoped GaAs channel layer 3 is sandwiched between n-type AβGaAs electron supply layers 2A and 2B, and electrons are supplied from both electron supply layers 2A and 2B to form a two-dimensional electron gas layer 4. The electron concentration is increased.
第４図について説明した従来例に於いては、確かに２次
元電子ガス層４に於ける電子ガス濃度を向上させる効果
はあるが、このような構造にすると、Ａ／ＧａＡｓ中の
深い不純物準位が半導体装置の特性に悪影響を与え、ま
た、チャネルとショットキ障壁界面までの距離が非常に
小さくなることからゲート耐圧が低下する旨の欠点があ
る。In the conventional example explained with reference to FIG. 4, it is true that the electron gas concentration in the two-dimensional electron gas layer 4 is improved, but with such a structure, the deep impurity level in A/GaAs is reduced. This has disadvantages in that the gate voltage has an adverse effect on the characteristics of the semiconductor device, and the distance between the channel and the Schottky barrier interface becomes very small, resulting in a reduction in gate breakdown voltage.
本発明は、２次元キャリヤ・ガス層に於けるキャリヤ濃
度を高め、半導体の深い不純物準位の悪影響を解消し、
ゲート耐圧の低下がない高速電界効果半導体装置を提供
する。The present invention increases the carrier concentration in the two-dimensional carrier gas layer, eliminates the adverse effects of deep impurity levels in semiconductors, and
Provided is a high-speed field effect semiconductor device with no reduction in gate breakdown voltage.
本発明に依る高速電界効果半導体装置では、２次元キャ
リヤ・ガス層（例えば２次元電子ガス層２１が生成され
るアン・ドープ半導体チャネル層（例えばｉ型ＧａＡＳ
チャネル層１４）と、前記チャネル層の下側に接する第
１の超格子（例えば第１の超格子１３）及び上側に接す
る第２の超格子（例えば第２の超格子１５）と、前記第
１の超格子に接するアン・ドープ半導体層（例えばｉ型
Ａｌｏ、ｚ Ｇａ６．マＡｓ層１２）及び前記第２の超
格子に接するアン・ドープ半導体層（例えばｉ型Ａ１ｏ
、ｚ Ｇａｏ、７Ａｓ層１６）と、前記第２の超格子に
接するアン・ドープ半導体層にコンタクトするゲート電
極（例えばゲート電極２０）とを備えてなり、前記第１
及び第２の各超格子は高濃度に不純物がドーピングされ
且つエネルギ・サブ・ハンドが生成される得るウェル層
（例えばｎ型ＧａＡｓウェル層１３Ｂ及び１５Ｂ）と該
ウェル層を挟み且つ前記チャネル層よりキャリヤ親和力
が小でエネルギ・バンド・ギャップが大であるバリヤ層
（例えばｉ型ＡｌＡｓバリヤ層１３Ａ及び１５Ａ）とか
らなっていることを特徴とする構成を採っている。In the fast field effect semiconductor device according to the present invention, a two-dimensional carrier gas layer (e.g. an undoped semiconductor channel layer (e.g. i-type GaAS) in which a two-dimensional electron gas layer 21 is generated)
a first superlattice (for example, first superlattice 13) in contact with the lower side of the channel layer, a second superlattice (for example, second superlattice 15) in contact with the upper side of the channel layer; an undoped semiconductor layer in contact with the first superlattice (e.g., i-type Alo, zGa6.Ma layer 12) and an undoped semiconductor layer in contact with the second superlattice (e.g., i-type A1o).
, z Gao, 7As layer 16), and a gate electrode (e.g., gate electrode 20) in contact with the undoped semiconductor layer in contact with the second superlattice;
Each of the second superlattices is sandwiched between a well layer (for example, n-type GaAs well layers 13B and 15B) doped with impurities at a high concentration and in which energy sub-hands can be generated, and is further away from the channel layer. The structure is characterized by comprising a barrier layer (for example, i-type AlAs barrier layers 13A and 15A) having a small carrier affinity and a large energy band gap.
前記構成に依り、２次元キャリヤ・ガス層に於けるキャ
リヤ濃度は高められ、また、半導体の深い不純物単位の
悪影響は解消され、更にまた、ゲート耐圧の低下を防止
することが可能となる。With the above structure, the carrier concentration in the two-dimensional carrier gas layer is increased, the adverse effects of deep impurity units in the semiconductor are eliminated, and furthermore, it is possible to prevent the gate breakdown voltage from decreasing.
第１図は本発明一実施例の要部切断側面図を表している
。FIG. 1 shows a cutaway side view of essential parts of an embodiment of the present invention.
図に於いて、１１は半絶縁性であるＧａＡｓ基斗反、１
２はｉ型Ａ（ｌｏ、ｘ Ｇａｏ、７Ａｓ層、１３は第１
の超格子、１４はｉ型ＧａＡｓチャネル層、１５は第２
の超格子、１６はｉ型Ａｌ−６，３Ｇａｐ、？、６．ｓ
ｊｉ、１７はｉ （或いはｎ）型ＧａＡｓキャップ層、
１８はソース電極、１９はドレイン電極、２０はゲート
電極、２１は２次元電子ガス層をそれぞれ示している。In the figure, 11 is a semi-insulating GaAs substrate;
2 is i-type A (lo, x Gao, 7As layer, 13 is the first
14 is an i-type GaAs channel layer, 15 is a second superlattice.
superlattice, 16 is i-type Al-6, 3Gap, ? ,6. s
ji, 17 is an i (or n) type GaAs cap layer,
18 is a source electrode, 19 is a drain electrode, 20 is a gate electrode, and 21 is a two-dimensional electron gas layer.
尚、第１及び第２の超格子層１３及び１５の内容は第２
図にて説明される。Note that the contents of the first and second superlattice layers 13 and 15 are as follows.
This is explained in the figure.
第２図は第１図に関して説明した実施例に於けるゲート
電極直下のエネルギ・バンド・ダイヤグラムを表し、第
１図に於いて用いた記号と同記号は同部分を表すか或い
は同じ意味を持つものとする。FIG. 2 shows an energy band diagram directly under the gate electrode in the embodiment explained with reference to FIG. 1, and the same symbols as those used in FIG. 1 represent the same parts or have the same meaning. shall be taken as a thing.
図に於いて、１３Ａ及び１５Ａはｉ型Ａｊｌ！Ａｓバリ
ヤ層、１３Ｂ及び１５Ｂはｎ型ＧａＡｓウェル層を示し
、バリヤ層１３Ａ及びウェル層１３Ｂで第１の超格子１
３が、そして、バリヤ層１５Ａ及びウェル層１５Ｂで第
２の超格子が構成されている。In the figure, 13A and 15A are i type Ajl! The As barrier layers 13B and 15B represent n-type GaAs well layers, and the barrier layer 13A and the well layer 13B form the first superlattice 1.
3, and a second superlattice is constituted by the barrier layer 15A and the well layer 15B.
第１図及び第２図に見られる実施例に於ける各半導体層
及び電極に関する諸データを例示すると次の通りである
。Examples of data regarding each semiconductor layer and electrode in the embodiment shown in FIGS. 1 and 2 are as follows.
（１） ｉ型Ａ１１ｏ、３Ｇａ（＋、７ Ａ ｓ層１
２について厚さ：１５００（人〕
（２）バリヤ層１３Ａ及び１５Ａについて厚さ：２０
〔人〕
（３） ウェル層１３Ｂ及び１５Ｂについて厚さ：６
０ 〔人〕
不純物：５ｉ
Ｓｔのドナー濃度：シート濃度にしてＩＸ１ｌＸ１０１
２（”）
（３） チャネル層１４について
厚さ：１００Ｃ人〕
（４）ｉ型Ａｌｏ、＋ Ｇａｏ、、Ａｓ層１６について
厚さ：３００Ｃ３０
０Ｃ） ソース電極１８及びドレイン電極１９につい
て
材料：Ａｕ−Ｇｅ／Ａｕ
厚さ：２００（人）／２８００（人〕
（６） ゲート電極２０について
材料：Ａ１
厚さ：４０００ （人〕
本実施例に於けるウェル層１３Ｂ及び１５Ｂに不純物を
導入する場合、所謂、プレーナ・ドーピング法を適用す
ると高濃度化することが極めて容易である。即ち、ｎ型
Ｇ ａ Ａ ｓウェル層１３Ｂ或いは１５Ｂを分子線エ
ピタキシャル成長（ｍ ｏ １ｅｃｕｌａｒ ｂｅａ
ｍ ｅｐｉｔａｘｙ：ＭＢＥ）法を適用して成長させ
るに際し、先ず、ＧａＡｓ層の成長を行い、次いで、Ｇ
ａの分子線を遮断した状態でＳｉの分子線のみを放射す
ると、ＧａＡｓは成長されず、極めて薄＜Ｓｉのみが成
長するので、そのＧａＡｓの成長とＳｉの成長とを適宜
回数繰り返すと、ＧａＡｓ層中にＳｉを２次元的にドー
ピングすることができ、通常の技法では得られない高濃
度にすることができる。(1) i-type A11o, 3Ga(+, 7A s layer 1
Thickness for 2: 1500 (person) (2) Thickness for barrier layer 13A and 15A: 20
[People] (3) Thickness for well layers 13B and 15B: 6
0 [Human] Impurity: 5i St donor concentration: IX11X101 as sheet concentration
2('') (3) Thickness of channel layer 14: 100C] (4) Thickness of i-type Alo, + Gao, As layer 16: 300C300C) Material of source electrode 18 and drain electrode 19: Au- Ge/Au Thickness: 200 (people)/2800 (people) (6) Regarding the gate electrode 20 Material: A1 Thickness: 4000 (people) When introducing impurities into the well layers 13B and 15B in this example, It is extremely easy to increase the concentration by applying the so-called planar doping method.In other words, the n-type GaAs well layer 13B or 15B is grown by molecular beam epitaxial growth (mol bea epitaxial growth).
When growing a GaAs layer by applying the m epitaxy (MBE) method, first a GaAs layer is grown, and then a GaAs layer is grown.
If only the molecular beam of Si is emitted while the molecular beam of It is possible to dope Si into the layer two-dimensionally, resulting in high concentrations that cannot be obtained using conventional techniques.
さて、本実施例では、バリヤ層１５Ａに挟まれたウェル
層１５Ｂ、バリヤ層１３Ａに挟まれたウェル層１３Ｂに
はエネルギ・サブ・バンドが生成され、それに依り、電
子のエネルギは高められて容易にチャネル層１４に注入
され２次元電子ガス層２１に於ける電子濃度は向上され
る。Now, in this embodiment, energy sub-bands are generated in the well layer 15B sandwiched between the barrier layers 15A and the well layer 13B sandwiched between the barrier layers 13A. Injected into the channel layer 14, the electron concentration in the two-dimensional electron gas layer 21 is improved.
また、ＧａＡｓ−Ａ／Ａｓ系の場合に於いては、本発明
に依る高速電界効果半導体装置の半導体層には、深い不
純物単位を有するｎ型ＡｌＧａＡｓを使用していない為
、低温度（例えば液体窒素温度）で動作させた場合でも
、室温の場合と比較してしきい値電圧の変化はない。Furthermore, in the case of the GaAs-A/As system, the semiconductor layer of the high-speed field effect semiconductor device according to the present invention does not use n-type AlGaAs having deep impurity units, so the temperature is low (for example, liquid There is no change in threshold voltage compared to room temperature even when the device is operated at room temperature (nitrogen temperature).
更にまた、ゲート電極２０とチャネル層１４との間には
ｉ型Ａｎｏ、ｚ Ｇａｏ、７Ａｓｌｉｌｌ ６が存在し
ているので、チャネル層１４に多量の電子が存在してい
るにも拘わらず、ゲート耐圧が低下することは絶無であ
る。尚、前記Ａ６ＧａＡＳに於けるＡ１のモル濃度はゲ
ート耐圧向上の為、更に大きくしても良い。Furthermore, since i-type Ano, z Gao, and 7 Asrill 6 are present between the gate electrode 20 and the channel layer 14, the gate breakdown voltage is low even though a large amount of electrons are present in the channel layer 14. There is no way that this will decrease. Note that the molar concentration of A1 in the A6GaAS may be further increased in order to improve the gate breakdown voltage.
本実施例に於ける閾値電圧Ｖｔｈは、Ａ７！ゲート電極
２０とコンタクトするｉ型Ａ’Ｑ、３Ｇａ０．７Ａｓ層
１６の厚さに依存し、例えば３００ （人〕である場
合、約０．１ （Ｖ）のエンハンスメント・モードとな
り、そして、ゲート長Ｌ９が１ 〔μｍ〕である場合の
相互コンダクタンスｇ、は室温で３５０（ｍｓ）が得ら
れた。The threshold voltage Vth in this embodiment is A7! Depending on the thickness of the i-type A'Q, 3Ga0.7As layer 16 in contact with the gate electrode 20, for example, if it is 300 (people), it will be an enhancement mode of about 0.1 (V), and the gate length will be A mutual conductance g of 350 (ms) was obtained at room temperature when L9 was 1 [μm].
また、ゲート耐圧は、通常のダブル・ヘテロ接合構造、
即ち、第４図に見られる従来例のものに於ける６〔■〕
に対し、本発明のものに於いては１５（Ｖ）と著しい向
上が見られ、更にまた、室温と低温（液体窒素温度）に
於けるしきい値電圧の変動量は約１００１００（であっ
て、従来例の２００〜４００（ｍＶ）と比較すると非常
に小さい。In addition, the gate breakdown voltage is the same as the normal double heterojunction structure.
That is, 6 [■] in the conventional example shown in FIG.
On the other hand, the device of the present invention showed a remarkable improvement of 15 (V), and furthermore, the amount of variation in threshold voltage at room temperature and low temperature (liquid nitrogen temperature) was approximately 100,100 (V). , which is very small compared to 200 to 400 (mV) in the conventional example.
本発明に依る高速電界効果半導体装置では、アン・ドー
プ半導体チャネル層を第１の超格子と第２の超格子とで
挟み、それ等超格子内のウェル層にのみ高濃度の不純物
をドーピングし、それ以外のゲート電極直下に於ける半
導体層はアン・ドープとすることに依り、２次元キャリ
ヤ・ガス層に於けるキャリヤ濃度を増加させ、また、半
導体層に於ける深い不純物単位の悪影響を解消し、更に
また、ゲート耐圧の低下を防止することを可能にしてい
る。In the high speed field effect semiconductor device according to the present invention, an undoped semiconductor channel layer is sandwiched between a first superlattice and a second superlattice, and only the well layer in the superlattice is doped with a high concentration of impurity. By making the other semiconductor layers directly under the gate electrode undoped, the carrier concentration in the two-dimensional carrier gas layer is increased and the adverse effects of deep impurity units in the semiconductor layer are reduced. In addition, it is possible to prevent the gate breakdown voltage from decreasing.
第１図は本発明一実施例の要部切断側面図、第２図は第
１図に見られる実施例のエネルギ・バンド・ダイヤグラ
ム、第３図及び第４図は従来例のエネルギ・バンド・ダ
イヤグラムを表している。
図に於いて、ｌｌは半絶縁性であるＧａＡｓ基板、１２
はｉ型Ａ１６．３ Ｇａ、、、 Ａｓ層、１３は第１の
超格子、１４はｉ型ＧａＡｓチャネル層、１５は第２の
超格子、１６はｉ型Ａｆｆｉ６．３ Ｇａｏ、。
Ａｓ層、１７はｉ （或いはｎ）型ＧａＡｓキャップ層
、１８はソース電極、１９はドレイン電極、２０はゲー
ト電極、２１は２次元電子ガス層、１３Ａ及び１５Ａは
ｉ型ＡｆｆｉＡｓバリヤ層、１３Ｂ及び１５Ｂはｎ型Ｇ
ａＡＳウェル層をそれぞれ示している。
特許出願人 冨士通株式会社
代理人弁理士 相 谷 昭 司
代理人弁理士 渡 邊 弘 一
実施例の要部切断側面図
第１図
実施例のエネルギ・バント・ダイヤグラム第２図
従来例のエネルギ・パン８・ダイヤグラム第３図FIG. 1 is a cutaway side view of essential parts of an embodiment of the present invention, FIG. 2 is an energy band diagram of the embodiment shown in FIG. 1, and FIGS. 3 and 4 are energy band diagrams of the conventional example. represents a diagram. In the figure, ll is a semi-insulating GaAs substrate, 12
is an i-type A16.3 Ga,..., As layer, 13 is a first superlattice, 14 is an i-type GaAs channel layer, 15 is a second superlattice, and 16 is an i-type Affi6.3 Gao. 17 is an i (or n) type GaAs cap layer, 18 is a source electrode, 19 is a drain electrode, 20 is a gate electrode, 21 is a two-dimensional electron gas layer, 13A and 15A are i-type AffiAs barrier layers, 13B and 15B is n-type G
Each aAS well layer is shown. Patent Applicant: Fujitsu Co., Ltd. Representative Patent Attorney: Akira Aitani Representative Patent Attorney: Hiroshi Watanabe Pan 8 Diagram Figure 3
Claims (1)
導体チャネル層と、 前記チャネル層の下側に接する第１の超格子及び上側と
接する第２の超格子と、 前記第１の超格子に接するアン・ドープ半導体層及び前
記第２の超格子に接するアン・ドープ半導体層と、 前記第２の超格子に接するアン・ドープ半導体層にコン
タクトするゲート電極と を備えてなり、 前記第１及び第２の各超格子は高濃度に不純物がドーピ
ングされ且つエネルギ・サブ・バンドが生成され得るウ
ェル層と該ウェル層を挟み且つ前記チャネル層よりキャ
リヤ親和力が小でエネルギ・バンド・ギャップが大であ
るバリヤ層とからなっていること を特徴とする高速電界効果半導体装置。Claims: an undoped semiconductor channel layer in which a two-dimensional carrier gas layer is produced; a first superlattice in contact with the lower side of the channel layer and a second superlattice in contact with the upper side; an undoped semiconductor layer in contact with the first superlattice, an undoped semiconductor layer in contact with the second superlattice, and a gate electrode in contact with the undoped semiconductor layer in contact with the second superlattice. , each of the first and second superlattices is sandwiched between a well layer doped with impurities at a high concentration and in which an energy sub-band can be generated, and has a lower carrier affinity than the channel layer and an energy band. - A high-speed field effect semiconductor device characterized by comprising a barrier layer with a large gap.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27703685A JPS62136882A (en) | 1985-12-11 | 1985-12-11 | High-speed field effect semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27703685A JPS62136882A (en) | 1985-12-11 | 1985-12-11 | High-speed field effect semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62136882A true JPS62136882A (en) | 1987-06-19 |
Family
ID=17577883
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27703685A Pending JPS62136882A (en) | 1985-12-11 | 1985-12-11 | High-speed field effect semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62136882A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0794758A (en) * | 1991-09-12 | 1995-04-07 | Pohang Iron & Steel Co Ltd | Manufacture of delta-doped quantum well type field-effect transistor |
| EP0841704A1 (en) * | 1996-11-07 | 1998-05-13 | Paul-Drude-Institut für Festkörperelektronik | Semiconductor transistor device and method of manufacturing the same |
-
1985
- 1985-12-11 JP JP27703685A patent/JPS62136882A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0794758A (en) * | 1991-09-12 | 1995-04-07 | Pohang Iron & Steel Co Ltd | Manufacture of delta-doped quantum well type field-effect transistor |
| EP0841704A1 (en) * | 1996-11-07 | 1998-05-13 | Paul-Drude-Institut für Festkörperelektronik | Semiconductor transistor device and method of manufacturing the same |
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