JPS62133775A - Mixed crystal semiconductor - Google Patents
Mixed crystal semiconductorInfo
- Publication number
- JPS62133775A JPS62133775A JP60274243A JP27424385A JPS62133775A JP S62133775 A JPS62133775 A JP S62133775A JP 60274243 A JP60274243 A JP 60274243A JP 27424385 A JP27424385 A JP 27424385A JP S62133775 A JPS62133775 A JP S62133775A
- Authority
- JP
- Japan
- Prior art keywords
- indium
- mixed crystal
- crystal semiconductor
- aluminum
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Light Receiving Elements (AREA)
- Semiconductor Lasers (AREA)
- Led Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
（技術分野）
本発明は発光受光素子あるいはトランジスタなどの電気
素子および、これらを集積した集積回路などに応用され
る混晶半導体に関する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a mixed crystal semiconductor applied to electric elements such as light-emitting light-receiving elements or transistors, and integrated circuits in which these elements are integrated.
（従来技術とその問題点）
アルミニウム−インジウム−ひ素混晶半導体層を用いる
ことにより長距離無中継光フアイバ通信に適した半導体
レーザ、高速なだれ増倍フォトダイオード、高相互コン
ダクタンスを持つ電界効果トランジスタなどの半導体装
置を実現することが可能であり、従来よりこれら半導体
装置について研究開発が進められている。また、これら
半導体装置を集積化することをでより機能面および性能
面において従来のものを上回る集積回路が実現できるも
のと考えられている。前記半導体装置を作製あるいは集
積化する際にはアルミニウム−インジウム−ひ素混晶半
導体層の任意の領域を電気的に絶縁化させる必要がある
。しかし従来技術ではアルミニウム−インジウム−ひ素
混晶半導体層の任意の領域を絶縁化する方法は知られて
おらず、作製あるいは集積化の際の課題となっていた。(Prior art and its problems) Semiconductor lasers suitable for long-distance non-repeater optical fiber communications by using aluminum-indium-arsenic mixed crystal semiconductor layers, high-speed avalanche multiplication photodiodes, field-effect transistors with high mutual conductance, etc. It is possible to realize such semiconductor devices, and research and development of these semiconductor devices has been progressing for some time. It is also believed that by integrating these semiconductor devices, it will be possible to realize integrated circuits that are superior to conventional circuits in terms of functionality and performance. When manufacturing or integrating the semiconductor device, it is necessary to electrically insulate any region of the aluminum-indium-arsenic mixed crystal semiconductor layer. However, in the prior art, there is no known method for insulating any region of an aluminum-indium-arsenic mixed crystal semiconductor layer, which has been a problem during fabrication or integration.
（問題点を解決するための手段）
本発明では上記問題点を解決するためにイオン注入によ
りアルミニウム−インジウム−ひ素混晶半導体を絶縁化
するとしたものである。(Means for Solving the Problems) In order to solve the above problems, the present invention insulates an aluminum-indium-arsenic mixed crystal semiconductor by ion implantation.
（作用および実施例）
本発明の作用を発明者が行なった実験すなわち実施例に
基づいて説明する。(Operation and Examples) The operation of the present invention will be explained based on experiments conducted by the inventor, that is, examples.
第１図は、半絶縁性インジウム−りん基板上に分子線エ
ビクキシャル成長法によって作製したアルミニウム−イ
ンジウム−ひ素混晶半導体の電気抵抗のイオン注入によ
る変化を示したものである。FIG. 1 shows the change in electrical resistance of an aluminum-indium-arsenic mixed crystal semiconductor fabricated on a semi-insulating indium-phosphorus substrate by the molecular beam eviaxial growth method due to ion implantation.
ここで、アルミニウム−インジウム−ひ素混晶半導体層
には約１０１９ｃｒｎ−３の電子濃度となるようにｎ型
不純物であるシリコンが添加きれている。注入するイオ
ン種としては一価のほう素イオンを用いた。第１図（ａ
）はほう素イオンを１．Ｘ１０］３ｍ−２注入した際の
アルミニウム、インジウム−ひ素混晶半導体層の抵抗率
の加速エネルギー依存性を示したものである。加速エネ
ルギーが１００ ＫｅＶを越えるとアルミニウム−イン
ジウム−ひ素混晶半導体層は急激に高抵抗化し、ＩＳ
ＯＫｅＶ以上で抵抗率は］０４Ω、（７）以上の値とな
っている。ここで、アルミニウム−インジウム−ひ素混
晶半導体層の厚さは約１μｍであり、半絶縁性インジウ
ム−りん基板の厚さは約４・００μｍである。半絶縁性
インジウム−りん基板の抵抗率は１０７Ω、（１）程度
であるため、第１図（ａ）に示された抵抗率１０４Ω−
訓 以上の試料ではアルミニウム−インジウム−ひ素混
晶半導体中を流れる電流は半絶縁性インジウム−りん基
板中を流れる電流と同程度あるいはそれ以下と考えられ
る。これより、アルミニウム−インジウム−ひ素混晶半
導体層にｌ ３０ ＫｅＶ以上の加速エネルギーでほう
素イオンを注入することにより、半絶縁性インジウム−
りん基板と同程度あるいはそれ以上の抵抗を持つ絶縁層
が形成されることがわかる。Here, silicon, which is an n-type impurity, has been added to the aluminum-indium-arsenic mixed crystal semiconductor layer so that the electron concentration is about 1019 crn-3. Monovalent boron ions were used as the ion species to be implanted. Figure 1 (a
) is boron ion 1. This figure shows the acceleration energy dependence of the resistivity of the aluminum, indium-arsenic mixed crystal semiconductor layer when implanted with X10]3m-2. When the acceleration energy exceeds 100 KeV, the resistance of the aluminum-indium-arsenic mixed crystal semiconductor layer suddenly increases, and the IS
At OKeV or higher, the resistivity is ]04Ω, a value of (7) or higher. Here, the thickness of the aluminum-indium-arsenic mixed crystal semiconductor layer is about 1 μm, and the thickness of the semi-insulating indium-phosphorous substrate is about 4.00 μm. Since the resistivity of the semi-insulating indium-phosphorous substrate is about 107Ω, (1), the resistivity shown in Fig. 1(a) is 104Ω-
In the above samples, the current flowing through the aluminum-indium-arsenic mixed crystal semiconductor is considered to be about the same level or lower than the current flowing through the semi-insulating indium-phosphorous substrate. From this, by implanting boron ions into the aluminum-indium-arsenic mixed crystal semiconductor layer with an acceleration energy of l 30 KeV or more, semi-insulating indium-arsenic
It can be seen that an insulating layer having a resistance equal to or higher than that of the phosphor substrate is formed.
第１図（ｂ）は、ほう素イオンの注入量によるアルミニ
ウムーインジウム・ひ素混晶半導体層の電気抵抗の変化
を示したものである。FIG. 1(b) shows the change in electrical resistance of the aluminum-indium-arsenic mixed crystal semiconductor layer depending on the amount of boron ions implanted.
ここで加速エネルギーはすべて１８０ ＫｅＶである。Here, the acceleration energy is all 180 KeV.
これより注入されるほう素イオンの注入量が６×］、Ｑ
］２ｃｍ−２から６ Ｘ １０ 】３ｔｙｎ−２のとき
に良好な絶縁性が得られることがわかる。From this, the amount of boron ions implanted is 6×], Q
]2cm-2 to 6×10 ]3tyn-2, it can be seen that good insulation can be obtained.
（効 果）
本発明により、イオン注入を用いてアルミニウム−イン
ジウム−ひ素混晶半導体層の任意の領域を絶縁化するこ
とができ、例えば以下のような産業上の効果をもたらす
。(Effects) According to the present invention, any region of the aluminum-indium-arsenic mixed crystal semiconductor layer can be insulated using ion implantation, and the following industrial effects can be brought about, for example.
（１）前記混晶半導体を用いた半導体レーザあるいは発
光ダイオードの電流注入領域のストライプ化による駆動
電流の低減および周辺不要領域の絶縁化による工程の簡
素化およびこれら発光素子集積化の際の素子間分離工程
の簡素化−歩留り向上。(1) Reduction of drive current by striping the current injection region of a semiconductor laser or light emitting diode using the above-mentioned mixed crystal semiconductor, simplification of process by insulating unnecessary peripheral regions, and inter-element spacing when integrating these light emitting devices. Simplified separation process - improved yield.
（２）前記混晶半導体を用いたなだれ増倍フォトダイオ
ードなどの受光素子の周辺不要領域の絶縁化による暗電
流の低下と工程の簡素化。(2) Reduced dark current and simplified process by insulating unnecessary areas around a light receiving element such as an avalanche multiplication photodiode using the above-mentioned mixed crystal semiconductor.
（３）前記混晶半導体を用いた電界効果ｌ・ランジスタ
の周辺不要領域の絶縁化による工程の簡素化−歩留り向
上およびこれら電界効果トランジスタおよびこれら電界
効果トランジスタと前記発光受光素子との集積化の際の
素子間分離工程の簡素化−歩留り向上。(3) Simplification of the process by insulating unnecessary areas around the field effect transistor using the mixed crystal semiconductor - yield improvement and integration of these field effect transistors and the light emitting/receiving element with these field effect transistors. Simplification of the separation process between elements at the time of production - improved yield.
第１図（ａ）及び（ｂ）は本発明の作用および実施例を
説明する図であり、ほう素イオン注入によるアルミニウ
ム−インジウム−ひ素混晶半導体の抵抗率の変化を示し
た図である。
６一
Ｂ 住人￥（ｃｍ）FIGS. 1(a) and 1(b) are diagrams for explaining the operation and embodiments of the present invention, and are diagrams showing changes in resistivity of an aluminum-indium-arsenic mixed crystal semiconductor due to boron ion implantation. 61B Resident ¥ (cm)
Claims (3)
化されたことを特徴とするアルミニウム−インジウム−
ひ素混晶半導体。(1) Aluminum-indium characterized by being electrically insulated by boron ion implantation
Arsenic mixed crystal semiconductor.
０ＫｅＶ以上であることを特徴とする特許請求の範囲第
１項記載の混晶半導体。(2) The acceleration energy of the implanted boron ions is 13
The mixed crystal semiconductor according to claim 1, wherein the mixed crystal semiconductor has a voltage of 0 KeV or more.
−＾２から６×１０＾１＾３ｃｍ＾−＾２までの範囲で
あることを特徴とする特許請求の範囲第１項および第２
項記載の混晶半導体。(3) Boron ion implantation amount is 6 x 10^1^2cm^
-^2 to 6 x 10^1^3 cm^-^2
The mixed crystal semiconductor described in Section 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60274243A JPS62133775A (en) | 1985-12-05 | 1985-12-05 | Mixed crystal semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60274243A JPS62133775A (en) | 1985-12-05 | 1985-12-05 | Mixed crystal semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62133775A true JPS62133775A (en) | 1987-06-16 |
Family
ID=17538993
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60274243A Pending JPS62133775A (en) | 1985-12-05 | 1985-12-05 | Mixed crystal semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62133775A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09232667A (en) * | 1996-02-21 | 1997-09-05 | Sony Corp | Compound semiconductor device and manufacture thereof |
-
1985
- 1985-12-05 JP JP60274243A patent/JPS62133775A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09232667A (en) * | 1996-02-21 | 1997-09-05 | Sony Corp | Compound semiconductor device and manufacture thereof |
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