JPS62133724A - Formation of thin film by bias sputtering - Google Patents
Formation of thin film by bias sputteringInfo
- Publication number
- JPS62133724A JPS62133724A JP27329485A JP27329485A JPS62133724A JP S62133724 A JPS62133724 A JP S62133724A JP 27329485 A JP27329485 A JP 27329485A JP 27329485 A JP27329485 A JP 27329485A JP S62133724 A JPS62133724 A JP S62133724A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor
- sample
- thin film
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Physical Vapour Deposition (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は高周波放電プラズマを用いてバイアススパッタ
薄膜を半導体試料表面に堆積させるバイアススパッタ薄
膜の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for producing a bias-sputtered thin film in which a bias-sputtered thin film is deposited on the surface of a semiconductor sample using high-frequency discharge plasma.
最近、半導体集積回路のプロセス技術において平担な形
状に金属、あるいは810!薄膜を形成する、バイアス
スパッタ技術の開発が盛んに行なわれている。従来、薄
膜を堆積すべき試料としての半導体基板を設置する平板
電極には金属板あるいはその金属板表面にシリコン薄膜
をコーティングしたものを用いているが、グローと暗部
の境界の空間的なゆらぎの為、試料としての半導体基板
に堆積される薄膜の厚さが極めて不拘一番こなってしま
い集積回路製造の上で問題があった。Recently, in the process technology of semiconductor integrated circuits, metal or 810! Bias sputtering techniques for forming thin films are being actively developed. Conventionally, a metal plate or one coated with a silicon thin film on the surface of the metal plate has been used as the flat plate electrode on which the semiconductor substrate as the sample on which the thin film is to be deposited is placed, but the problem is that spatial fluctuations at the boundary between the glow and the dark area have been avoided. Therefore, the thickness of the thin film deposited on the semiconductor substrate as a sample is extremely unrestricted, which poses a problem in the manufacture of integrated circuits.
本発明は、上記の点に鑑みてなされたもので、薄膜を堆
積すべき試料としての半導体基板面上のグローと暗部の
境界の空間的なゆらぎを減少させて均一な厚さの薄膜を
得るバイアススパッタ薄膜の製造方法を提供することを
目的とする。The present invention has been made in view of the above points, and reduces the spatial fluctuation of the boundary between the glow and dark areas on the surface of a semiconductor substrate as a sample on which a thin film is to be deposited, thereby obtaining a thin film of uniform thickness. An object of the present invention is to provide a method for manufacturing a bias sputtered thin film.
本発明はバイアスバッタ装置を用いた薄膜の堆積におい
て、第4図に示すように薄膜を堆積させるべき半導体を
有する試料41と骸半導体試料41を設置する電極43
の間あるいは周囲に前記試料41よりも例えば径が大き
い半導体からなる基板42を設置するものである。この
場合、好ましくは半導体からなる基板の厚さは薄膜堆積
される半導体試料の厚さ以上のものを用いかつ中央をく
り抜きあるいは凹部45を設けることにより、電極43
との接解面から表面までの高さを前記半導体試料41と
半導体からなる基板42で等しくする。The present invention involves depositing a thin film using a bias batter device, as shown in FIG.
A substrate 42 made of a semiconductor and having a diameter larger than that of the sample 41 is placed between or around the sample 41, for example. In this case, the thickness of the substrate made of semiconductor is preferably equal to or greater than the thickness of the semiconductor sample on which the thin film is deposited, and the electrode 43 is hollowed out or provided with a recess 45 in the center.
The height from the contact surface to the surface is made equal between the semiconductor sample 41 and the substrate 42 made of a semiconductor.
従来のバイアススパッタ装置を用いた場合は、第3図に
示すように電極32上の半導体試料31近傍のグロー3
4と暗部35の境界が試料31の外周部位置で変化して
いる。その為この外周部でのスパッタ作用が中央部より
激しくなる為外周部で膜厚が薄くなる。これに対して本
発明のように半導体からなる基板、42を設置すること
によりグロー45と暗部46の境界の変化が第4図に示
すように半導体試料41の近傍では少なくな4為該半導
体試料41の面内でのスパッタ作用が比較的均一となり
、中央部と外周部との膜厚差が減少する。When a conventional bias sputtering device is used, as shown in FIG.
4 and the dark area 35 change at the outer peripheral position of the sample 31. Therefore, the sputtering action at the outer periphery is more intense than at the center, resulting in a thinner film at the outer periphery. On the other hand, by installing the substrate 42 made of a semiconductor as in the present invention, the change in the boundary between the glow 45 and the dark area 46 is small in the vicinity of the semiconductor sample 41 as shown in FIG. The sputtering action within the plane of the film 41 becomes relatively uniform, and the difference in film thickness between the central portion and the outer peripheral portion is reduced.
以下本発明の一実施例を図面を参照しながら説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第1図は同実施例で使用するバイアススパッタ装置の構
成図であり、第2図はその要部を拡大したものである。FIG. 1 is a block diagram of a bias sputtering apparatus used in the same embodiment, and FIG. 2 is an enlarged view of the main parts thereof.
図に於いて、11は薄膜堆積される試料としての半導体
基板、12は補助的な半導体基板、13は基板支持台兼
電極、14はターゲット材料、15はターゲット電極、
16.17は高周波発振器、18は排気装置、19はA
rガス供給装置、9.10はキャパシタ、lは真空容器
である。In the figure, 11 is a semiconductor substrate as a sample on which a thin film is deposited, 12 is an auxiliary semiconductor substrate, 13 is a substrate support and electrode, 14 is a target material, 15 is a target electrode,
16.17 is a high frequency oscillator, 18 is an exhaust system, 19 is A
r is a gas supply device, 9.10 is a capacitor, and l is a vacuum container.
ここにおいて特徴は薄膜を堆積させる試料としての半導
体基板11と該半導体基板11を設置する電極13の間
あるいは周囲に該半導体基板11よりも大きい補助的な
半導体基板12を設置した点にある。この場合、半導体
板12の厚さは試料である半導体基板11の厚さ以上の
ものを用いて中央をくり抜くあるいは凹部20を設ける
ことにより第2図に示すように電極13との接触面から
表面味での高さを半導体基板11と半導体板12で等し
くすることが重要である。半導体基板11は、試料とし
てSO8基板や3次元IC基板等であってもよく、又半
導体基板12は絶縁基体表面にシリコン層を形成したよ
うなものでもよい。The feature here is that an auxiliary semiconductor substrate 12 larger than the semiconductor substrate 11 is placed between or around the semiconductor substrate 11 as a sample on which a thin film is to be deposited and the electrode 13 on which the semiconductor substrate 11 is placed. In this case, the thickness of the semiconductor substrate 12 can be adjusted by hollowing out the center or providing a recess 20 using a material that is greater than or equal to the thickness of the semiconductor substrate 11 as a sample, so that the thickness of the semiconductor substrate 12 can be adjusted from the contact surface with the electrode 13 to the surface as shown in FIG. It is important that the semiconductor substrate 11 and the semiconductor board 12 have the same height. The semiconductor substrate 11 may be an SO8 substrate, a three-dimensional IC substrate, or the like as a sample, and the semiconductor substrate 12 may be one in which a silicon layer is formed on the surface of an insulating substrate.
実際に第1図に示すような装置を用いて、試料として直
径4インチのSi基板上に中央部で2μmの厚さの5r
oa膜を堆積させる実験を行った。放電条件はArガス
圧IQm ’l’orr 、高周波電力1.5 kw。Actually, using the apparatus shown in Fig. 1, a 5R film with a thickness of 2 μm at the center was placed on a Si substrate with a diameter of 4 inches as a sample.
An experiment was conducted to deposit an OA film. The discharge conditions were Ar gas pressure IQm'l'orr and high frequency power 1.5 kW.
8i0.ターゲット直流バイアス800V、基板側直流
バイアス130■とした。補助的なSi基板としては第
2図に示すように6インチのSt基板12の中央部を直
径4インチでくり抜いたものの上に高さが等しくなるよ
うに設置した。その結果、第5図に示すように従来のバ
イアススパッタ方法では(a)に示す通り15〜16%
程度あった膜厚のバラツキが、本発明の方法においては
(b)に示すようにバラツキが11〜12%程度に減少
した。ここでバラツキは、4インチウェハの面内で5点
を測定しそれぞれの膜厚をTI(1=l〜5)とし、次
式によりバラツキDを求めた。8i0. The target DC bias was 800V, and the substrate side DC bias was 130V. As shown in FIG. 2, the auxiliary Si substrate was placed on a 6-inch St substrate 12 with a 4-inch diameter hollowed out in the center so that the heights were the same. As a result, as shown in Fig. 5, in the conventional bias sputtering method, as shown in (a), 15 to 16%
In the method of the present invention, the variation in film thickness was reduced to about 11 to 12%, as shown in (b). Here, the variation was measured at 5 points within the surface of a 4-inch wafer, and the film thickness of each was set as TI (1=1 to 5), and the variation D was determined by the following formula.
以上の実施例に詔いてはターゲット14の材料としては
8i0!を用いたが、チタン、タングステン等の金属で
も、同様な効果が得られる。また、高周波放電を発生さ
せる2枚の電極13.15の位置関係は平行でなくても
よく、上下逆になっていてもよく、さらに水平でなくて
も同様な効果が得られる。According to the above embodiment, the material of the target 14 is 8i0! was used, but similar effects can be obtained with metals such as titanium and tungsten. Further, the positional relationship of the two electrodes 13.15 for generating high-frequency discharge does not have to be parallel, they can be upside down, and the same effect can be obtained even if they are not horizontal.
第1図は本発明の一実施例で用いるバイアススパッタ装
置の構成図、第2図はその要部を拡大して示す断面図、
第3図及び第4図は従来方法及び本発明方法による暗部
とグローの境界の状態を示す説明図、第5図は従来と本
発明方法の効果の相違を示す特性図である。
11・・・半導体基板(試料)、12・・・半導体基板
、13・・・基板支持台兼電極、14・・・ターゲット
材料、15・・・ターゲット電極、16.17・・・高
周波発振器、18・・・排気装置、19・・・Arガス
供給装置、8.9・・・キャパシタ、1・・・真空容器
。
代理人 弁理士 則 近 憲 佑
同 竹 花 喜久男
第1図
第2図
麟紗ヤのI〈ラッキD (咲)
(α)
第
喉辱のバクツキD(弓)
5図FIG. 1 is a configuration diagram of a bias sputtering apparatus used in an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing an enlarged view of its main parts.
FIGS. 3 and 4 are explanatory diagrams showing the state of the boundary between a dark area and a glow according to the conventional method and the method of the present invention, and FIG. 5 is a characteristic diagram showing the difference in effect between the conventional method and the method of the present invention. DESCRIPTION OF SYMBOLS 11... Semiconductor substrate (sample), 12... Semiconductor substrate, 13... Substrate support stand and electrode, 14... Target material, 15... Target electrode, 16.17... High frequency oscillator, 18... Exhaust device, 19... Ar gas supply device, 8.9... Capacitor, 1... Vacuum container. Agent Patent Attorney Noriyuki Ken Yudo Takehana Kikuo Figure 1 Figure 2 Rinsaya's I〈Rakki D (Saki) (α) No. 1 Bakutsuki D (Bow) Figure 5
Claims (3)
膜を半導体試料表面に堆積させる際に前記半導体試料と
それを保持する電極の間あるいは周囲に前記導体試料よ
りも大きい半導体からなる基板を設置することを特徴と
するバイアススパッタ薄膜の製造方法。(1) When depositing a bias-sputtered thin film on the surface of a semiconductor sample using high-frequency discharge plasma, a substrate made of a semiconductor larger than the conductor sample is installed between or around the semiconductor sample and the electrode that holds it. A method for manufacturing a bias sputtered thin film.
べく半導体からなる基板に半導体試料と略同等の直径及
び高を有する凹部あるいは穴を形成することを特徴とす
る特許請求範囲第1項記載のバイアススパッタ薄膜の製
造方法。(2) Claim 1, characterized in that a recess or hole having a diameter and height substantially equal to that of the semiconductor sample is formed in the substrate made of semiconductor so that the semiconductor sample is accommodated within the substrate made of semiconductor. A method for producing bias sputtered thin films.
せることを特徴とする特許請求範囲第2項記載のバイア
ススパッタ薄膜の製造方法。(3) A method for producing a bias sputtered thin film according to claim 2, characterized in that the semiconductor sample is positioned at the center of a substrate made of a semiconductor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27329485A JPS62133724A (en) | 1985-12-06 | 1985-12-06 | Formation of thin film by bias sputtering |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27329485A JPS62133724A (en) | 1985-12-06 | 1985-12-06 | Formation of thin film by bias sputtering |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62133724A true JPS62133724A (en) | 1987-06-16 |
Family
ID=17525846
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP27329485A Pending JPS62133724A (en) | 1985-12-06 | 1985-12-06 | Formation of thin film by bias sputtering |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62133724A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5591493A (en) * | 1994-06-30 | 1997-01-07 | Texas Instruments Incorporated | Structure and method for incorporating an inductively coupled plasma source in a plasma processing chamber |
-
1985
- 1985-12-06 JP JP27329485A patent/JPS62133724A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5591493A (en) * | 1994-06-30 | 1997-01-07 | Texas Instruments Incorporated | Structure and method for incorporating an inductively coupled plasma source in a plasma processing chamber |
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