JPS62128667U - - Google Patents

Info

Publication number
JPS62128667U
JPS62128667U JP1455086U JP1455086U JPS62128667U JP S62128667 U JPS62128667 U JP S62128667U JP 1455086 U JP1455086 U JP 1455086U JP 1455086 U JP1455086 U JP 1455086U JP S62128667 U JPS62128667 U JP S62128667U
Authority
JP
Japan
Prior art keywords
printed board
terminal
wiring pattern
soldering
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1455086U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1455086U priority Critical patent/JPS62128667U/ja
Publication of JPS62128667U publication Critical patent/JPS62128667U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例によるフラツトパツ
ケージICを実装したプリント板の平面図とA―
A′断面図、第2図は従来例による同上平面図と
A―A′断面図である。 1:フラツトパツケージ、1C,2:ICの半
田付用ランド、3:ICの端子、4,4′:配線
パターン、5:ICの不使用端子下のシルク印刷
、6:プリント板。
FIG. 1 is a plan view of a printed board on which a flat package IC according to an embodiment of the present invention is mounted, and A-
FIG. 2 is a plan view of the conventional example and a sectional view taken along line A-A'. 1: Flat package, 1C, 2: Land for IC soldering, 3: IC terminal, 4, 4': Wiring pattern, 5: Silk printing under unused terminal of IC, 6: Printed board.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] リード挿入用穴を使用せずにプリント板上の配
線パターンに面実装形ICの端子を半田付けして
実装するプリント板において、前記ICの不使用
端子と、この端子下に設けた配線パターンとの間
に絶縁被膜を形成したことを特徴とするプリント
板。
In a printed board in which a terminal of a surface mount IC is mounted by soldering to a wiring pattern on a printed board without using a lead insertion hole, an unused terminal of the IC and a wiring pattern provided below this terminal. A printed board characterized by having an insulating film formed in between.
JP1455086U 1986-02-05 1986-02-05 Pending JPS62128667U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1455086U JPS62128667U (en) 1986-02-05 1986-02-05

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1455086U JPS62128667U (en) 1986-02-05 1986-02-05

Publications (1)

Publication Number Publication Date
JPS62128667U true JPS62128667U (en) 1987-08-14

Family

ID=30804637

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1455086U Pending JPS62128667U (en) 1986-02-05 1986-02-05

Country Status (1)

Country Link
JP (1) JPS62128667U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0357960U (en) * 1989-10-11 1991-06-05

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0357960U (en) * 1989-10-11 1991-06-05

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