JPS62128174A - Charge transfer device - Google Patents

Charge transfer device

Info

Publication number
JPS62128174A
JPS62128174A JP26846185A JP26846185A JPS62128174A JP S62128174 A JPS62128174 A JP S62128174A JP 26846185 A JP26846185 A JP 26846185A JP 26846185 A JP26846185 A JP 26846185A JP S62128174 A JPS62128174 A JP S62128174A
Authority
JP
Japan
Prior art keywords
film
oxide film
charge transfer
gate
transfer device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26846185A
Other languages
Japanese (ja)
Inventor
Shiro Hine
日根　史郎
Satoshi Hirose
広瀬　諭
Hidekazu Yamamoto
秀和 山本
Sotohisa Asai
浅井　外壽
Masafumi Ueno
雅史 上野
Naoki Yuya
直毅 油谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP26846185A priority Critical patent/JPS62128174A/en
Publication of JPS62128174A publication Critical patent/JPS62128174A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To easily differentiate the surface potentials of electrode transfer channel below respective transfer electrodes between respective transfer electrodes without increasing processes by a method wherein gate oxide film only is formed below the first transfer electrodes while forming the gate oxide film and a gate nitride film below the second transfer electrodes. CONSTITUTION:A gate oxide film 2 and a polysilicon film 3 are formed on the surface of substrate 1. First, multiple resist film patterns 5a are formed to form the first transfer electrodes 3a by selectively etching the polysilicon film 3 using the resist film patterns 5a as masks. Second, the resist film patterns 5a are removed to form an oxide film 4 by thermooxidizing the surface of the first electrodes 3a. Later a nitride film 6 is formed on the exposed surface of gate oxide film 2 and the surface of oxide film 4 by ECR type PECVD device further continuously forming an amorphous silicon film 7 on the surface of nitride film 6. Third, the amorphous silicon film 7 and the nitride film 6 are seccessively and selectively dryetched to form the second transfer electrodes 7a and a gate nitride films 6a using resist film patterns 8a as masks. Finally, the resist film patterns 8a are removed to form a two phase driving charge transfer device.

Description

【発明の詳細な説明】 ［産業上の利用分野） この発明は渭荷括送装コに関し、待に転送電極下の表面
ポテンシャルに容易に差をつけることができ、かつウェ
ハプロセスでの歩留り向上させることができる電荷転送
装置に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a bulk transfer device, which enables easy differentiation of the surface potential under the transfer electrode and improves yield in wafer processing. The present invention relates to a charge transfer device that can perform

〔従来の技術］ 第２Ａ図〜第２Ｅ図は、２相駆動電荷転送装置の製造方
法の主要工程段階における状態を示す断面図である。こ
の製造方法について説明すると、まず、ｐ形シリコン基
板１の表面にゲート酸化膜２を形成し、このゲート酸化
膜の表面に第１のポリシリコン膜３を形成する（第２Ａ
図）。次に、第１のポリシリコン膜３の表面に互いに間
隔を隔てて複数個のレジスト膜パターン５ａを形成し、
このレジスト膜パターンをマスクとして第１のポリシリ
コン膜３を選択エツチングして第１の転送電極３ａを形
成する。この後、レジスト膜パターン５ａをマスクとし
てゲート酸化膜２の露出した表面からｐ形不純物をイオ
ン注入してｐ形シリコン基板１の表面にｐ＋形イオン注
入層９を形成する（第２Ｂ図）。次に、レジスト膜パタ
ーン５ａおよびゲート酸化膜２の露出した部分を除去し
、ｐ形シリコン基板１の露出した表面および第１転送電
極３ａの表面を酸化して、ゲート酸化膜２の膜厚より薄
い膜厚の酸化膜４０および酸化膜４１を形成する。この
後、酸化膜４０および４１の表面に第２のポリシリコン
膜１０を形成する（第２Ｃ図）。次に、第２のポリシリ
コン膜１０の表面の所定部に互いに間隔を隔てて複数個
のレジスト膜パターン８ａを形成し、レジスト膜パター
ン８ａをマスクとして第２のポリシリコン１１０を選択
エツチングして酸化膜４１で覆われた第１転送電極３８
間に第２転送電極１０ａを形成する。次に、レジスト膜
パターン８ａを除去すると２相駆動Ｔｉ荷転送装置が完
成される。[Prior Art] FIGS. 2A to 2E are cross-sectional views showing the main process steps of a method for manufacturing a two-phase drive charge transfer device. To explain this manufacturing method, first, a gate oxide film 2 is formed on the surface of a p-type silicon substrate 1, and a first polysilicon film 3 is formed on the surface of this gate oxide film (second A).
figure). Next, a plurality of resist film patterns 5a are formed at intervals on the surface of the first polysilicon film 3,
Using this resist film pattern as a mask, first polysilicon film 3 is selectively etched to form first transfer electrode 3a. Thereafter, using the resist film pattern 5a as a mask, p-type impurities are ion-implanted from the exposed surface of the gate oxide film 2 to form a p+-type ion-implanted layer 9 on the surface of the p-type silicon substrate 1 (FIG. 2B). Next, the exposed portions of the resist film pattern 5a and the gate oxide film 2 are removed, and the exposed surface of the p-type silicon substrate 1 and the surface of the first transfer electrode 3a are oxidized so that the thickness of the gate oxide film 2 is smaller than that of the gate oxide film 2. A thin oxide film 40 and an oxide film 41 are formed. Thereafter, a second polysilicon film 10 is formed on the surfaces of oxide films 40 and 41 (FIG. 2C). Next, a plurality of resist film patterns 8a are formed at predetermined intervals on the surface of the second polysilicon film 10, and the second polysilicon 110 is selectively etched using the resist film patterns 8a as a mask. First transfer electrode 38 covered with oxide film 41
A second transfer electrode 10a is formed in between. Next, the resist film pattern 8a is removed to complete the two-phase drive Ti load transfer device.

第３Ａ図、第３Ｂ図はこの２相駆動電荷転送装置の動作
を説明するための図である。FIGS. 3A and 3B are diagrams for explaining the operation of this two-phase drive charge transfer device.

次に、この２相駆動’Ｒ？ｒＪ転送装置の動作を第３Ａ
図、第３Ｂ図を参照しながら説明する。第２Ｅ図のよう
に構成された２相駆動電荷転送装置に第３Ｂ図に示した
ドロップ・クロック・パルスΦ１およびΦ２を印加する
と、時刻１．〜【Ｓにおいて第１転送電極３ａ、第２転
送電極１０ａ下の電荷転送チャンネルの表面ポテンシャ
ルは第３Ａｉに示したようになり、信号電荷Ｑｓ１ａは
右方向へ転送される。この動作を繰返すことによって、
入力された信号電荷ＱｓＩａは左から右へ転送され、フ
ローティングディフュージョンアンプなどの出力用プリ
アンプを経て外部に読出される。Next, this two-phase drive 'R? The operation of the rJ transfer device is explained in 3rd A.
This will be explained with reference to FIGS. 3B and 3B. When drop clock pulses Φ1 and Φ2 shown in FIG. 3B are applied to the two-phase drive charge transfer device configured as shown in FIG. 2E, time 1. ~ [S] The surface potential of the charge transfer channel under the first transfer electrode 3a and the second transfer electrode 10a becomes as shown in No. 3 Ai, and the signal charge Qs1a is transferred to the right. By repeating this action,
The input signal charge QsIa is transferred from left to right and read out to the outside through an output preamplifier such as a floating diffusion amplifier.

［発明が解決しようとする問題点］ 従来の２相駆動電荷転送装置は以上のように構成されて
おり、第１転送電極３ａ下のゲート酸化ｐＪ２の膜厚と
第２転送電ｔｌ！１０ａ下のゲート酸化膜４０のｐＩｉ
厚とが異なる結果、第１転送電極３ａ下と第２転送電極
１０ａ下で電荷転送チャンネルの表面ポテンシャルに差
が生じることとなる。電荷転送量を大きくするには、こ
の表面ポテンシャルの差を大きくする必要があり、従来
は、ｐ形シリコン基板１にｐ“形イオン注入層９を形成
することよってこの差を積極的につけていた。しかしな
がら、このｐ＋形イオン注入層９の形成はウェハプロセ
スにおける工程の増加につながり、ウェハプロセスの歩
留りを低下させるという問題点があった。[Problems to be Solved by the Invention] The conventional two-phase drive charge transfer device is configured as described above, and the thickness of the gate oxide pJ2 under the first transfer electrode 3a and the second transfer voltage tl! pIi of gate oxide film 40 under 10a
As a result of the difference in thickness, a difference occurs in the surface potential of the charge transfer channel under the first transfer electrode 3a and under the second transfer electrode 10a. In order to increase the amount of charge transfer, it is necessary to increase this difference in surface potential, and in the past, this difference was actively created by forming a p" type ion implantation layer 9 on the p type silicon substrate 1. However, the formation of the p + -type ion implantation layer 9 leads to an increase in the number of steps in the wafer process, resulting in a problem of lowering the yield of the wafer process.

この発明は上記のような問題点を解消するためになされ
たちので、ウェハプロセスにおける工程を増加させるこ
となく、各転送電極下の電荷転送チャンネルの表面ポテ
ンシャルに各転送電極間で容易に差をつけることができ
る電荷転送装置を得ることを目的とする。This invention was made to solve the above problems, and it is possible to easily differentiate the surface potential of the charge transfer channel under each transfer electrode between each transfer electrode without increasing the number of steps in the wafer process. The object of the present invention is to obtain a charge transfer device that can perform the following steps.

［問題点を解決するための手段］ この発明に係る電荷転送装置は、基板の表面に第１ゲー
ト絶縁膜を形成し、第１ゲート絶縁膜の表面に互いに間
隔を隔てて複数個のポリシリコンからなる第１転送電極
を形成し、第１転送電楊の表面に酸化膜を形成し、少な
くとも露出した基板の表面にＥＣＲ型ＰＥＣＶＤ装置に
よって第２ゲート絶縁膜を形成し、第２ゲート絶縁膜の
表面にＥＣＲ型ＰＥＣＶＤ装置によって複数個のアモル
ファスシリコンまたは微結晶シリコンからなる第２転送
電極を形成したものである。[Means for Solving the Problems] A charge transfer device according to the present invention includes a first gate insulating film formed on the surface of a substrate, and a plurality of polysilicon films arranged at intervals on the surface of the first gate insulating film. forming a first transfer electrode, forming an oxide film on the surface of the first transfer electrode, forming a second gate insulating film on at least the exposed surface of the substrate using an ECR type PECVD apparatus; A plurality of second transfer electrodes made of amorphous silicon or microcrystalline silicon are formed on the surface of the substrate using an ECR type PECVD apparatus.

［作用コ この発明においては、第１転送電極下に第１ゲー゛ト絶
縁膜のみが形成され、第２転送電極下に第１および第２
ゲート絶［５１が形成されるので、第１転送電極下の電
荷転送チャンネルの表面ポテンシャルと第２転送電極下
の電荷転送チャンネルの表面ポテンシャルとの間に差が
つく。また、ＥＣＲ型ＰＥＣＶＤ１！置によって、第２
ゲート絶縁膜とアモルファスシリコンまたは微結晶シリ
コンからなる第２転送電極とを低温下で連続的に容易に
形成することができる。また、第２ゲート絶縁膜と第２
転送電極とはこの装置によって形成されるので、膜間の
界面順位が安定し、また膜中への不純物の混入が少なく
なり、さらには膜中のストレスが制御される。[Function] In this invention, only the first gate insulating film is formed under the first transfer electrode, and the first and second gate insulating films are formed under the second transfer electrode.
Since the gate isolation [51] is formed, a difference is created between the surface potential of the charge transfer channel under the first transfer electrode and the surface potential of the charge transfer channel under the second transfer electrode. Also, ECR type PECVD1! Depending on the location, the second
The gate insulating film and the second transfer electrode made of amorphous silicon or microcrystalline silicon can be easily and continuously formed at a low temperature. In addition, the second gate insulating film and the second
Since the transfer electrode is formed by this device, the interface order between the films is stabilized, impurities are less mixed into the film, and stress in the film is controlled.

［実施例］ 以下、この発明の実施例を図について説明する。[Example] Embodiments of the present invention will be described below with reference to the drawings.

第１Ａ図〜第１Ｅ図は、この発明の実施例である２相駆
動電荷転送装置の製造方法の主要工程段階における状態
を示す断面図である。この製造方法について説明すると
、まず、ｐ形シリコン基板１の表面にゲート酸化膜２を
形成し、この後ゲート酸化ｍ２の表面にポリシリコン膜
３を形成する（第１Ａ図）。次に、ポリシリコン膜３の
表面の所定部に互いに間隔を隔てて複数個のレジスト膜
パターン５ａを形成し、このレジスト膜パターンをマス
クとしてポリシリコン膜３を選択エツチングして第１転
送電極３ａを形成する（第１Ｂ図）。1A to 1E are cross-sectional views showing the main process steps of a method for manufacturing a two-phase drive charge transfer device according to an embodiment of the present invention. To explain this manufacturing method, first, a gate oxide film 2 is formed on the surface of a p-type silicon substrate 1, and then a polysilicon film 3 is formed on the surface of the gate oxide m2 (FIG. 1A). Next, a plurality of resist film patterns 5a are formed at predetermined intervals on the surface of the polysilicon film 3, and using the resist film patterns as a mask, the polysilicon film 3 is selectively etched to form the first transfer electrode 3a. (Figure 1B).

次に、レジスト膜パターン５ａを除去し、この後第１転
送電極３ａの表面を熱酸化して酸化ｌ１１４を形成する
。この後、ゲート酸化膜２の露出した表面および酸化膜
４の表面にＥ　ＣＲ（Ｅ　ＩｅｃｔｒｏｎＣｙｃｌｏｔ
ｒｏｎ　　Ｒｅｓｏｎａｎｃｅ）型ＰＥＣＶＤ’（Ｐｌ
ａ＋ｖ＋ａ　　Ｅ　ｎｈａｎｃｅｄ　Ｃｈｅｎ＋ｔｃａ
ｌ　Ｖａｐｏｕｒ　［）ｅｐｏｓｉ口ｏｎ　）装置によ
って窒化膜６を形成し、続いて窒化膜６の表面に同じＥ
ＣＲ型ＰＥＣＶＤ装置によって連続的にアモルファスシ
リコン膜７を形成する。このＥＣＩ（型ＰＥＣＶＤ装置
は、基板温度が室温から３００℃程度までの低温下で熱
窒化膜と同等のプラズマ窒化膜を形成でき、しかも、窒
素ガスを導入するかしないかによって、窒化膜を形成す
るかアモルファスシリコン膜を形成するかという制御が
可能である。また、この装置では、１０−４７　ｏｒｒ
程度の高真空下で堆積を行なうため形成された膜中への
不純物の混入が少なくなり、しかも、窒化膜、アモルフ
ァスシリコン膜の連続形成を行なえるため１１間の界面
順位を安定させる上で都合が良い。また、この装置は形
成された膜中のストレスを制御することができるのでデ
バイス作成上好都合である。次に、アモルファスシリコ
ン膜７の表面の所定部に互いに間隔を隔てて複数個のレ
ジスト膜パターン８ａを形成し、このレジスト膜パター
ンをマスクとしてアモルファスシリコン膜７および窒化
膜６を順次選択ドライエツチングして第２転送Ｎ極７ａ
およびゲート窒化膜６ａを形成する（第１Ｄ図）。次に
、レジスト膜パターン８ａを除去すると２相駆動電荷転
送装置が完成される。Next, the resist film pattern 5a is removed, and then the surface of the first transfer electrode 3a is thermally oxidized to form oxide l114. After that, an ECR (E electron cycle) is applied to the exposed surface of the gate oxide film 2 and the surface of the oxide film 4.
ron Resonance) type PECVD' (Pl
a+v+a Enhanced Chen+tca
A nitride film 6 is formed using a Vapor [)eposit on] device, and then the same E is applied to the surface of the nitride film 6.
An amorphous silicon film 7 is continuously formed using a CR type PECVD apparatus. This ECI (type PECVD equipment) can form a plasma nitride film equivalent to a thermal nitride film at low substrate temperatures from room temperature to about 300°C, and can also form a nitride film depending on whether or not nitrogen gas is introduced. It is possible to control whether to form an amorphous silicon film or an amorphous silicon film.
Since the deposition is carried out under a moderately high vacuum, there is less contamination of impurities into the formed film.Moreover, since the nitride film and amorphous silicon film can be formed continuously, it is convenient for stabilizing the interface order between 11. is good. Furthermore, this apparatus is convenient for device production because it can control stress in the formed film. Next, a plurality of resist film patterns 8a are formed at predetermined intervals on the surface of the amorphous silicon film 7, and using the resist film patterns as a mask, the amorphous silicon film 7 and the nitride film 6 are sequentially selectively dry etched. second transfer north pole 7a
Then, a gate nitride film 6a is formed (FIG. 1D). Next, the resist film pattern 8a is removed to complete the two-phase drive charge transfer device.

以上のように、第１転送電ｍｓａ下にゲート酸化膜２の
みを形成し、第２転送１！極７ａ下にゲート酸化１１２
およびゲート窒化ｍ６ａを形成することによって、第１
転送電極３ａ下の電荷転送チャンネルの表面ポテンシャ
ルと第２転送電極７ａ下の電荷転送チャンネルの表面ポ
テンシャルとの間に差をつけることができ、この発明に
よる２相駆動電荷転送装置は、２相駆動用ポテンシヤル
バリヤを設けるために従来用いられていたｐ＋形イオン
注入層９を、ＥＣＲ型ＰＥＣＶＤ装置によって形成され
たゲート窒化！！！６ａ−ゲート酸化膜２で置き換えた
ことを特徴とするものである。As described above, only the gate oxide film 2 is formed under the first transfer voltage msa, and the second transfer 1! Gate oxidation 112 under pole 7a
and gate nitride m6a.
A difference can be made between the surface potential of the charge transfer channel under the transfer electrode 3a and the surface potential of the charge transfer channel under the second transfer electrode 7a, and the two-phase drive charge transfer device according to the present invention has two-phase drive The p+ type ion implantation layer 9, which was conventionally used to provide a potential barrier, was replaced by gate nitridation formed by an ECR type PECVD device! ! ! 6a--The gate oxide film 2 is replaced with the gate oxide film 2.

次に、この２相駆動電荷転送装置の動作については従来
の２相駆動電荷転送装置の動作と全く同様である。Next, the operation of this two-phase drive charge transfer device is exactly the same as that of the conventional two-phase drive charge transfer device.

なお、上記実施例では、第２転送電極を形成するとき、
ＥＣＲ型ＰＥＣＶＤ装置でまず窒化膜を形成し、次にア
モルファスシリコン膜を形成したが、窒化膜の代わりに
酸化膜を形成するようにしてもよい。この場合は、窒化
膜形成の際の窒素ガス導入の代わりに酸素ガスを導入す
ればよいだけである。In addition, in the above embodiment, when forming the second transfer electrode,
Although a nitride film was first formed and then an amorphous silicon film was formed using an ECR type PECVD apparatus, an oxide film may be formed instead of the nitride film. In this case, it is only necessary to introduce oxygen gas instead of nitrogen gas when forming the nitride film.

また、第２転送電極下の絶縁膜は、上記の窒化膜のみ、
または酸化膜のみだけではなく、酸化膜上に窒化膜を形
成した後にアモルファスシリコン膜とする構成または酸
化膜と窒化膜の順序を替えた構成にしてもよい。In addition, the insulating film under the second transfer electrode is only the above nitride film.
Alternatively, instead of using only an oxide film, a structure in which a nitride film is formed on an oxide film and then an amorphous silicon film is formed, or a structure in which the order of the oxide film and the nitride film is changed may be used.

また、第２転送電極下に、従来例と同様、表面ポテンシ
ャル差をさらにつけるためにｐ＋形ビイオン注入層設け
てもよい。Further, as in the conventional example, a p+ type bio-ion implantation layer may be provided under the second transfer electrode in order to further increase the surface potential difference.

また、上記実施例では、第２転送電極をＥＣＲ型ＰＥＣ
ＶＤｖｔＩによって形成されたアモルファスシリコン膜
から形成する場合について示したが、この装置によって
微結晶シリコン膜を形成し、この膜から第２転送電極を
形成するようにしてもよい。Further, in the above embodiment, the second transfer electrode is an ECR type PEC.
Although the case of forming from an amorphous silicon film formed by VDvtI has been shown, a microcrystalline silicon film may be formed using this apparatus, and the second transfer electrode may be formed from this film.

［発明の効果］ 以上のようにこの発明によれば、基板の表面に第１ゲー
ト絶縁膜を形成し、第１ゲート絶縁膜の表面に互いに間
隔を隔てて複数個のポリシリコン膜からなる第１転送電
極を形成し、第１転送電極の表面に酸化膜を形成し、少
なくとも露出した基板の表面にＥＣＲ型ＰＥＣＶＤ装置
によって第２ゲート絶縁躾を形成し、第２ゲート絶縁膜
の表面にＥＣＲ型ＰＥＣＶＤ装置によって複数個のアモ
ルファスシリコンまたは微結晶シリコンからなる第２転
送電極を形成する構成としたので、ウェハプロセスにお
ける工程を増加させることなく、各転送電極下の電荷転
送チャンネルの表面ポテンシャルに各転送電極間で容易
に差をつけることができる電荷転送装置を得ることがで
きる。[Effects of the Invention] As described above, according to the present invention, a first gate insulating film is formed on the surface of a substrate, and a plurality of polysilicon films made of a plurality of polysilicon films are formed on the surface of the first gate insulating film at intervals. A first transfer electrode is formed, an oxide film is formed on the surface of the first transfer electrode, a second gate insulation film is formed on at least the exposed surface of the substrate using an ECR type PECVD apparatus, and an ECR type PECVD film is formed on the surface of the second gate insulation film. The second transfer electrode made of a plurality of amorphous silicon or microcrystalline silicon is formed using a type PECVD apparatus, so that the surface potential of the charge transfer channel under each transfer electrode can be adjusted to the surface potential of the charge transfer channel under each transfer electrode without increasing the number of steps in the wafer process. A charge transfer device that can easily differentiate between transfer electrodes can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第１Ａ図〜第１Ｅ図は、この発明の実施例である２相駆
動電荷転送装置の製造方法の主要工程段階における状態
を示す断面図である。 第２Ａ図〜第２Ｅ図は、従来の２相駆動電荷転送装置の
製造方法の主要工程段階における状態を示す断面図であ
る。 第３Ａ図、第３Ｂ図は、２相駆動電荷転送装置の動作を
説明するための図である。 図において、１はｐ形シリコン基板、２はゲート酸化膜
、３はポリシリコン膜、３ａは第１転送電極、４は酸化
膜、５ａ　、　８ａはレジスト膜パターン、６は窒化膜
、６ａはゲート窒化膜、７はアモルファスシリコン膜、
７ａは第２転送電極でわる。 なお、各図中同一符号は同一または相当部分を示す。 代　　理　　人　　　　　大　　岩　　増　　雄第１Ａ
図 第２Ａ図 アイ研究所内 １番地　三菱電機株式会社エル・ニス・１番地　三菱電
機株式会社エル・ニス・手続補正書（自発） ２１発明の名称 電荷転送装置 ３、補正をする者 ５、補正の対象 図面の第１Ｄ図および第１Ｅ図 ６、補正の内容 図面の第１Ｄ図および第１Ｅ図を別紙のとおり。 以上1A to 1E are cross-sectional views showing the main process steps of a method for manufacturing a two-phase drive charge transfer device according to an embodiment of the present invention. FIGS. 2A to 2E are cross-sectional views showing the main process steps of a conventional method for manufacturing a two-phase drive charge transfer device. FIGS. 3A and 3B are diagrams for explaining the operation of the two-phase drive charge transfer device. In the figure, 1 is a p-type silicon substrate, 2 is a gate oxide film, 3 is a polysilicon film, 3a is a first transfer electrode, 4 is an oxide film, 5a and 8a are resist film patterns, 6 is a nitride film, and 6a is a gate nitride film, 7 is an amorphous silicon film,
7a is the second transfer electrode. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa 1st A
Figure 2A Eye Research Institute Address 1 Mitsubishi Electric Corporation El Nis Address 1 Mitsubishi Electric Corporation El Nis Procedural Amendment (Voluntary) 21 Name of Invention Charge Transfer Device 3, Person Making Amendment 5, Amendment Figures 1D and 1E of the subject drawings and Figures 1D and 1E of the drawings related to the amendment are as attached. that's all

Claims (5)

【特許請求の範囲】[Claims] （１）基板と、 前記基板の表面に形成される第１ゲート絶縁膜と、 前記第１ゲート絶縁膜の表面に互いに間隔を隔てて形成
される、複数個のポリシリコンからなる第１転送電極と
、 前記第１転送電極の表面に形成される酸化膜と、少なく
とも前記露出した基板の表面にＥＣＲ型ＰＥＣＶＤ装置
によって形成される第２ゲート絶縁膜と、 前記第２ゲート絶縁膜の表面にＥＣＲ型ＰＥＣＶＤ装置
によつて形成される、複数個のアモルファスシリコンま
たは微結晶シリコンからなる第２転送電極とを備えた電
荷転送装置。(1) A substrate, a first gate insulating film formed on the surface of the substrate, and a plurality of first transfer electrodes made of polysilicon formed at intervals on the surface of the first gate insulating film. an oxide film formed on the surface of the first transfer electrode; a second gate insulating film formed on at least the exposed surface of the substrate by an ECR type PECVD apparatus; and an ECR-type PECVD film formed on the surface of the second gate insulating film. A charge transfer device comprising a plurality of second transfer electrodes made of amorphous silicon or microcrystalline silicon formed by a type PECVD apparatus. （２）前記第１ゲート絶縁膜は酸化膜である特許請求の
範囲第１項記載の電荷転送装置。(2) The charge transfer device according to claim 1, wherein the first gate insulating film is an oxide film. （３）前記第２ゲート絶縁膜は窒化膜である特許請求の
範囲第１項または第２項記載の電荷転送装置。(3) The charge transfer device according to claim 1 or 2, wherein the second gate insulating film is a nitride film. （４）前記第２ゲート絶縁膜は酸化膜である特許請求の
範囲第１項または第２項記載の電荷転送装置。(4) The charge transfer device according to claim 1 or 2, wherein the second gate insulating film is an oxide film. （５）前記第２ゲート絶縁膜は酸化膜と窒化膜の２層膜
である特許請求の範囲第１項または第２項記載の電荷転
送装置。(5) The charge transfer device according to claim 1 or 2, wherein the second gate insulating film is a two-layer film of an oxide film and a nitride film.
JP26846185A 1985-11-28 1985-11-28 Charge transfer device Pending JPS62128174A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26846185A JPS62128174A (en) 1985-11-28 1985-11-28 Charge transfer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26846185A JPS62128174A (en) 1985-11-28 1985-11-28 Charge transfer device

Publications (1)

Publication Number Publication Date
JPS62128174A true JPS62128174A (en) 1987-06-10

Family

ID=17458823

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26846185A Pending JPS62128174A (en) 1985-11-28 1985-11-28 Charge transfer device

Country Status (1)

Country Link
JP (1) JPS62128174A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0685234A (en) * 1992-05-11 1994-03-25 Samsung Electron Co Ltd Image sensor device and its manufacture
US6165695A (en) * 1998-12-01 2000-12-26 Advanced Micro Devices, Inc. Thin resist with amorphous silicon hard mask for via etch application
KR20120109310A (en) * 2011-03-25 2012-10-08 소니 주식회사 Solid-state imaging device, manufacturing method of the same and electronic apparatus

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0685234A (en) * 1992-05-11 1994-03-25 Samsung Electron Co Ltd Image sensor device and its manufacture
US6165695A (en) * 1998-12-01 2000-12-26 Advanced Micro Devices, Inc. Thin resist with amorphous silicon hard mask for via etch application
KR20120109310A (en) * 2011-03-25 2012-10-08 소니 주식회사 Solid-state imaging device, manufacturing method of the same and electronic apparatus
JP2012204562A (en) * 2011-03-25 2012-10-22 Sony Corp Solid state image pickup device, manufacturing method of the solid state image pickup device, and electronic apparatus

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