JPS62126677A - Thin film transistor array - Google Patents

Thin film transistor array

Info

Publication number
JPS62126677A
JPS62126677A JP60270355A JP27035585A JPS62126677A JP S62126677 A JPS62126677 A JP S62126677A JP 60270355 A JP60270355 A JP 60270355A JP 27035585 A JP27035585 A JP 27035585A JP S62126677 A JPS62126677 A JP S62126677A
Authority
JP
Japan
Prior art keywords
source
gate
wiring
layer
tft
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60270355A
Other languages
Japanese (ja)
Inventor
Hirohisa Tanaka
田仲　広久
Kohei Kishi
岸　幸平
Hiroaki Kato
博章 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP60270355A priority Critical patent/JPS62126677A/en
Priority to GB8628172A priority patent/GB2185622B/en
Priority to DE19863640174 priority patent/DE3640174A1/en
Publication of JPS62126677A publication Critical patent/JPS62126677A/en
Priority to US07/267,680 priority patent/US4935792A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4825—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body for devices consisting of semiconductor layers on insulating or semi-insulating substrates, e.g. silicon on sapphire devices, i.e. SOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Liquid Crystal (AREA)

Abstract

PURPOSE:To improve insulation of an intersection part between a gate wiring and a source siring, to suppress yield of leakage between a gate and source and to improve the yield rate of a TFT array, by providing two insulating layers, which hold a semiconductor layer that is a constituting film of the TFT, at the overlapped part of the source wiring and the gate wiring. CONSTITUTION:A gate electrode 102 and a source electrode 107 of a thin film transistor (TFT) are provided on a substrate 101. A gate wiring 103 and a source wiring 108, which commonly link the electrodes 102 and 107, are intersected at a overlapping region. Both insulating layers 104 and 106, which hold a semiconductor layer that is a constituting film of the TFT, are provided at the overlapped region. For example, a TFT array is formed on the supporting substrate such as the glass substrate 101 and arranged in correspondence with the intersection of the gate wiring 103 and the source wiring 108. An SiNx film, which is a second insulating layer 106, is deposited on an a-Si layer 105, which is the semiconductor layer of the TFT. Then, one end part of the layer 106 is extended to the upper part of the source wiring 108 along the gate wiring 103. The second insulating layer 106 is provided at the intersecting part of the gate wiring 103 and the source wiring 108.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は、製造の歩留りの向上を図った構造を有する薄
膜トランジスタ（以下Ｔ　Ｐ　Ｔと略す）アレイに関す
る。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a thin film transistor (hereinafter abbreviated as TPT) array having a structure designed to improve manufacturing yield.

（従来技術） 近年、液晶のアクティブマ）　ＩＪクス表示において、
絶縁性基板−ににＴ　Ｐ　Ｔをマトリクス状に形成し２
’ｌアクテイブ・マトリクス基板の研究が活発に行なわ
れている。ＴＦＴに用いられる半導体材料としては、ポ
リＳｉ、　ａ（アモルファス）−８１、′ｒ’ｅ　、　
ＣｄＳｅ等がある０ａ−ｓｉを用いたＴＦＴの構造の一
例を第７図の部分断面図及び第８図の部分平面図に示す
。第７図は、第８図のＡ−Ａ線での断面を示す。ガラス
基板ｌの上に、ゲート電極２．２．　を連結するゲート
配線３を膜厚２，０００〜３．０００λのＴａ、Ｍｏ、
Ｔｉ、Ａ／＝等の金属により形成する。ガラス基板１及
びゲート電極２上に堆積されるゲート絶縁膜４げ、プラ
ズマＣＶＤ法によって形成した膜厚ｊ、０００〜２，０
００只の窒化シリコン（以下ＳｉＮｘと略す）膜である
（第８図においては、図示しない。）。ＴＦＴの半導体
層としてゲート絶縁膜４−にに堆積されるａ−８ｉ層５
は、プラズマＣＶｒ）法にヨＤｆｆｌ厚１　ｏ　ｏＸ　
〜３．ｏｏｏＸｔｃ形ｒｖする。ａ−８ｉ層５上には第
２の絶縁膜６として２．０００〜３，０ＯＯＡのＳｉＮ
ｘ膜がプラズマｃｖＤ法により形成される。ソース電極
７及びソース電極７を連結するソース配線８げゲート配
線３に直交して形成される。ソース配線８にはソース電
極７と接続される分枝部８ａが１定ピッチで並設され、
Ｔ　Ｆ　Ｔは分枝部８ａを中心に形成される。ソース電
極７とドレイン電極９とは、ともに膜厚２，０００〜１
０，０ＯＯＡのＴａ、Ｍｏ、Ｔｉ、Ａ７等の金属により
形成する。なお、ソース電極７及びドレイン電極９とａ
−５ｉ膜５の間に、Ｐ（リン）をドープしたＢＵ’Ｊ５
００〜２，０ＯＯＸ（７）ａ−５ｉ膜１ｏを介在サセる
と、ソース電極７、ドレイン電極９とａ−５ｉ層５のオ
ーミックコンタクトがとれ、好ましい。このようにし７
て、ゲート配線３とソース配線８との交点毎にＴ　Ｐ　
Ｔがアレイ状に形成される。さらに、各Ｔ　Ｐ　Ｔに対
応し７て、酸化インジウム等の透明導電膜から成る絵素
電極１１がドレイン電極９に接１−７で形成される。(Prior art) In recent years, liquid crystal activema) In IJ display,
Forming TPT in a matrix on an insulating substrate 2
Active matrix substrate research is being actively conducted. Semiconductor materials used for TFTs include poly-Si, a (amorphous)-81, 'r'e,
An example of the structure of a TFT using Oa-si containing CdSe or the like is shown in the partial cross-sectional view of FIG. 7 and the partial plan view of FIG. 8. FIG. 7 shows a cross section taken along line A-A in FIG. 8. On the glass substrate l, gate electrodes 2.2. The gate wiring 3 connecting the
It is formed from a metal such as Ti or A/=. The gate insulating film 4 deposited on the glass substrate 1 and the gate electrode 2 has a film thickness j, 000 to 2,0, formed by plasma CVD method.
This is a silicon nitride (hereinafter abbreviated as SiNx) film of 0.00 mm (not shown in FIG. 8). The a-8i layer 5 is deposited on the gate insulating film 4 as a semiconductor layer of the TFT.
For plasma CVr) method, Dffl thickness 1 o oX
~3. oooXtc type rv. On the a-8i layer 5, a SiN film of 2.000 to 3.0 OOA is formed as a second insulating film 6.
The x film is formed by plasma CVD method. A source electrode 7 and a source line 8 connecting the source electrodes 7 are formed perpendicularly to the gate line 3 . Branch portions 8a connected to the source electrode 7 are arranged in parallel at a constant pitch on the source wiring 8,
T F T is formed around the branch portion 8a. Both the source electrode 7 and the drain electrode 9 have a film thickness of 2,000 to 1
It is formed from a metal such as Ta, Mo, Ti, A7, etc. of 0.0OOA. Note that the source electrode 7 and the drain electrode 9 and a
-BU'J5 doped with P (phosphorus) between the -5i films 5
00 to 2,0OOX (7) If the a-5i film 1o is interposed, ohmic contact can be established between the source electrode 7, the drain electrode 9, and the a-5i layer 5, which is preferable. In this way 7
T P at each intersection between the gate wiring 3 and the source wiring 8
T is formed in an array. Further, a picture element electrode 11 made of a transparent conductive film such as indium oxide is formed at 1-7 corresponding to each TPT in contact with the drain electrode 9.

（発明が解決しようとする問題点） ＴＦＴアレイを用いたアクティブ・マトリクス基板にお
いては、マトリクスの各配線ごとに共通のゲート配線か
らシグナル信号を入力し、共通のソース配線からデータ
信号を入力する。ゲート配線占ソース配線との交点は多
数であり、例えは２５０Ｘ２５０マトリクスにおいては
、６２，５００ケ所存在する。この多数の交点のうち１
ケ所でもゲート・ソース間にリークが生じると必然的に
該当するゲート配線とソース配線で表示に際１、て十字
型のライン欠陥が発生し、実用に耐えない表示となり、
アクティブ・マトリクス基板の歩留りはゼロとなる。こ
のため、ゲート配線とソース配線の数が増すにつれてゲ
ート・ソース間の絶縁の確実性かより一層要求されるこ
ととなる。(Problems to be Solved by the Invention) In an active matrix substrate using a TFT array, a signal signal is inputted from a common gate wiring for each wiring of the matrix, and a data signal is inputted from a common source wiring. There are many intersections between the gate line and the source line, for example, in a 250x250 matrix, there are 62,500 points. One of these many intersections
If leakage occurs between the gate and source at any point, a cross-shaped line defect will inevitably occur in the corresponding gate wiring and source wiring, resulting in a display that is not suitable for practical use.
The yield of active matrix substrates is zero. Therefore, as the number of gate wirings and source wirings increases, the reliability of insulation between the gate and the source becomes even more required.

（問題点を解決するだめの手段） 本発明者らは、ゲート・ソース間のリーク箇所を種々の
方法によって調べた結果、ゲート・ソース間のリークが
、ゲートのエツジ（縁部）とソース七が交差する部分（
第５図における胴線部分）において特に多発することを
見い出し７た。この原因汀、ゲート絶縁膜の膜厚がゲー
ト電極の膜厚より大きいか又は同じ程度であるゆえに、
ゲート配線のエツジの部分の膜厚が薄くなって耐圧が低
下し２、さらに、ゲート絶縁膜の膜質が平坦な部分と段
差部分とで異なり、段差部分の方が絶縁性の面で劣るた
めと考えられる。(Means for solving the problem) As a result of investigating the leakage points between the gate and the source using various methods, the present inventors found that the leakage between the gate and the source is caused by the edges of the gate and the source. The part where (
It has been found that this phenomenon occurs particularly frequently in the body line area in Fig. 5). The reason for this is that the thickness of the gate insulating film is greater than or approximately the same as that of the gate electrode.
This is because the film thickness at the edges of the gate wiring becomes thinner and the breakdown voltage decreases2.Furthermore, the film quality of the gate insulating film is different between flat parts and stepped parts, and the stepped parts are inferior in terms of insulation. Conceivable.

本発明の目的は、ＴＦＴアレイの製造の歩留りを向」ニ
ジ得るＴＦＴアレイ構造を提供することにある。即ち、
本発明の゛ｒＦＴアレイは絶縁性基板−ににゲート電極
、ゲート絶縁膜、半導体膜、第２の絶縁膜、ソース電極
、ドレイン電極を順次積層してアレイ状に形成、される
゛「ＦＴ槽構造おいて、ソース配線とゲート配線の重畳
部にも第２の絶縁膜を介在させたことを特徴とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a TFT array structure that can improve the manufacturing yield of TFT arrays. That is,
The FT array of the present invention is formed by sequentially stacking a gate electrode, a gate insulating film, a semiconductor film, a second insulating film, a source electrode, and a drain electrode on an insulating substrate in an array shape. The structure is characterized in that a second insulating film is also interposed in the overlapping portion of the source wiring and the gate wiring.

（発明の効果） 土肥構我とするこ吉により、本発明においては、ゲート
配線とソース配線間の交差部の絶縁性を向−１−させ、
ゲート・ソース間のリークの発生を抑制御−て゛ｒＦＴ
アレイの歩留りを向」ニさせている。従ってこの’「Ｆ
　Ｔアレイ基板を用いた液晶表示装置の製作が容易とな
り信頼性が高くなる。(Effects of the Invention) According to Doi Kaga and Toru Kokichi, in the present invention, the insulation of the intersection between the gate wiring and the source wiring is improved.
Controls the occurrence of leakage between the gate and source.
This is driving the yield of arrays forward. Therefore, this 'F
A liquid crystal display device using a T-array substrate can be manufactured easily and has high reliability.

〈実施例１〉 第１図は、本発明の１実施例を示すＴ　Ｆ　Ｔアレイ基
板の部分平面図である。第２図は、第１図のＢ−Ｂ線断
面図（ゲート配線１０３とソース配線１０８の交差部の
部分断面図）である。Ｔ　Ｆ　′ｒアレイはガラス基板
１０１等の支持基板−ヒに形成され、ゲート配線＋０８
とソース配線１０８の交点に対応して配置される。本実
施例では第２の絶縁層＋０６であるＳｉＮｘ膜をＴ　Ｆ
　Ｔの半導体層であるａ−５ｉ層１０５」―に堆積した
後、その片縁部をゲート配ｍ１０３に沿ってソース配線
１０８の上方捷で延在さぜ、ゲート配線＋０３とソース
配線１０８の交差する部分に第２の絶縁層１０６を介挿
することにより、ゲート・ソース間のリークを大幅に減
少させている。ソース配線＋０８の分枝部にはＴＦＴの
ソース電極が連結さね一１ＴＦＴのドレイン電極１０９
には絵素電極１１０が連結さねでいる。尚、ゲート配線
１０３とソース配線１０８の交差部ＶＣさらに半導体層
であるａ−８ｉ層１０５を介在させるとゲート・ソース
間のリークをより減少させることができる。<Embodiment 1> FIG. 1 is a partial plan view of a TFT array substrate showing one embodiment of the present invention. FIG. 2 is a sectional view taken along the line BB in FIG. 1 (a partial sectional view of the intersection of the gate wiring 103 and the source wiring 108). The T F'r array is formed on a support substrate such as the glass substrate 101, and the gate wiring +08
and the source wiring 108. In this example, the SiNx film which is the second insulating layer +06 is T F
After depositing on the a-5i layer 105'' which is a semiconductor layer of T, one edge thereof is extended along the gate wiring m103 at the upper part of the source wiring 108, and the gate wiring +03 and the source wiring 108 intersect. By interposing the second insulating layer 106 in the portion where the gate is connected, leakage between the gate and the source is significantly reduced. The source electrode of the TFT is connected to the branch part of the source wiring +08.
A pixel electrode 110 is connected to the pixel electrode 110 . Note that by interposing the a-8i layer 105, which is a semiconductor layer, at the intersection VC between the gate wiring 103 and the source wiring 108, leakage between the gate and the source can be further reduced.

第１図ｒ（示した構造を有するＴＦＴアレイは例えば第
３図（Ａ）〜（Ｄ）に示すように製造される。第３図（
Ａ）〜（Ｄ）　ｔ、ｃ示すＴ　Ｐ　Ｔ製造工程の部分断
面図は第１図のＴ　Ｐ　ＴにおいてはＣ−Ｃ線の断面図
を示す。A TFT array having the structure shown in FIG. 1r is manufactured, for example, as shown in FIGS.
A) to (D) t and c are partial cross-sectional views of the TPT manufacturing process shown in FIG.

まず、ガラス基＆　Ｉ　０　＋−＋：Ｖｃ２，０００λ
厚のＴａ（タンタル）層をスパッタリングにより全面に
被着し、ホトエツチングによって第１図に示すようなゲ
ート配線１０３の形にパターン化して、第３図（Ａ）に
示すようにゲート電極１０２を形成する。このゲート電
極Ｍ１２１−に後述する如く半導体層が堆積され、ＴＦ
Ｔの動作部が形成される。次に第３図（Ｂ）に示すよう
に、プラズマＣＶＤ法によりゲート絶縁膜１０４となる
ｇ、ｏ　ｏ　ｏ　Ｘ厚のＳｉＮｘ膜、半導体層となる１
５００久層のａ−５ｉ層１０５及び第２の絶縁膜１０６
である２、０００　Ｘ厚のＳｉＮｘ膜を全面にわをって
連続的に被着し、ホトエツチングにより−１一部ＳｉＮ
ｘ膜を第１図に示す第２の絶縁膜１０６の形にパターン
化する。即ち、第２の絶縁膜１０６はゲート配線ｌ０Ｂ
Ｋ沿ってソース配線１０８との交差部分の直」−丑で延
設される。さらに第３図（Ｃ）に示すようにａ−５ｉ層
１０５もホトエツチングにより第１図に示すａ−８ｉ層
１０５の形にパターン化する。このａ−５ｉ層＋０５も
上記第２の絶縁膜１０６と同様にソース配線１０８との
交差部まで延設される。次に第３図（Ｄ）　Ｋ示すよう
に、プラズマＣＶＤ法によりＰ（リン）をドープしたａ
−５ｉ層を＋、ｏｏｏＸ引き続きスパッタリングにより
Ｔｉ（−Ｆ−夕ｙ）層を１，０ＯＯＸ　、　Ｍｏ　（モ
ＩＪブデン）層を２，０ＯＯＸ連続して三層に堆積し、
ホトエツチングにより第１図に示すソース配線１０８及
びドレイン電極１０９の形にパターン化してａ−５ｉ層
、Ｔｉ層及びＭｏ層の三層構造ソース電極１０７及びド
レイン電極１０９とすることによりＴＦＴが形成される
。最後にスパッタリングにより３．ｏ　ｏ　ｏ　Ｘの酸
化インジウム膜を堆積した後、ホトエツチングによりパ
ターン化して絵素電極１１０を形成する。First, glass group & I 0 +-+: Vc2,000λ
A thick Ta (tantalum) layer is deposited over the entire surface by sputtering, and patterned by photoetching into the shape of a gate wiring 103 as shown in FIG. 1 to form a gate electrode 102 as shown in FIG. 3(A). do. A semiconductor layer is deposited on this gate electrode M121- as described later, and the TF
A working part of T is formed. Next, as shown in FIG. 3(B), a SiNx film with a thickness of g, o o o x, which will become the gate insulating film 104, and 1, which will become the semiconductor layer, are formed by plasma CVD.
500 layers of a-5i layer 105 and second insulating film 106
A SiNx film with a thickness of 2,000X was deposited continuously over the entire surface, and a -1 part SiNx film was photo-etched.
The x film is patterned into the shape of the second insulating film 106 shown in FIG. That is, the second insulating film 106 is connected to the gate wiring l0B.
It is extended along the line K directly at the intersection with the source line 108. Furthermore, as shown in FIG. 3(C), the a-5i layer 105 is also patterned into the shape of the a-8i layer 105 shown in FIG. 1 by photoetching. This a-5i layer +05 also extends to the intersection with the source wiring 108, similarly to the second insulating film 106. Next, as shown in FIG. 3(D), a
-5i layer +, oooX followed by sputtering to deposit a Ti (-F-Y) layer of 1,000X and a Mo (MoIJ Budden) layer of 2,000X in three consecutive layers.
A TFT is formed by patterning the source wiring 108 and drain electrode 109 shown in FIG. 1 by photoetching to form a three-layer structure source electrode 107 and drain electrode 109 of an a-5i layer, a Ti layer, and a Mo layer. . Finally, by sputtering 3. After depositing an indium oxide film of o o o x, it is patterned by photoetching to form a picture element electrode 110.

以−１−の製造工程を介して製作されるＴＦＴはガラス
基板＋０１上にマトリックス状に配列されたゲート配線
＋０３とソース配線１０８の各交点に対応して配置され
、ＴＦＴアレイ基板となる。ゲート配線１０３にシグナ
ル信号、ソース配線１０８にデータ信号を入力すること
によりＴＦＴがマトリクス駆動される。即ち、ゲート配
線■０３のシグナル信号はゲート電極＋０２より各ライ
ン毎に’ｆ’　Ｆ　Ｔにゲート電圧として印加され、ソ
ース配線１０８のデータ信号は分枝部を介して三層構造
ソース電極１０７より各ライン毎にＴ　Ｐ　Ｔにデータ
電圧として印加される。このデータ電圧がａ−５ｉ層＋
０５を介してシグナル信号で同期制御を受け、三層構造
ドレイン電極＋０９より絵素電極１１０に印加される。The TFTs manufactured through the manufacturing process described in -1- below are arranged corresponding to each intersection of the gate wiring +03 and the source wiring 108 arranged in a matrix on the glass substrate +01, thereby forming a TFT array substrate. By inputting a signal signal to the gate wiring 103 and a data signal to the source wiring 108, the TFTs are driven in a matrix. That is, the signal signal of the gate wiring 03 is applied as a gate voltage to 'f' F T for each line from the gate electrode +02, and the data signal of the source wiring 108 is applied from the three-layer structure source electrode 107 via the branch part. A data voltage is applied to TPT for each line. This data voltage is the a-5i layer +
The signal is synchronously controlled via signal signal 05, and is applied to the picture element electrode 110 from the three-layer structure drain electrode +09.

ソース電極１０７及びドレイン電極１０・９のａ−３ｉ
層はＴＦＴ半導体層であるａ−５ｉ　ｆｆｉ　ｌ　０５
とオーミックコンタクトを形成し、Ｔｉ層は密着性及び
電極の機械的強度を向−１−させる。a-3i of source electrode 107 and drain electrodes 10 and 9
The layer is a TFT semiconductor layer a-5i ffil 05
The Ti layer improves adhesion and mechanical strength of the electrode.

〈実施例２〉 第４図は、本発明の他の実施例を示すＴ　Ｆ　Ｔアレイ
基板の部分平面図である。第５図は第４図のＤ−Ｄ線断
面図（ゲート配線２０３とソース配線２０８の交差部の
部分断面図）である。実施例１同様に第２の絶縁層２０
６をパターン化する際にこれを２分割し、ＴＦＴ側に位
置する絶縁層２０６ａとソース配線２０８−ｔ：に位置
する絶縁層２０６ｂとする。即ち、ゲート配線２０３と
ソース配線２０８の交差する部分に第２の絶縁層２０６
）＋を残存させる。本実施例では第２の絶縁層２０６を
５ｉ０２（酸化シリコン）膜で形成しており、ゲート・
ソース間のリークを大幅に減少させている。<Embodiment 2> FIG. 4 is a partial plan view of a TFT array substrate showing another embodiment of the present invention. FIG. 5 is a sectional view taken along the line DD in FIG. 4 (a partial sectional view of the intersection of the gate wiring 203 and the source wiring 208). As in Example 1, the second insulating layer 20
When patterning 6, it is divided into two to form an insulating layer 206a located on the TFT side and an insulating layer 206b located on the source wiring 208-t:. That is, the second insulating layer 206 is formed at the intersection of the gate wiring 203 and the source wiring 208.
) + remains. In this embodiment, the second insulating layer 206 is formed of a 5i02 (silicon oxide) film, and the gate and
Leakage between sources has been significantly reduced.

第４図に示した構造を有するＴＦＴアレイは、第６図（
Ａ）〜（Ｄ）に示すように製造される。第６図（Ａ）〜
（Ｄ）に示すＴＦＴ製造工程は、第４図のＥ−Ｅ線断面
に対応している。まず、ガラス基板２０　＋　−１−に
２．ｏｏｏＸ厚のＭｏ層をスパッタリングにより全面に
被着し、ホトエツチングにより第４図に示すゲート配線
２０３の形にパターン化して、第６図（Ａ）に示すよう
なゲート電極＋０２を形成する。次に、第６図（Ｂ）　
Ｋ示すように、プラズマＣＶＤ法により、ゲート絶縁膜
２０４である３、０００　Ｘ厚のＳｉＮｘ膜及びＴ　Ｆ
　Ｔの半導体膜である１、５００λ厚のａ−５ｉ層２０
５を全面に連続的に被着し、ホトエツチングによりａ−
賓層２０５を第４図に示す半導体層の形にパターン化す
る。このａ−５ｉ層２０５けＴｊＴの部分のみに形成さ
れる。さらに、第６図（Ｃ）に示すように、プラズマＣ
ＶＤ法により第２４７）、１［’３ｉ３ｉ　０６　てＡ
る８、０００ＸＩｉ（７）Ｓｉ０２膜を全面に被着し、
ホトエツチングにより第４図に示す如＜ＴＦＴ側の絶縁
層２０６ａとソース配線２０８上の絶縁層２０６　ｂ　
＆Ｕ分割してパターン化する。次に第６図（Ｄ）に示す
ように、プラズマＣＶＤ法によりＰ（リン）をドープし
たａ−５ｉ層を１，０００λ、Ａｔ層を２，０００　Ｘ
連続して被着しホトエツチングにより第４図に示すソー
ス配線２０８及びドレイン電極２０９の形にパターン化
してソース電極２０７及びドレイン電極２０９とし、Ｔ
ＦＴアレイさする。最後にスパンタリングにより３．０
０ＯＡの酸化インジウム膜を形［戊し、ホトエツチング
によりドレイン電極２０９に片端か重畳された絵素電極
２１０の形にパターン化することによりＴＦＴアレイ基
板が作製される。本実施例においては第２の絶縁層２０
６のみを延設してソース配ａ２０８吉ゲート配線２０３
の間に介挿１−、でいる。The TFT array having the structure shown in Fig. 4 is shown in Fig. 6 (
It is manufactured as shown in A) to (D). Figure 6 (A) ~
The TFT manufacturing process shown in (D) corresponds to the cross section taken along the line E--E in FIG. 4. First, 2. An oooX thick Mo layer is deposited on the entire surface by sputtering and patterned by photoetching into the shape of the gate wiring 203 shown in FIG. 4 to form a gate electrode +02 as shown in FIG. 6(A). Next, Figure 6 (B)
As shown in K, a SiNx film with a thickness of 3,000× and T F
A-5i layer 20 with a thickness of 1,500λ, which is a semiconductor film of T
5 was continuously deposited on the entire surface and a-
The base layer 205 is patterned into the shape of a semiconductor layer as shown in FIG. This a-5i layer 205 is formed only in the TjT portion. Furthermore, as shown in FIG. 6(C), plasma C
247), 1['3i3i 06 teA by VD method
8,000XIi(7)Si02 film is deposited on the entire surface,
By photo-etching, as shown in FIG.
&U Divide into patterns. Next, as shown in FIG. 6(D), the a-5i layer doped with P (phosphorus) by the plasma CVD method was heated at 1,000λ, and the At layer was doped at 2,000X.
It is successively deposited and patterned by photo-etching into the shape of the source wiring 208 and drain electrode 209 shown in FIG.
Insert FT array. Finally 3.0 by spantering
A TFT array substrate is fabricated by cutting a 0OA indium oxide film and patterning it into a pixel electrode 210 overlapping the drain electrode 209 at one end by photoetching. In this embodiment, the second insulating layer 20
6 is extended and the source wiring a208 and the gate wiring 203 are connected.
Insert 1-, in between.

【図面の簡単な説明】[Brief explanation of drawings]

第１図及び第４図はそれぞれ本発明の１実施例を示すＴ
ＦＴアレイ基板の要部平面図である。 第２図及び第５図はそれぞれ第１図及び第４図のＢ−Ｂ
断面及びＤ−Ｄ断面図である。 第３図（Ａ）乃至（Ｄ）及び第６図（Ａ）乃至（ｒ））
はそれぞれ第１図及び第４図に示す実施例の製造工程図
である○ 第７図及び第８図はそれぞれ従来のａ−５ｉ・ＴＦＴア
レイ基板の要部断面図及び要部平面図である。 １０１．２０１・絶縁基板、１０２，２０２・・ゲート
電極、ＩＯ３，２０３・ゲート配線、１０４，２０４・
ゲート絶縁膜、１０５，２０５−ａ−８ｉ層、１０６，
２０６・・第２の絶縁層、１０７，２０７・・・ソース
電極、１０８゜２０８・・ソース配線、１０９，２０９
・・ドレイン電極、１１０．２１０・・絵素電極。 代理人　弁理士　福　士　愛　彦（他２名）０■ 簗１図 Ｂ−Ｂ町町図 第２記 （Ａ） 第７′２！FIG. 1 and FIG. 4 each show an embodiment of the present invention.
FIG. 3 is a plan view of the main parts of the FT array substrate. Figures 2 and 5 are B-B of Figures 1 and 4, respectively.
It is a cross section and a DD sectional view. Figure 3 (A) to (D) and Figure 6 (A) to (r))
are manufacturing process diagrams of the embodiment shown in FIG. 1 and FIG. 4, respectively. ○ FIG. 7 and FIG. 8 are a cross-sectional view and a plan view of a main part of a conventional a-5i TFT array substrate, respectively. . 101.201・Insulating substrate, 102,202・・Gate electrode, IO3,203・Gate wiring, 104,204・
Gate insulating film, 105, 205-a-8i layer, 106,
206...Second insulating layer, 107,207...Source electrode, 108°208...Source wiring, 109,209
...Drain electrode, 110.210...Picture element electrode. Agent Patent Attorney Aihiko Fukushi (and 2 others) 0■ Yan 1 Map B-B Town Map No. 2 (A) No. 7'2!

Claims (1)

【特許請求の範囲】 １、基板上に並設された薄膜トランジスタのゲート電極
とソース電極をそれぞれ共通に連結するゲート配線とソ
ース配線が交差する重畳領域にＴＦＴの構成膜である半
導体層を挾持する絶縁層を２層とも介在させたことを特
徴とする薄膜トランジスタアレイ。 ２、特許請求の範囲第１項において、 上記半導体層がアモルファスシリコン薄膜である薄膜ト
ランジスタアレイ。 ３、特許請求の範囲第１項において、 上記絶縁層が窒化シリコン膜である薄膜トランジスタア
レイ。 ４、特許請求の範囲第１項において、 上記絶縁層が酸化シリコン膜である薄膜トランジスタア
レイ。[Claims] 1. A semiconductor layer, which is a constituent film of a TFT, is sandwiched in an overlapping region where a gate wiring and a source wiring intersect, which commonly connect the gate electrodes and source electrodes of thin film transistors arranged in parallel on a substrate. A thin film transistor array characterized in that two insulating layers are interposed. 2. The thin film transistor array according to claim 1, wherein the semiconductor layer is an amorphous silicon thin film. 3. The thin film transistor array according to claim 1, wherein the insulating layer is a silicon nitride film. 4. The thin film transistor array according to claim 1, wherein the insulating layer is a silicon oxide film.
JP60270355A 1985-11-27 1985-11-27 Thin film transistor array Pending JPS62126677A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP60270355A JPS62126677A (en) 1985-11-27 1985-11-27 Thin film transistor array
GB8628172A GB2185622B (en) 1985-11-27 1986-11-25 Thin film transistor array
DE19863640174 DE3640174A1 (en) 1985-11-27 1986-11-25 THIN FILM TRANSISTOR ARRANGEMENT
US07/267,680 US4935792A (en) 1985-11-27 1988-11-01 Thin film transistor array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60270355A JPS62126677A (en) 1985-11-27 1985-11-27 Thin film transistor array

Publications (1)

Publication Number Publication Date
JPS62126677A true JPS62126677A (en) 1987-06-08

Family

ID=17485110

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60270355A Pending JPS62126677A (en) 1985-11-27 1985-11-27 Thin film transistor array

Country Status (1)

Country Link
JP (1) JPS62126677A (en)

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63276030A (en) * 1987-05-08 1988-11-14 Hitachi Ltd Liquid crystal display device
JPS6410222A (en) * 1987-07-03 1989-01-13 Asahi Glass Co Ltd Substrate for thin film passive element
JPH01217422A (en) * 1988-02-26 1989-08-31 Seikosha Co Ltd Amorphous silicon thin film transistor array substrate
JPH01259565A (en) * 1988-04-11 1989-10-17 Hitachi Ltd Thin film transistor and manufacture of the same
JPH01271727A (en) * 1988-04-25 1989-10-30 Seikosha Co Ltd Amorphous silicon thin film transistor array
JPH0219840A (en) * 1988-07-08 1990-01-23 Hitachi Ltd Manufacture of active matrix panel
JPH03222370A (en) * 1990-01-26 1991-10-01 Mitsubishi Electric Corp Thin film transistor
JPH04190330A (en) * 1990-11-26 1992-07-08 Semiconductor Energy Lab Co Ltd Driving method for display device
US5899547A (en) * 1990-11-26 1999-05-04 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and driving method for the same
US5933205A (en) * 1991-03-26 1999-08-03 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method for driving the same
US5956105A (en) * 1991-06-14 1999-09-21 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method of driving the same
US6013928A (en) * 1991-08-23 2000-01-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having interlayer insulating film and method for forming the same
US6195139B1 (en) 1992-03-04 2001-02-27 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device
US6242758B1 (en) 1994-12-27 2001-06-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device employing resinous material, method of fabricating the same and electrooptical device
US6778231B1 (en) 1991-06-14 2004-08-17 Semiconductor Energy Laboratory Co., Ltd. Electro-optical display device
US6975296B1 (en) 1991-06-14 2005-12-13 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method of driving the same
US7154147B1 (en) 1990-11-26 2006-12-26 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and driving method for the same
JP2007304557A (en) * 2006-05-09 2007-11-22 Lg Philips Lcd Co Ltd Liquid crystal display and method of fabricating the same
US7554616B1 (en) 1992-04-28 2009-06-30 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method of driving the same
JP2012074596A (en) * 2010-09-29 2012-04-12 Toppan Printing Co Ltd Thin-film transistor, image display device having thin-film transistor, method of manufacturing thin-film transistor, and method of manufacturing image display device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS599941A (en) * 1982-07-08 1984-01-19 Matsushita Electric Ind Co Ltd Thin-film semiconductor device and its manufacture
JPS60261174A (en) * 1984-06-07 1985-12-24 Nippon Soken Inc Matrix array

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS599941A (en) * 1982-07-08 1984-01-19 Matsushita Electric Ind Co Ltd Thin-film semiconductor device and its manufacture
JPS60261174A (en) * 1984-06-07 1985-12-24 Nippon Soken Inc Matrix array

Cited By (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63276030A (en) * 1987-05-08 1988-11-14 Hitachi Ltd Liquid crystal display device
JPS6410222A (en) * 1987-07-03 1989-01-13 Asahi Glass Co Ltd Substrate for thin film passive element
JPH01217422A (en) * 1988-02-26 1989-08-31 Seikosha Co Ltd Amorphous silicon thin film transistor array substrate
JPH01259565A (en) * 1988-04-11 1989-10-17 Hitachi Ltd Thin film transistor and manufacture of the same
JPH01271727A (en) * 1988-04-25 1989-10-30 Seikosha Co Ltd Amorphous silicon thin film transistor array
JPH0219840A (en) * 1988-07-08 1990-01-23 Hitachi Ltd Manufacture of active matrix panel
JPH03222370A (en) * 1990-01-26 1991-10-01 Mitsubishi Electric Corp Thin film transistor
JPH04190330A (en) * 1990-11-26 1992-07-08 Semiconductor Energy Lab Co Ltd Driving method for display device
US5899547A (en) * 1990-11-26 1999-05-04 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and driving method for the same
US5905555A (en) * 1990-11-26 1999-05-18 Semiconductor Energy Laboratory Co., Ltd. Active matrix type electro-optical device having leveling film
US5946059A (en) * 1990-11-26 1999-08-31 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and driving method for the same
US7154147B1 (en) 1990-11-26 2006-12-26 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and driving method for the same
KR100522960B1 (en) * 1990-11-26 2005-10-24 가부시키가이샤 한도오따이 에네루기 켄큐쇼 A method of manufacturing a display device
US5933205A (en) * 1991-03-26 1999-08-03 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method for driving the same
US5963278A (en) * 1991-03-26 1999-10-05 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method for driving the same
US6975296B1 (en) 1991-06-14 2005-12-13 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method of driving the same
US7928946B2 (en) 1991-06-14 2011-04-19 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method of driving the same
US5956105A (en) * 1991-06-14 1999-09-21 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method of driving the same
US6778231B1 (en) 1991-06-14 2004-08-17 Semiconductor Energy Laboratory Co., Ltd. Electro-optical display device
US6013928A (en) * 1991-08-23 2000-01-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having interlayer insulating film and method for forming the same
US7123320B2 (en) 1992-03-04 2006-10-17 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device
US6195139B1 (en) 1992-03-04 2001-02-27 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device
US6618105B2 (en) 1992-03-04 2003-09-09 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device
US8035773B2 (en) 1992-03-04 2011-10-11 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device
US7554616B1 (en) 1992-04-28 2009-06-30 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method of driving the same
US6242758B1 (en) 1994-12-27 2001-06-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device employing resinous material, method of fabricating the same and electrooptical device
US6429053B1 (en) 1994-12-27 2002-08-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device method of fabricating same, and, electrooptical device
JP2007304557A (en) * 2006-05-09 2007-11-22 Lg Philips Lcd Co Ltd Liquid crystal display and method of fabricating the same
US7825413B2 (en) 2006-05-09 2010-11-02 Lg Display Co., Ltd. Liquid crystal display device and method of fabricating the same
JP2012074596A (en) * 2010-09-29 2012-04-12 Toppan Printing Co Ltd Thin-film transistor, image display device having thin-film transistor, method of manufacturing thin-film transistor, and method of manufacturing image display device

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