JPS62119952A - Integrated circuit device - Google Patents

Integrated circuit device

Info

Publication number
JPS62119952A
JPS62119952A JP60259972A JP25997285A JPS62119952A JP S62119952 A JPS62119952 A JP S62119952A JP 60259972 A JP60259972 A JP 60259972A JP 25997285 A JP25997285 A JP 25997285A JP S62119952 A JPS62119952 A JP S62119952A
Authority
JP
Japan
Prior art keywords
integrated circuit
lead frame
circuit device
resin
island
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60259972A
Other languages
Japanese (ja)
Inventor
Hitoshi Mitani
三谷　仁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60259972A priority Critical patent/JPS62119952A/en
Publication of JPS62119952A publication Critical patent/JPS62119952A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
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    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities

Abstract

PURPOSE:To realize a device occupying but a small area by a method wherein an IC is installed on a lead frame and wiring is accomplished between them, another IC is installed on another lead frame and wiring is accomplished between them, the two lead frames are connected with each other, and the entirely is sealed in resin. CONSTITUTION:An IC element 1 is installed on a first island 4 and connection is made to a lead frame 3 by a bonding wire 7. Next, an IC element 2 is installed on a second island 6 and connection is made to a lead frame 5 by a bonding wire 7. Finally, the lead frames 3 and 5 are connected and sealing is accomplished in resin 8 for the completion of the device. Another method may be employed wherewith IC elements are housed in ceramic packages instead of resin for the realization of a laminate of packages. A plurality of IC elements may be installed on a single lead frame.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は複数の集積回路素子を１つのパッケージ内に収
納した集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit device in which a plurality of integrated circuit elements are housed in one package.

〔従来の技術〕[Conventional technology]

第４図（ａｌは、一つのリードフレームに複数の集積回
路素子を載置し結線した樹脂封止前の従来の集積回路装
置の平面図、同図（ｂ）は同図（ａ）図のＡ−Ａ断面図
である。これらの図において、リードフレームのアイラ
ンド１４に集積回路素子１１．１２をマクントし、ボン
ディングワイヤ７で、リード１７と集積回路素子１１．
１２とを電気的に接続したものでめる。Figure 4 (al is a plan view of a conventional integrated circuit device before resin sealing in which multiple integrated circuit elements are mounted and wired on one lead frame, and Figure 4 (b) is the same as Figure 4 (a)). 3A-A are cross-sectional views. In these figures, an integrated circuit element 11.12 is mounted on an island 14 of a lead frame, and a bonding wire 7 connects a lead 17 and an integrated circuit element 11.12.
12 are electrically connected.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の集積回路装置は、複数の集積回路素子を
同一パッケージ内に収納する場合、占有面積が増大する
欠点がある。例えば、ある四−機能を有する２個の集積
回路素子を第４図の禄に平面的に配置し、各々の素子の
選択は、各々に選択信号を加えて各集積回路素子を使用
する場合や、異なる機能の重子′ｔ″複畝個央裟し、１
個の集積回路装置として利用する場合など、素子の占有
面積やパッケージの容積等が限定されていれば、それら
の収納は非常に困難となる欠点がある。The above-described conventional integrated circuit device has the disadvantage that the occupied area increases when a plurality of integrated circuit elements are housed in the same package. For example, when two integrated circuit elements having a certain four functions are arranged in a plane as shown in FIG. , with different functions of multiple ridges, 1
When used as an individual integrated circuit device, if the area occupied by the device, the volume of the package, etc. are limited, it becomes extremely difficult to store them.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の集積回路装置は、集積回路系子が載置され結線
された第１のリードフレーム上に、別の集積回路系子が
載置され結線された７ｉｐ、２のリードフレームが配置
され、第１と第２のリードフレームは電気的に接続され
、そしてこれらは樹脂で一体に封止されているのである
。In the integrated circuit device of the present invention, a 7IP, 2 lead frame on which another integrated circuit device is placed and connected is arranged on a first lead frame on which an integrated circuit device is placed and connected, The first and second lead frames are electrically connected and are sealed together with resin.

〔実施例〕〔Example〕

本発明について図面を参照して説明する。第１図は本発
明の、第１の実施例の断面図を示したものである。図に
於いて、１，２は第１及び第２の集積回路系子であり、
３，５は第１及び第２のリードフレーム、４，６は第１
及び謝２のリードフレームのアイランド、７はボンゲイ
ンクワイヤ、８は樹脂部である。The present invention will be explained with reference to the drawings. FIG. 1 shows a sectional view of a first embodiment of the present invention. In the figure, 1 and 2 are first and second integrated circuit devices,
3 and 5 are the first and second lead frames, 4 and 6 are the first
7 is a bonding wire, and 8 is a resin part.

本発明の集積回路装置を得る為には、まず、第１のアイ
ランド４に第１の集積回路系子ｌをマウントし、ボンゲ
インクワイヤ７にて第１のリードフレーム３と第１の集
積回路素子１とを電気的に接続する。次に第２のアイラ
ンド６に第２の集積回路素子２をマウントし、ボンディ
ングワイヤ７にて第２のリードフレーム５と第２の集積
回路素子２とを電気的に接続する。最後に第１のリード
フレーム３と第２のリードフレーム５と全熱的又は機械
的に接続した後、樹脂８にて封止する事により本集積回
路装置を得る事ができる。In order to obtain the integrated circuit device of the present invention, first, the first integrated circuit device l is mounted on the first island 4, and the first lead frame 3 and the first integrated circuit are connected by a bonding choir 7. It is electrically connected to element 1. Next, the second integrated circuit element 2 is mounted on the second island 6, and the second lead frame 5 and the second integrated circuit element 2 are electrically connected using bonding wires 7. Finally, after thermally or mechanically connecting the first lead frame 3 and the second lead frame 5, the integrated circuit device can be obtained by sealing with resin 8.

第２図は本発明の第２の実施例の断面図を示したもので
ある。図に於いて、１１．１２は下段側の集積回路系子
であり、２１．２２は上段側の集積回路素子である。１
３．１５は下段と上段のリードフレーム、１４．１５は
下段と上段のリードフレームのアイランド、７はボンデ
ィングワイヤ、１８は樹脂部である。図に示す通り、第
２の実施例は、下段と上段のリードフレーム上の集積回
路素子を複数設けたものでるる。尚、第２の実施例の集
積回路装置を得るための方法については、第１の実施例
と同一方法で得られる。FIG. 2 shows a cross-sectional view of a second embodiment of the invention. In the figure, 11.12 is an integrated circuit element on the lower stage side, and 21.22 is an integrated circuit element on the upper stage side. 1
3.15 is the lower and upper lead frames, 14.15 is the island of the lower and upper lead frames, 7 is a bonding wire, and 18 is a resin part. As shown in the figure, the second embodiment has a plurality of integrated circuit elements on the lower and upper lead frames. Note that the method for obtaining the integrated circuit device of the second embodiment is the same as that of the first embodiment.

第３図は耐湿性及び熱に対する動作特性の向上を図って
、セラミックパッケージに本発明を応用した応用例の断
面図である。図に於いて、１，２は第１及び第２の集積
回路素子であり、３４　、３７は第１及び集２のアイラ
ンド部、３３．３６はセラミックパッケージの基底部、
３５．３８は第１及び第２のリード部、７はボンディン
グワイヤ、３９はセラミックパッケージのキャップであ
る。FIG. 3 is a sectional view of an application example in which the present invention is applied to a ceramic package with the aim of improving moisture resistance and operating characteristics against heat. In the figure, 1 and 2 are the first and second integrated circuit elements, 34 and 37 are the island parts of the first and second integrated circuit elements, 33 and 36 are the base of the ceramic package,
35 and 38 are first and second lead parts, 7 is a bonding wire, and 39 is a cap of the ceramic package.

この応用例を得る為の方法について説明する。A method for obtaining this application example will be explained.

まず第１のセラミックパッケージ基底部３３のアイラン
ド部３４に第１の集積回路索子１をマクントシ、ワイヤ
ポンチインクを行う。次に第２のセラミックパッケージ
基底部３６のアイランド部３７に第２の集積回路索子２
をマウントシ、ワイヤボンディングを行なう。最後に、
セラミックパッケージの基底部３３と３６を重ねて封止
し、基底部３Ｇにキャップ３９で蓋をし封じる事により
、製品が得られる。First, the first integrated circuit cable 1 is attached to the island portion 34 of the first ceramic package base portion 33, and then a wire punch is applied. Next, a second integrated circuit cable 2 is attached to the island portion 37 of the second ceramic package base portion 36.
Mount it and perform wire bonding. lastly,
A product is obtained by overlapping and sealing the base parts 33 and 36 of the ceramic package, and covering and sealing the base part 3G with a cap 39.

〔発明の効果〕〔Effect of the invention〕

以上説明した株に本発明は、従来技術を使って容易に実
現する拳が可能であシ、しかも、４１Ｉ数の集積回路系
子を同一パッケージ内に収納する場合の占有面積の増加
を半分以下におさえる事ができる効果がある。The present invention can be easily realized using the conventional technology, and moreover, the increase in the occupied area when 41I integrated circuit devices are housed in the same package can be reduced to less than half. It has the effect of suppressing

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の第１の実施例の断面図、第２図は本発
明の第２の実施例の断面図、第３図は本発明をセラミッ
クパッケージに応用した一応用例の断面図、第４図（ａ
）は従来の集積回路装置の樹脂封止前の平面図、同図（
ｂ）は同図（ａ）のＡ−Ａ断面図である。 １．２，１１，１２，２１．２２・・・・・・集積回路
素子、３．５，１３，１５・・・・・・リードフレーム
、４，６，１４゜１６・・・・・・アイランド、７・・
・・・・ボンディングワイヤ、８．１８・・・・・・封
止樹脂、３３．３６・・・・・・セラミックパ、ケージ
基底部、３４．３７・・団・アイランド部、３５゜３８
・・・・・・リード部、３９・・・・・・キャップ。 代′理人　弁理士　　内　原　　　晋 （ａ） 第　４　図FIG. 1 is a sectional view of a first embodiment of the present invention, FIG. 2 is a sectional view of a second embodiment of the present invention, and FIG. 3 is a sectional view of an example of application of the present invention to a ceramic package. Figure 4 (a
) is a plan view of a conventional integrated circuit device before resin sealing;
b) is a sectional view taken along line A-A in FIG. 1.2, 11, 12, 21.22... Integrated circuit element, 3.5, 13, 15... Lead frame, 4, 6, 14° 16... Island, 7...
... Bonding wire, 8.18 ... Sealing resin, 33.36 ... Ceramic wire, cage base, 34.37 ... Group/island part, 35° 38
...Lead part, 39...Cap. Representative Patent Attorney Susumu Uchihara (a) Figure 4

Claims (2)

【特許請求の範囲】[Claims] （１）集積回路素子が載置され、かつ、結線されたリー
ドフレームを２段に重ね、さらに、前記上下のリードフ
レームが互いに接続され、樹脂で封止されてなることを
特徴とする集積回路装置。(1) An integrated circuit comprising two stacked lead frames on which integrated circuit elements are placed and connected, and further, the upper and lower lead frames are connected to each other and sealed with resin. Device. （２）上記上下のリードフレームの少くとも一方のリー
ドフレームには、複数の集積回路素子が載置されている
ことを特徴とする特許請求の範囲第１項に記載の集積回
路装置。(2) The integrated circuit device according to claim 1, wherein a plurality of integrated circuit elements are mounted on at least one of the upper and lower lead frames.
JP60259972A 1985-11-19 1985-11-19 Integrated circuit device Pending JPS62119952A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60259972A JPS62119952A (en) 1985-11-19 1985-11-19 Integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60259972A JPS62119952A (en) 1985-11-19 1985-11-19 Integrated circuit device

Publications (1)

Publication Number Publication Date
JPS62119952A true JPS62119952A (en) 1987-06-01

Family

ID=17341484

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60259972A Pending JPS62119952A (en) 1985-11-19 1985-11-19 Integrated circuit device

Country Status (1)

Country Link
JP (1) JPS62119952A (en)

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6431450A (en) * 1987-07-28 1989-02-01 Nec Corp Ic package
EP0409196A2 (en) * 1989-07-18 1991-01-23 Kabushiki Kaisha Toshiba Plastic molded type semiconductor device
US5295045A (en) * 1990-11-14 1994-03-15 Hitachi, Ltd. Plastic-molded-type semiconductor device and producing method therefor
US5587341A (en) * 1987-06-24 1996-12-24 Hitachi, Ltd. Process for manufacturing a stacked integrated circuit package
US5701031A (en) * 1990-04-26 1997-12-23 Hitachi, Ltd. Sealed stacked arrangement of semiconductor devices
US6340846B1 (en) 2000-12-06 2002-01-22 Amkor Technology, Inc. Making semiconductor packages with stacked dies and reinforced wire bonds
US6380616B1 (en) 1998-01-15 2002-04-30 Infineon Technologies Ag Semiconductor component with a number of substrate layers and at least one semiconductor chip, and method of producing the semiconductor component
US6395578B1 (en) 1999-05-20 2002-05-28 Amkor Technology, Inc. Semiconductor package and method for fabricating the same
US6452278B1 (en) 2000-06-30 2002-09-17 Amkor Technology, Inc. Low profile package for plural semiconductor dies
US6472758B1 (en) 2000-07-20 2002-10-29 Amkor Technology, Inc. Semiconductor package including stacked semiconductor dies and bond wires
US6531784B1 (en) 2000-06-02 2003-03-11 Amkor Technology, Inc. Semiconductor package with spacer strips
US6552416B1 (en) 2000-09-08 2003-04-22 Amkor Technology, Inc. Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring
US6577013B1 (en) 2000-09-05 2003-06-10 Amkor Technology, Inc. Chip size semiconductor packages with stacked dies
US6642610B2 (en) 1999-12-20 2003-11-04 Amkor Technology, Inc. Wire bonding method and semiconductor package manufactured using the same
WO2005013364A2 (en) * 2003-07-28 2005-02-10 Infineon Technologies Ag Electronic component and panel for producing the same
US20160379933A1 (en) * 2007-02-21 2016-12-29 Amkor Technology, Inc. Semiconductor package in package

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5587341A (en) * 1987-06-24 1996-12-24 Hitachi, Ltd. Process for manufacturing a stacked integrated circuit package
JPS6431450A (en) * 1987-07-28 1989-02-01 Nec Corp Ic package
EP0409196A2 (en) * 1989-07-18 1991-01-23 Kabushiki Kaisha Toshiba Plastic molded type semiconductor device
USRE37539E1 (en) * 1990-04-26 2002-02-05 Hitachi, Ltd. Sealed stacked arrangement of semiconductor devices
US5701031A (en) * 1990-04-26 1997-12-23 Hitachi, Ltd. Sealed stacked arrangement of semiconductor devices
US5295045A (en) * 1990-11-14 1994-03-15 Hitachi, Ltd. Plastic-molded-type semiconductor device and producing method therefor
US6380616B1 (en) 1998-01-15 2002-04-30 Infineon Technologies Ag Semiconductor component with a number of substrate layers and at least one semiconductor chip, and method of producing the semiconductor component
US6395578B1 (en) 1999-05-20 2002-05-28 Amkor Technology, Inc. Semiconductor package and method for fabricating the same
US6762078B2 (en) 1999-05-20 2004-07-13 Amkor Technology, Inc. Semiconductor package having semiconductor chip within central aperture of substrate
US6803254B2 (en) 1999-12-20 2004-10-12 Amkor Technology, Inc. Wire bonding method for a semiconductor package
US6642610B2 (en) 1999-12-20 2003-11-04 Amkor Technology, Inc. Wire bonding method and semiconductor package manufactured using the same
US6531784B1 (en) 2000-06-02 2003-03-11 Amkor Technology, Inc. Semiconductor package with spacer strips
US6452278B1 (en) 2000-06-30 2002-09-17 Amkor Technology, Inc. Low profile package for plural semiconductor dies
US6650019B2 (en) 2000-07-20 2003-11-18 Amkor Technology, Inc. Method of making a semiconductor package including stacked semiconductor dies
US6472758B1 (en) 2000-07-20 2002-10-29 Amkor Technology, Inc. Semiconductor package including stacked semiconductor dies and bond wires
US6577013B1 (en) 2000-09-05 2003-06-10 Amkor Technology, Inc. Chip size semiconductor packages with stacked dies
US6552416B1 (en) 2000-09-08 2003-04-22 Amkor Technology, Inc. Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring
US6340846B1 (en) 2000-12-06 2002-01-22 Amkor Technology, Inc. Making semiconductor packages with stacked dies and reinforced wire bonds
WO2005013364A2 (en) * 2003-07-28 2005-02-10 Infineon Technologies Ag Electronic component and panel for producing the same
WO2005013364A3 (en) * 2003-07-28 2005-03-24 Infineon Technologies Ag Electronic component and panel for producing the same
US7524699B2 (en) 2003-07-28 2009-04-28 Infineon Technologies Ag Electronic component and a panel
US20160379933A1 (en) * 2007-02-21 2016-12-29 Amkor Technology, Inc. Semiconductor package in package
US9768124B2 (en) 2007-02-21 2017-09-19 Amkor Technology, Inc. Semiconductor package in package

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