JPS6211783B2 - - Google Patents
Info
- Publication number
- JPS6211783B2 JPS6211783B2 JP54172908A JP17290879A JPS6211783B2 JP S6211783 B2 JPS6211783 B2 JP S6211783B2 JP 54172908 A JP54172908 A JP 54172908A JP 17290879 A JP17290879 A JP 17290879A JP S6211783 B2 JPS6211783 B2 JP S6211783B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- metal film
- forming
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910052751 metal Inorganic materials 0.000 claims description 24
- 239000002184 metal Substances 0.000 claims description 24
- 238000005530 etching Methods 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 16
- 238000000034 method Methods 0.000 description 9
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 4
- 239000000758 substrate Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
本発明は、多層配線を有する半導体装置を製造
する方法の改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a method of manufacturing a semiconductor device having multilayer wiring.
従来、多層配線を形成する方法として、例え
ば、第１図に見られるように、第１層目配線１を
絶縁膜２で覆い、該絶縁膜２にコンタクト穴
（via ホール）２ａを形成し、その後、第２層目
配線３を形成するものが知られている。 Conventionally, as a method for forming multilayer wiring, for example, as shown in FIG. 1, a first layer wiring 1 is covered with an insulating film 2, and a contact hole (via hole) 2a is formed in the insulating film 2. It is known that the second layer wiring 3 is then formed.
しかしながら、これに依ると、コンタクト穴２
ａを配線１上に正確に位置合せして形成しなけれ
ばならないこと、また、エツチング精度を出し難
いこと、更にまた、矢印で示したようなカバレイ
ジの悪さに依り配線３が断線し易いことなどの問
題がある。 However, according to this, the contact hole 2
a must be formed by accurately aligning it on the wiring 1, it is difficult to achieve etching accuracy, and furthermore, the wiring 3 is easily disconnected due to poor coverage as shown by the arrow. There is a problem.
本発明は、多層配線を形成する際に、配線間を
結ぶためのコンタクト穴を形成しなくて済むよう
に、また、段差に基因する上層配線の断線が起ら
ないようにするものであり、以下これを詳細に説
明する。 The present invention eliminates the need to form contact holes to connect interconnects when forming multilayer interconnects, and prevents disconnection of upper layer interconnects due to differences in level. This will be explained in detail below.
第２図乃至第８図は本発明一実施例を説明する
為の工程要所に於ける半導体装置の要部側断面説
明図であり、次に、これ等の図を参照しつつ記述
する。 2 to 8 are side cross-sectional views of essential parts of a semiconductor device at key points in the process for explaining one embodiment of the present invention, and the following description will be made with reference to these figures.
第２図参照
(1) 基板１１上に例えばアルミニウムの第１層目
配線膜１２と、エツチング・ストツパ膜１３
と、例えばアルミニウムからなる配線間コンタ
クト用金属膜１４を形成する。この際適用する
技法としては蒸着法、スパツタ法など適宜に採
用して良い。また、エツチング・ストツパ膜１
３は例えばチタン、チタン・タングステン、シ
リコンなど適当なものを選ぶことができる。Refer to FIG. 2 (1) A first layer wiring film 12 made of, for example, aluminum and an etching stopper film 13 are placed on the substrate 11.
Then, an inter-wiring contact metal film 14 made of, for example, aluminum is formed. As a technique to be applied at this time, a vapor deposition method, a sputtering method, or the like may be employed as appropriate. In addition, the etching stopper film 1
3 can be selected from any suitable material, such as titanium, titanium/tungsten, or silicon.
第３図参照
(2) パターンのエツジを鋭角にする為、ドライ・
エツチング法を採用し、フオト・レジスト膜１
５をマスクとして金属膜１４、ストツパ膜１
３、配線膜１２のパターニングを行なう。スト
ツパ膜１３をエツチングするにはガスを変更し
たり、場合に依つては、ウエツト・エツチング
法を採つても良い。See Figure 3 (2) To make the edges of the pattern acute, dry
Using the etching method, photo resist film 1
5 as a mask, metal film 14, stopper film 1
3. Patterning the wiring film 12. To etch the stopper film 13, the gas may be changed or, depending on the case, a wet etching method may be used.
第４図参照
(3) 一酸化シリコン、二酸化シリコンなどを配線
膜１２の厚さ分だけ蒸着して絶縁膜１６を形成
する。Refer to FIG. 4 (3) Silicon monoxide, silicon dioxide, or the like is deposited to the thickness of the wiring film 12 to form the insulating film 16.
第５図参照
(4) フオト・レジスト膜１５を溶解して除去す
る。これに依り、その上に在つた絶縁膜１６の
一部も除去されてしまう。Refer to FIG. 5 (4) The photoresist film 15 is dissolved and removed. As a result, a portion of the insulating film 16 existing thereon is also removed.
(5) 新たにフオト・レジスト膜１７を形成する。
これは、コンタクト穴と同様のパターンを有す
るものとする。(5) Form a new photoresist film 17.
This shall have a similar pattern to the contact holes.
第６図参照
(6) フオト・レジスト膜１７をマスクとして金属
膜１４をパターニングする。このときもドラ
イ・エツチング法を適用する。Refer to FIG. 6 (6) The metal film 14 is patterned using the photoresist film 17 as a mask. At this time as well, the dry etching method is applied.
第７図参照
(7) 前記工程(3)と同様にして絶縁膜１８を形成す
る。その厚さは金属膜１４とストツパ膜１３を
加えたものとする。尚、この工程の前に、金属
膜１４の直下に在るもの以外のストツパ膜１３
を除去することは任意である。Refer to FIG. 7 (7) An insulating film 18 is formed in the same manner as in step (3). Its thickness is the sum of the metal film 14 and the stopper film 13. Note that before this step, the stopper film 13 other than the one directly under the metal film 14 is removed.
Removal is optional.
第８図参照
(8) フオト・レジスト膜１７を溶解してその上の
絶縁膜１８をリフト・オフする。Refer to FIG. 8 (8) The photoresist film 17 is dissolved and the insulating film 18 thereon is lifted off.
(9) 第２層目配線膜１９を形成する。この後、同
様な工程を繰返して更に多層の配線を形成する
こともできる。尚、本実施例に於いて、金属膜
１４は、ボンデイング・パツドの一辺の長さが
80〜150〔μｍ〕であるとき、一辺が１〜３
〔μｍ〕程度の大きさで良い。また、絶縁膜１
６，１８の厚さは配線膜１２，金属膜１４など
のそれと一致している必要はなく、80〜120
〔％〕程度の範囲で許容できる。更にまた、材
質もSiOx以外にアルミナ（Al2O3）なども使用
することができる。(9) Form a second layer wiring film 19. Thereafter, similar steps can be repeated to form further multilayer wiring. In this embodiment, the metal film 14 has a length of one side of the bonding pad.
When it is 80 to 150 [μm], one side is 1 to 3
A size of approximately [μm] is sufficient. In addition, insulating film 1
The thickness of the wiring film 12, metal film 14, etc. does not need to be the same as that of the wiring film 12, metal film 14, etc.
It is acceptable within a range of about [%]. Furthermore, other materials such as alumina (Al 2 O 3 ) can be used in addition to SiO x .
ところで、前記説明した実施例に於ける位置合
せ精度を更に容易に向上することができる。次
に、これを第９図乃至第１１図を参照しつつ説明
する。 By the way, the alignment accuracy in the embodiment described above can be further easily improved. Next, this will be explained with reference to FIGS. 9 to 11.
第９図参照
(1) 第１層目配線膜１２、ストツパ膜１３、金属
膜１４を形成した上に最初からコンタクト穴と
同様のパターンを有するフオト・レジスト膜１
７を形成する。Refer to FIG. 9 (1) A photoresist film 1 having a pattern similar to the contact hole from the beginning on which the first layer wiring film 12, stopper film 13, and metal film 14 are formed.
form 7.
第１０図参照
(2) その上に第１層目配線膜１２のエツチング・
パターンを有するフオト・レジスト膜１５を形
成する。このフオト・レジスト膜１５をフオ
ト・レジスト膜１７とは溶解液を異にするもの
とする。フオト・レジスト膜１７が形成されて
いるところに合せてフオト・レジスト膜１５を
形成することは極めて精密になし得る。尚、フ
オト・レジスト膜１５の代りにポリイミド膜な
どを使用することができる。Refer to FIG. 10 (2) On top of that, the first layer wiring film 12 is etched.
A photoresist film 15 having a pattern is formed. The photoresist film 15 and the photoresist film 17 are dissolved in a different solution. It is possible to form the photoresist film 15 very precisely in accordance with the location where the photoresist film 17 is formed. Note that a polyimide film or the like can be used instead of the photoresist film 15.
第１１図参照
(3) フオト・レジスト膜１５をマスクとして金属
膜１４、ストツパ膜１３、第１層目配線膜１２
のパターニングを行なう。Refer to FIG. 11 (3) Using the photoresist film 15 as a mask, the metal film 14, stopper film 13, and first layer wiring film 12 are removed.
Perform patterning.
(4) この後、第４図に関して説明したように絶縁
膜１６を形成し、フオト・レジスト膜１５を除
去することに依るリフト・オフを行なうと第５
図に見られる状態が得られることになるから、
それ以後の工程は前記実施例に従えば良い。(4) Thereafter, as explained with reference to FIG. 4, the insulating film 16 is formed and lift-off is performed by removing the photoresist film 15.
The state shown in the figure will be obtained, so
The subsequent steps may be carried out in accordance with the embodiment described above.
以上の説明で判るように、本発明に依れば、多
層配線を有する半導体装置を製造する場合に於い
て、所定層の配線膜上にエツチング・ストツパ膜
を形成してからその上に配線間コンタクト用金属
膜を形成する工程と、次いで、該金属膜とエツチ
ング・ストツパ膜と配線膜とを配線形状にパター
ニングする工程と、次いで、前記金属膜のみを配
線間コンタクトとして必要な柱状をなすように更
にパターニングする工程と、次いで、その残され
た柱状の金属膜の側周を囲む絶縁膜を形成する工
程とが含まれてなるようにしたものであり、これ
に依り、所定層の配線膜とその上層の配線膜とを
コンタクトさせる為のコンタクト穴の形成は不要
になるので、その位置合せ不良やエツチング精度
不良について考慮する必要がなくなり、製造歩留
りは飛躍的に向上する。また、最切に、金属膜と
エツチング・ストツパ膜と配線膜とをパターニン
グしてから更にその金属膜を柱状にパターニング
するようにしているので、柱状になつた金属膜は
必ず前記配線膜上に在り、該金属膜がずれて隣接
配線膜間が短絡するなどの事故は発生することが
ない。更にまた、表面は平坦に形成されるので、
段差に依る配線の切断などは生じない。 As can be seen from the above description, according to the present invention, when manufacturing a semiconductor device having multilayer wiring, an etching stopper film is formed on a wiring film of a predetermined layer, and then an etching stopper film is formed on the wiring film. A step of forming a metal film for contact, then a step of patterning the metal film, an etching stopper film, and a wiring film into a wiring shape, and then forming only the metal film into a necessary columnar shape as an inter-wiring contact. This method includes a step of further patterning the remaining columnar metal film, and a step of forming an insulating film surrounding the periphery of the remaining columnar metal film. Since it is no longer necessary to form a contact hole to make contact between the wiring film and the wiring film in the upper layer, there is no need to consider poor alignment or poor etching accuracy, and the manufacturing yield is dramatically improved. Moreover, since the metal film, the etching stopper film, and the wiring film are first patterned, the metal film is further patterned into a columnar shape, so that the metal film formed into a columnar shape is always placed on the wiring film. Therefore, an accident such as a short circuit between adjacent wiring films due to displacement of the metal film does not occur. Furthermore, since the surface is formed flat,
There is no disconnection of wiring due to differences in level.
第１図は従来例の要部側断面説明図、第２図乃
至第８図は本発明一実施例を説明する為の工程要
所に於ける半導体装置の要部側断面説明図、第９
図乃至第１１図は他の実施例を説明する為の工程
要所に於ける半導体装置の要部側断面説明図であ
る。
図に於いて、１１は基板、１２は配線膜、１３
はストツパ膜、１４は金属膜、１５はフオト・レ
ジスト膜、１６は絶縁膜、１７はフオト・レジス
ト膜、１８は絶縁膜、１９は配線膜である。
FIG. 1 is an explanatory side cross-sectional view of the main part of a conventional example, FIGS.
11A through 11 are explanatory side cross-sectional views of essential parts of a semiconductor device at key points in the process for explaining other embodiments. In the figure, 11 is a substrate, 12 is a wiring film, and 13 is a substrate.
14 is a stopper film, 14 is a metal film, 15 is a photoresist film, 16 is an insulating film, 17 is a photoresist film, 18 is an insulating film, and 19 is a wiring film.
Claims (1)
を形成してからその上に配線間コンタクト用金属
膜を形成する工程と、 次いで、該金属膜とエツチング・ストツパ膜と
配線膜とを配線形状にパターニングする工程と、 次いで、前記金属膜のみを配線間コンタクトと
して必要な柱状をなすように更にパターニングす
る工程と、 次いで、その残された柱状の金属膜の側周を囲
む絶縁膜を形成する工程と が含まれてなることを特徴とする半導体装置の製
造方法。[Scope of Claims] 1. A step of forming an etching stopper film on a wiring film of a predetermined layer, and then forming a metal film for contact between wirings thereon; a step of patterning the metal film into a wiring shape, a step of further patterning only the metal film to form a necessary columnar shape as a contact between the wirings, and a step of surrounding the side periphery of the remaining columnar metal film. 1. A method of manufacturing a semiconductor device, comprising the step of forming an insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17290879A JPS5696845A (en) | 1979-12-28 | 1979-12-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17290879A JPS5696845A (en) | 1979-12-28 | 1979-12-28 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5696845A JPS5696845A (en) | 1981-08-05 |
| JPS6211783B2 true JPS6211783B2 (en) | 1987-03-14 |
Family
ID=15950564
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17290879A Granted JPS5696845A (en) | 1979-12-28 | 1979-12-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5696845A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0828420B2 (en) * | 1986-04-09 | 1996-03-21 | 富士通株式会社 | Method of forming multilayer wiring |
| KR100593126B1 (en) * | 1999-12-29 | 2006-06-26 | 주식회사 하이닉스반도체 | Method of forming a metal wiring in a semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4894866A (en) * | 1972-03-15 | 1973-12-06 |
-
1979
- 1979-12-28 JP JP17290879A patent/JPS5696845A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4894866A (en) * | 1972-03-15 | 1973-12-06 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5696845A (en) | 1981-08-05 |
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