JPS62117355A - Manufacture of integrated circuit - Google Patents

Manufacture of integrated circuit

Info

Publication number
JPS62117355A
JPS62117355A JP60258135A JP25813585A JPS62117355A JP S62117355 A JPS62117355 A JP S62117355A JP 60258135 A JP60258135 A JP 60258135A JP 25813585 A JP25813585 A JP 25813585A JP S62117355 A JPS62117355 A JP S62117355A
Authority
JP
Japan
Prior art keywords
lead
sections
resin
lead frame
section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60258135A
Other languages
Japanese (ja)
Inventor
Yukitetsu Komatsu
幸哲 小松
Osamu Hirohashi
広橋　修
Yoshihiro Shigeta
善弘 重田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP60258135A priority Critical patent/JPS62117355A/en
Publication of JPS62117355A publication Critical patent/JPS62117355A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE:To obtain ICs, which have the same external shape and terminal arrangement thereof forms a pair of reflection symmetry, by casting a resin, separating a connecting section for a lead frame, bending the end section of a lead section in either direction to the surface of the lead section and shaping a terminal. CONSTITUTION:An IC chip 1 is fixed to a die pad section 3 for a lead frame, and electrodes for the chip 1 and lead sections 4 for the lead frame are connected through wire bonding. The lead sections 4 are fastened to a molding die so as to be projected to the center in the thickness direction of a resin body, and a resin is casted. The leads are formed, but the end sections of the lead sections 4 are bent to the side reverse to a semiconductor mounting surface for the lead frame and terminals 7 are shaped in one lead sections while the end sections of the lead sections 4 are bent in the opposite direction in the other lead sections. Consequently, the two molded shapes take a reflection shape. Accordingly, when the two ICs are paired and disposed, terminals having the same terminal number are faced oppositely, thus facilitating connections to the same wiring conductor, then eliminating the possibility of defective wirings.

Description

【発明の詳細な説明】[Detailed description of the invention] 【発明の属する技術分野】[Technical field to which the invention pertains]

一つの配線基板上に固定され、同一端子を同一配線導体
に接続するために鏡映対称の端子配列を有する同一回路
構成の対をなす集積回路の製造方法に関する。The present invention relates to a method for manufacturing a pair of integrated circuits having the same circuit configuration fixed on one wiring board and having a mirror-symmetrical terminal arrangement for connecting the same terminals to the same wiring conductor.

【従来技術とその問題点】[Prior art and its problems]

電子装置を構成するため多数の集積回路を配線基板上に
搭載する場合、集積回路を数列に並べて配列することが
基板面積の小形化のために行われる。その場合、同一回
路構成の集積回路の同一端子を同一配線導体に接続する
ためには鏡映対称の端子配列を有することが有利なこと
は明らかである。しかし、そのような対をなす集積回路
を得るためには、鏡映対称の２種類の半導体チップが必
要であり、鏡映対称のマスクを準備して別個の工程で２
種類の集積回路を製造しなければならなかった。そのた
めこのような集積回路の製造原価の上昇を免れることが
できなかった。When a large number of integrated circuits are mounted on a wiring board to configure an electronic device, the integrated circuits are arranged in several rows in order to reduce the board area. In that case, it is clear that it is advantageous to have a mirror-symmetric terminal arrangement in order to connect the same terminals of integrated circuits with the same circuit configuration to the same wiring conductor. However, in order to obtain such a paired integrated circuit, two types of mirror-symmetric semiconductor chips are required, and mirror-symmetric masks are prepared and the two types are separated in separate steps.
different types of integrated circuits had to be manufactured. Therefore, it has been impossible to avoid an increase in the manufacturing cost of such integrated circuits.

【発明の目的】[Purpose of the invention]

本発明は、上述の問題を解決して同一回路構成で鏡映対
称の端子配列を有して対をなす集積回路を共通の半導体
チップを用いて製造する方法を提供することを目的とす
る。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a method for manufacturing a pair of integrated circuits having the same circuit configuration and mirror-symmetrical terminal arrangement using a common semiconductor chip.

【発明の要点】[Key points of the invention]

本発明によれば、半導体チップの電極をリードフレーム
のリード部と接続し、次いでリード部が型面に平行に型
の空洞の中央に位置するようにリードフレームを固定し
て樹脂を注型したのち、リードフレームの連結部を切り
離し、最後に樹脂より露出したリード部の端部を樹脂に
被覆されたリード部の面に対していずれかの方向に曲げ
て端子を形成することにより、リードフォーミングの方
向により鏡映対称の端子配列を有する対をなす集積回路
を得ることができ、上述の目的が達成される。According to the present invention, the electrodes of the semiconductor chip are connected to the lead parts of the lead frame, and then the lead frame is fixed so that the lead parts are located parallel to the mold surface and in the center of the mold cavity, and resin is cast. After that, the connecting part of the lead frame is separated, and finally the end of the lead part exposed from the resin is bent in either direction against the surface of the lead part covered with resin to form a terminal, leading to lead forming. The orientation of , allows to obtain a paired integrated circuit with a mirror-symmetrical terminal arrangement, and the above-mentioned objective is achieved.

【発明の実施例】[Embodiments of the invention]

第１図は本発明の一実施例により製造された一対のフラ
ットパッケージ集積回路の断面図である。 いずれもＩＣチップ１を接着剤２によりリードフレーム
のダイパッド部３に固着し、ＩＣチップの電極とリード
フレームのリード部４とを金線５のワイヤボンディング
により接続する０次いでリード部４が樹脂体の厚さ方向
の中央の突出するようにモールド型に固定し、樹脂を注
型する。このあとリードフォーミングを行うが、第１図
（ａ）に示すものは、第２図に示した従来の集積回路と
同様にリード部４の端部をリードフレームの半導体装面
と逆の側に直角に曲げて端子７を形成したのに対し、第
１図（ｂｌに示すものはリード部４の端部が反対方向に
曲げられている。この結果第３図に示したような外観を
有し、４辺に端子７を有する集積回路における端子配列
は、第４図に端子番号１〜４４で示したように、第４図
＋ａ＋に示したものと第４図中）に示したものと鏡映対
称になっている。従ってこの両方の集積回路を対にして
並べれば同一端子番号の端子が向かい合うことになり、
同一配線導体への接続が容易で誤配線の虞がなくなる。FIG. 1 is a cross-sectional view of a pair of flat package integrated circuits manufactured in accordance with one embodiment of the present invention. In both cases, the IC chip 1 is fixed to the die pad part 3 of the lead frame with adhesive 2, and the electrode of the IC chip and the lead part 4 of the lead frame are connected by wire bonding with gold wire 5.Then, the lead part 4 is made of resin. It is fixed in a mold so that it protrudes from the center in the thickness direction, and resin is poured into the mold. After this, lead forming is performed, and in the case shown in FIG. 1(a), the end of the lead part 4 is placed on the opposite side of the lead frame from the semiconductor device surface, similar to the conventional integrated circuit shown in FIG. In contrast to the case where the terminal 7 is formed by bending it at a right angle, the end of the lead part 4 shown in FIG. However, the terminal arrangement in an integrated circuit having terminals 7 on four sides is as shown in Fig. 4 with terminal numbers 1 to 44, as shown in Fig. 4+a+ and in Fig. 4). It has mirror symmetry. Therefore, if these two integrated circuits are arranged in pairs, the terminals with the same terminal number will face each other.
Connection to the same wiring conductor is easy, eliminating the risk of incorrect wiring.

【発明の効果】【Effect of the invention】

本発明は、樹脂封止時のリードフレームのリード部の固
定位置を樹脂体の厚さ方向の中央になるようにして、リ
ードフォーミングの方向を変えるのみで同一の外形で端
子配列が鏡映対称の対をなす集積回路を得ることができ
、２種類のマスクを用いた２種類のウェーハプロセスを
必要とすることなく、同一ウェーハから製造できるので
、製造原価を低下させることができ、得られる効果は極
めて大きい。In the present invention, the fixed position of the lead part of the lead frame during resin sealing is set at the center in the thickness direction of the resin body, and the terminal arrangement is mirror-symmetrical with the same external shape by simply changing the direction of lead forming. It is possible to obtain a pair of integrated circuits, and it can be manufactured from the same wafer without the need for two types of wafer processes using two types of masks, so the manufacturing cost can be reduced, and the effects obtained. is extremely large.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例による一対の集積回路の断面
図、第２図は従来の集積回路の断面図、第３図は本発明
により製造される集積回路の外観の一例を示す斜視図、
第４図は本発明の一実施例による一対の集積回路の端子
配列を示す平面図である。 ！＋ＩＣチップ、３Ｉグイバッド部、４；リード部、５
＋Ａｕ線、６Ｉ樹脂、７＋端子。 第１図 第２図FIG. 1 is a sectional view of a pair of integrated circuits according to an embodiment of the present invention, FIG. 2 is a sectional view of a conventional integrated circuit, and FIG. 3 is a perspective view showing an example of the external appearance of an integrated circuit manufactured according to the present invention. figure,
FIG. 4 is a plan view showing the terminal arrangement of a pair of integrated circuits according to an embodiment of the present invention. ! +IC chip, 3I Guibad part, 4; Lead part, 5
+Au wire, 6I resin, 7+ terminal. Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] １）同一回路構成で鏡映対称の端子配列を有して対をな
す集積回路の製造方法であって、半導体チップの電極を
リードフレームのリード部と接続し、次いでリード部が
型面に平行に型の空洞の中央に位置するようにリードフ
レームを固定して樹脂を注型したのち、リードフレーム
の連結部を切離し、最後に樹脂より露出したリード部の
端部を樹脂に被覆されたリード部の面に対していずれか
の方向に曲げて端子を形成することを特徴とする集積回
路の製造方法。1) A method for manufacturing a pair of integrated circuits having the same circuit configuration and a mirror-symmetrical terminal arrangement, in which the electrodes of a semiconductor chip are connected to the lead parts of a lead frame, and then the lead parts are parallel to the mold surface. After fixing the lead frame so that it is located in the center of the mold cavity and pouring resin, the connection part of the lead frame is separated, and finally the end of the lead part exposed from the resin is inserted into the resin-covered lead. A method of manufacturing an integrated circuit, the method comprising forming a terminal by bending the terminal in either direction with respect to the surface of the integrated circuit.
JP60258135A 1985-11-18 1985-11-18 Manufacture of integrated circuit Pending JPS62117355A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60258135A JPS62117355A (en) 1985-11-18 1985-11-18 Manufacture of integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60258135A JPS62117355A (en) 1985-11-18 1985-11-18 Manufacture of integrated circuit

Publications (1)

Publication Number Publication Date
JPS62117355A true JPS62117355A (en) 1987-05-28

Family

ID=17315999

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60258135A Pending JPS62117355A (en) 1985-11-18 1985-11-18 Manufacture of integrated circuit

Country Status (1)

Country Link
JP (1) JPS62117355A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040006180A (en) * 2002-07-11 2004-01-24 삼성전기주식회사 Method for assembling a ic package
US7057273B2 (en) * 2001-05-15 2006-06-06 Gem Services, Inc. Surface mount package

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60220961A (en) * 1984-04-17 1985-11-05 Toshiba Corp Semiconductor memory device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60220961A (en) * 1984-04-17 1985-11-05 Toshiba Corp Semiconductor memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7057273B2 (en) * 2001-05-15 2006-06-06 Gem Services, Inc. Surface mount package
KR20040006180A (en) * 2002-07-11 2004-01-24 삼성전기주식회사 Method for assembling a ic package

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